tjh.dev
+1
-1
arch/arm/Kconfig
+1
-1
arch/arm/Kconfig
···
73
73
select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
74
74
select HAVE_EXIT_THREAD
75
75
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
76
-
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
76
+
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
77
77
select HAVE_FUNCTION_TRACER if !XIP_KERNEL
78
78
select HAVE_GCC_PLUGINS
79
79
select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
+3
-3
arch/arm/Kconfig.debug
+3
-3
arch/arm/Kconfig.debug
···
47
47
48
48
choice
49
49
prompt "Choose kernel unwinder"
50
-
default UNWINDER_ARM if AEABI && !FUNCTION_GRAPH_TRACER
51
-
default UNWINDER_FRAME_POINTER if !AEABI || FUNCTION_GRAPH_TRACER
50
+
default UNWINDER_ARM if AEABI
51
+
default UNWINDER_FRAME_POINTER if !AEABI
52
52
help
53
53
This determines which method will be used for unwinding kernel stack
54
54
traces for panics, oopses, bugs, warnings, perf, /proc/<pid>/stack,
···
65
65
66
66
config UNWINDER_ARM
67
67
bool "ARM EABI stack unwinder"
68
-
depends on AEABI
68
+
depends on AEABI && !FUNCTION_GRAPH_TRACER
69
69
select ARM_UNWIND
70
70
help
71
71
This option enables stack unwinding support in the kernel
+15
-1
arch/arm/boot/compressed/head.S
+15
-1
arch/arm/boot/compressed/head.S
···
1438
1438
1439
1439
@ Preserve return value of efi_entry() in r4
1440
1440
mov r4, r0
1441
-
bl cache_clean_flush
1441
+
1442
+
@ our cache maintenance code relies on CP15 barrier instructions
1443
+
@ but since we arrived here with the MMU and caches configured
1444
+
@ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
1445
+
@ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
1446
+
@ the enable path will be executed on v7+ only.
1447
+
mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
1448
+
tst r1, #(1 << 5) @ CP15BEN bit set?
1449
+
bne 0f
1450
+
orr r1, r1, #(1 << 5) @ CP15 barrier instructions
1451
+
mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
1452
+
ARM( .inst 0xf57ff06f @ v7+ isb )
1453
+
THUMB( isb )
1454
+
1455
+
0: bl cache_clean_flush
1442
1456
bl cache_off
1443
1457
1444
1458
@ Set parameters for booting zImage according to boot protocol
+1
-1
arch/arm/kernel/head-nommu.S
+1
-1
arch/arm/kernel/head-nommu.S
···
133
133
*/
134
134
.text
135
135
__after_proc_init:
136
-
#ifdef CONFIG_ARM_MPU
137
136
M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
138
137
M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
138
+
#ifdef CONFIG_ARM_MPU
139
139
M_CLASS(ldr r3, [r12, 0x50])
140
140
AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
141
141
and r3, r3, #(MMFR0_PMSA) @ PMSA field