tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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pinctrl: zynq: Add a 8 bit wide nand option

The hardware supports a 16 and 8 bit wide NAND bus, let users pick
either.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Jason Gunthorpe and committed by
Linus Walleij 951f033d 96bb12de

+5 -1
+5 -1
drivers/pinctrl/pinctrl-zynq.c
··· 247 247 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 248 248 12, 13, 14, 16, 17, 18, 19, 20, 249 249 21, 22, 23}; 250 + static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7, 251 + 8, 9, 10, 11, 12, 13, 14}; 250 252 /* Note: CAN MIO clock inputs are modeled in the clock framework */ 251 253 static const unsigned int can0_0_pins[] = {10, 11}; 252 254 static const unsigned int can0_1_pins[] = {14, 15}; ··· 447 445 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1), 448 446 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25), 449 447 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand), 448 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8), 450 449 DEFINE_ZYNQ_PINCTRL_GRP(can0_0), 451 450 DEFINE_ZYNQ_PINCTRL_GRP(can0_1), 452 451 DEFINE_ZYNQ_PINCTRL_GRP(can0_2), ··· 712 709 static const char * const smc0_nor_groups[] = {"smc0_nor_grp"}; 713 710 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; 714 711 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; 715 - static const char * const smc0_nand_groups[] = {"smc0_nand_grp"}; 712 + static const char * const smc0_nand_groups[] = {"smc0_nand_grp", 713 + "smc0_nand8_grp"}; 716 714 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", 717 715 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", 718 716 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",