Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

MIPS: fix typos in comments

Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Julia Lawall and committed by
Thomas Bogendoerfer
94bd83e4 7671f967

+20 -20
+1 -1
arch/mips/alchemy/common/dbdma.c
··· 574 574 dp++; 575 575 } 576 576 577 - /* Make last descrptor point to the first. */ 577 + /* Make last descriptor point to the first. */ 578 578 dp--; 579 579 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); 580 580 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
+1 -1
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
··· 318 318 } 319 319 320 320 /* 321 - * Determine if this is an entry that can satisify the 321 + * Determine if this is an entry that can satisfy the 322 322 * request Check to make sure entry is large enough to 323 323 * satisfy request. 324 324 */
+1 -1
arch/mips/cavium-octeon/executive/cvmx-pko.c
··· 377 377 /* 378 378 * Check to make sure all static priority 379 379 * queues are contiguous. Also catches some 380 - * cases of static priorites not starting at 380 + * cases of static priorities not starting at 381 381 * queue 0. 382 382 */ 383 383 if (static_priority_end != -1
+1 -1
arch/mips/cavium-octeon/octeon-irq.c
··· 1405 1405 * completed. 1406 1406 * 1407 1407 * There are 9 registers and 3 IPX levels with strides 0x1000 1408 - * and 0x200 respectivly. Use loops to clear them. 1408 + * and 0x200 respectively. Use loops to clear them. 1409 1409 */ 1410 1410 for (regx = 0; regx <= 0x8000; regx += 0x1000) { 1411 1411 for (ipx = 0; ipx <= 0x400; ipx += 0x200)
+1 -1
arch/mips/cavium-octeon/octeon-usb.c
··· 419 419 /* Step 5c: Enable SuperSpeed. */ 420 420 uctl_ctl.s.ref_ssp_en = 1; 421 421 422 - /* Step 5d: Cofngiure PHYs. SKIP */ 422 + /* Step 5d: Configure PHYs. SKIP */ 423 423 424 424 /* Step 6a & 6b: Power up PHYs. */ 425 425 uctl_ctl.s.hs_power_en = 1;
+2 -2
arch/mips/dec/ioasic-irq.c
··· 68 68 * I/O ASIC implements two kinds of DMA interrupts, informational and 69 69 * error interrupts. 70 70 * 71 - * The formers do not stop DMA and should be cleared as soon as possible 71 + * The former do not stop DMA and should be cleared as soon as possible 72 72 * so that if they retrigger before the handler has completed, usually as 73 73 * a side effect of actions taken by the handler, then they are reissued. 74 74 * These use the `handle_edge_irq' handler that clears the request right 75 75 * away. 76 76 * 77 - * The latters stop DMA and do not resume it until the interrupt has been 77 + * The latter stop DMA and do not resume it until the interrupt has been 78 78 * cleared. This cannot be done until after a corrective action has been 79 79 * taken and this also means they will not retrigger. Therefore they use 80 80 * the `handle_fasteoi_irq' handler that only clears the request on the
+1 -1
arch/mips/dec/setup.c
··· 71 71 EXPORT_SYMBOL(ioasic_base); 72 72 73 73 /* 74 - * IRQ routing and priority tables. Priorites are set as follows: 74 + * IRQ routing and priority tables. Priorities are set as follows: 75 75 * 76 76 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 77 77 *
+1 -1
arch/mips/fw/arc/memory.c
··· 32 32 static unsigned int nr_prom_mem __initdata; 33 33 34 34 /* 35 - * For ARC firmware memory functions the unit of meassuring memory is always 35 + * For ARC firmware memory functions the unit of measuring memory is always 36 36 * a 4k page of memory 37 37 */ 38 38 #define ARC_PAGE_SHIFT 12
+1 -1
arch/mips/jazz/irq.c
··· 141 141 /* 142 142 * Set clock to 100Hz. 143 143 * 144 - * The R4030 timer receives an input clock of 1kHz which is divieded by 144 + * The R4030 timer receives an input clock of 1kHz which is divided by 145 145 * a programmable 4-bit divider. This makes it fairly inflexible. 146 146 */ 147 147 r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
+1 -1
arch/mips/kernel/cmpxchg.c
··· 22 22 23 23 /* 24 24 * Calculate a shift & mask that correspond to the value we wish to 25 - * exchange within the naturally aligned 4 byte integerthat includes 25 + * exchange within the naturally aligned 4 byte integer that includes 26 26 * it. 27 27 */ 28 28 shift = (unsigned long)ptr & 0x3;
+1 -1
arch/mips/kernel/cpu-probe.c
··· 156 156 /* 157 157 * Erratum "RPS May Cause Incorrect Instruction Execution" 158 158 * This code only handles VPE0, any SMP/RTOS code 159 - * making use of VPE1 will be responsable for that VPE. 159 + * making use of VPE1 will be responsible for that VPE. 160 160 */ 161 161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 162 162 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
+1 -1
arch/mips/kernel/idle.c
··· 228 228 break; 229 229 230 230 /* 231 - * Another rev is incremeting c0_count at a reduced clock 231 + * Another rev is incrementing c0_count at a reduced clock 232 232 * rate while in WAIT mode. So we basically have the choice 233 233 * between using the cp0 timer as clocksource or avoiding 234 234 * the WAIT instruction. Until more details are known,
+1 -1
arch/mips/kernel/perf_event_mipsxx.c
··· 329 329 for (i = mipspmu.num_counters - 1; i >= 0; i--) { 330 330 /* 331 331 * Note that some MIPS perf events can be counted by both 332 - * even and odd counters, wheresas many other are only by 332 + * even and odd counters, whereas many other are only by 333 333 * even _or_ odd counters. This introduces an issue that 334 334 * when the former kind of event takes the counter the 335 335 * latter kind of event wants to use, then the "counter
+1 -1
arch/mips/kvm/tlb.c
··· 153 153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping. 154 154 * @vcpu: KVM VCPU pointer. 155 155 * @gpa: Guest virtual address in a TLB mapped guest segment. 156 - * @gpa: Ponter to output guest physical address it maps to. 156 + * @gpa: Pointer to output guest physical address it maps to. 157 157 * 158 158 * Converts a guest virtual address in a guest TLB mapped segment to a guest 159 159 * physical address, by probing the guest TLB.
+1 -1
arch/mips/net/bpf_jit_comp32.c
··· 722 722 0, JIT_RESERVED_STACK); 723 723 /* 724 724 * Argument 1: dst+off if xchg, otherwise src, passed in register a0 725 - * Argument 2: src if xchg, othersize dst+off, passed in register a1 725 + * Argument 2: src if xchg, otherwise dst+off, passed in register a1 726 726 */ 727 727 emit(ctx, move, MIPS_R_T9, dst); 728 728 if (code == BPF_XCHG) {
+1 -1
arch/mips/pci/pcie-octeon.c
··· 1345 1345 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ 1346 1346 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ 1347 1347 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ 1348 - /* PCIe Adddress Bits <63:34>. */ 1348 + /* PCIe Address Bits <63:34>. */ 1349 1349 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 1350 1350 mem_access_subid.cn68xx.ba = 0; 1351 1351 else
+1 -1
arch/mips/pic32/pic32mzda/config.c
··· 111 111 pic32_reset_status = readl(pic32_conf_base + PIC32_RCON); 112 112 writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON)); 113 113 114 - /* Device Inforation */ 114 + /* Device Information */ 115 115 pr_info("Device Id: 0x%08x, Device Ver: 0x%04x\n", 116 116 pic32_get_device_id(), 117 117 pic32_get_device_version());
+1 -1
arch/mips/tools/loongson3-llsc-check.c
··· 217 217 ) 218 218 219 219 /* 220 - * Skip the first instructionm allowing check_ll to look backwards 220 + * Skip the first instruction, allowing check_ll to look backwards 221 221 * unconditionally. 222 222 */ 223 223 advance();
+1 -1
arch/mips/txx9/generic/pci.c
··· 225 225 static int __init 226 226 txx9_arch_pci_init(void) 227 227 { 228 - PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ 228 + PCIBIOS_MIN_IO = 0x8000; /* reserve legacy I/O space */ 229 229 return 0; 230 230 } 231 231 arch_initcall(txx9_arch_pci_init);