ARM: tegra: Use proper tuple notation · tjh.dev/kernel@9482a17

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

ARM: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Thierry Reding 5 years ago 9482a170 cc761754

+89 -82

5 changed files

expand all

arch

arm

boot

dts

tegra114.dtsi

tegra124.dtsi

tegra20.dtsi

tegra30-apalis-v1.1-eval.dts

tegra30.dtsi

+8 -6

arch/arm/boot/dts/tegra114.dtsi

··· 255 255 256 256 apbmisc@70000800 { 257 257 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 258 - reg = <0x70000800 0x64 /* Chip revision */ 259 - 0x70000008 0x04>; /* Strapping options */ 258 + reg = <0x70000800 0x64>, /* Chip revision */ 259 + <0x70000008 0x04>; /* Strapping options */ 260 260 }; 261 261 262 262 pinmux: pinmux@70000868 { 263 263 compatible = "nvidia,tegra114-pinmux"; 264 - reg = <0x70000868 0x148 /* Pad control registers */ 265 - 0x70003000 0x40c>; /* Mux registers */ 264 + reg = <0x70000868 0x148>, /* Pad control registers */ 265 + <0x70003000 0x40c>; /* Mux registers */ 266 266 }; 267 267 268 268 /* ··· 704 704 705 705 phy1: usb-phy@7d000000 { 706 706 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 707 - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 707 + reg = <0x7d000000 0x4000>, 708 + <0x7d000000 0x4000>; 708 709 phy_type = "utmi"; 709 710 clocks = <&tegra_car TEGRA114_CLK_USBD>, 710 711 <&tegra_car TEGRA114_CLK_PLL_U>, ··· 742 741 743 742 phy3: usb-phy@7d008000 { 744 743 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 745 - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 744 + reg = <0x7d008000 0x4000>, 745 + <0x7d000000 0x4000>; 746 746 phy_type = "utmi"; 747 747 clocks = <&tegra_car TEGRA114_CLK_USB3>, 748 748 <&tegra_car TEGRA114_CLK_PLL_U>,

+10 -10

arch/arm/boot/dts/tegra124.dtsi

··· 22 22 pcie@1003000 { 23 23 compatible = "nvidia,tegra124-pcie"; 24 24 device_type = "pci"; 25 - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 26 - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 27 - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 25 + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 26 + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 27 + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 28 28 reg-names = "pads", "afi", "cs"; 29 29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 30 30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ ··· 38 38 #address-cells = <3>; 39 39 #size-cells = <2>; 40 40 41 - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 42 - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 43 - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 44 - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 45 - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 42 + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 43 + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 44 + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 45 + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 46 46 47 47 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 48 48 <&tegra_car TEGRA124_CLK_AFI>, ··· 885 885 886 886 soctherm: thermal-sensor@700e2000 { 887 887 compatible = "nvidia,tegra124-soctherm"; 888 - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 889 - 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 888 + reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 889 + <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 890 890 reg-names = "soctherm-reg", "car-reg"; 891 891 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 892 892 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,

+33 -31

arch/arm/boot/dts/tegra20.dtsi

··· 174 174 175 175 intc: interrupt-controller@50041000 { 176 176 compatible = "arm,cortex-a9-gic"; 177 - reg = <0x50041000 0x1000 178 - 0x50040100 0x0100>; 177 + reg = <0x50041000 0x1000>, 178 + <0x50040100 0x0100>; 179 179 interrupt-controller; 180 180 #interrupt-cells = <3>; 181 181 interrupt-parent = <&intc>; ··· 274 274 275 275 vde@6001a000 { 276 276 compatible = "nvidia,tegra20-vde"; 277 - reg = <0x6001a000 0x1000 /* Syntax Engine */ 278 - 0x6001b000 0x1000 /* Video Bitstream Engine */ 279 - 0x6001c000 0x100 /* Macroblock Engine */ 280 - 0x6001c200 0x100 /* Post-processing Engine */ 281 - 0x6001c400 0x100 /* Motion Compensation Engine */ 282 - 0x6001c600 0x100 /* Transform Engine */ 283 - 0x6001c800 0x100 /* Pixel prediction block */ 284 - 0x6001ca00 0x100 /* Video DMA */ 285 - 0x6001d800 0x300>; /* Video frame controls */ 277 + reg = <0x6001a000 0x1000>, /* Syntax Engine */ 278 + <0x6001b000 0x1000>, /* Video Bitstream Engine */ 279 + <0x6001c000 0x100>, /* Macroblock Engine */ 280 + <0x6001c200 0x100>, /* Post-processing Engine */ 281 + <0x6001c400 0x100>, /* Motion Compensation Engine */ 282 + <0x6001c600 0x100>, /* Transform Engine */ 283 + <0x6001c800 0x100>, /* Pixel prediction block */ 284 + <0x6001ca00 0x100>, /* Video DMA */ 285 + <0x6001d800 0x300>; /* Video frame controls */ 286 286 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 287 287 "tfe", "ppb", "vdma", "frameid"; 288 288 iram = <&vde_pool>; /* IRAM region */ ··· 297 297 298 298 apbmisc@70000800 { 299 299 compatible = "nvidia,tegra20-apbmisc"; 300 - reg = <0x70000800 0x64 /* Chip revision */ 301 - 0x70000008 0x04>; /* Strapping options */ 300 + reg = <0x70000800 0x64>, /* Chip revision */ 301 + <0x70000008 0x04>; /* Strapping options */ 302 302 }; 303 303 304 304 pinmux: pinmux@70000014 { 305 305 compatible = "nvidia,tegra20-pinmux"; 306 - reg = <0x70000014 0x10 /* Tri-state registers */ 307 - 0x70000080 0x20 /* Mux registers */ 308 - 0x700000a0 0x14 /* Pull-up/down registers */ 309 - 0x70000868 0xa8>; /* Pad control registers */ 306 + reg = <0x70000014 0x10>, /* Tri-state registers */ 307 + <0x70000080 0x20>, /* Mux registers */ 308 + <0x700000a0 0x14>, /* Pull-up/down registers */ 309 + <0x70000868 0xa8>; /* Pad control registers */ 310 310 }; 311 311 312 312 das@70000c00 { ··· 621 621 622 622 mc: memory-controller@7000f000 { 623 623 compatible = "nvidia,tegra20-mc-gart"; 624 - reg = <0x7000f000 0x400 /* controller registers */ 625 - 0x58000000 0x02000000>; /* GART aperture */ 624 + reg = <0x7000f000 0x00000400>, /* controller registers */ 625 + <0x58000000 0x02000000>; /* GART aperture */ 626 626 clocks = <&tegra_car TEGRA20_CLK_MC>; 627 627 clock-names = "mc"; 628 628 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; ··· 651 651 pcie@80003000 { 652 652 compatible = "nvidia,tegra20-pcie"; 653 653 device_type = "pci"; 654 - reg = <0x80003000 0x00000800 /* PADS registers */ 655 - 0x80003800 0x00000200 /* AFI registers */ 656 - 0x90000000 0x10000000>; /* configuration space */ 654 + reg = <0x80003000 0x00000800>, /* PADS registers */ 655 + <0x80003800 0x00000200>, /* AFI registers */ 656 + <0x90000000 0x10000000>; /* configuration space */ 657 657 reg-names = "pads", "afi", "cs"; 658 - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 659 - GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 658 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 659 + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 660 660 interrupt-names = "intr", "msi"; 661 661 662 662 #interrupt-cells = <1>; ··· 667 667 #address-cells = <3>; 668 668 #size-cells = <2>; 669 669 670 - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 671 - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 672 - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 673 - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ 674 - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 670 + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ 671 + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ 672 + <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ 673 + <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ 674 + <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 675 675 676 676 clocks = <&tegra_car TEGRA20_CLK_PEX>, 677 677 <&tegra_car TEGRA20_CLK_AFI>, ··· 728 728 729 729 phy1: usb-phy@c5000000 { 730 730 compatible = "nvidia,tegra20-usb-phy"; 731 - reg = <0xc5000000 0x4000 0xc5000000 0x4000>; 731 + reg = <0xc5000000 0x4000>, 732 + <0xc5000000 0x4000>; 732 733 phy_type = "utmi"; 733 734 clocks = <&tegra_car TEGRA20_CLK_USBD>, 734 735 <&tegra_car TEGRA20_CLK_PLL_U>, ··· 791 790 792 791 phy3: usb-phy@c5008000 { 793 792 compatible = "nvidia,tegra20-usb-phy"; 794 - reg = <0xc5008000 0x4000 0xc5000000 0x4000>; 793 + reg = <0xc5008000 0x4000>, 794 + <0xc5000000 0x4000>; 795 795 phy_type = "utmi"; 796 796 clocks = <&tegra_car TEGRA20_CLK_USB3>, 797 797 <&tegra_car TEGRA20_CLK_PLL_U>,

+2 -2

arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts

··· 248 248 regulator-max-microvolt = <3300000>; 249 249 regulator-type = "voltage"; 250 250 gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; 251 - states = <1800000 0x0 252 - 3300000 0x1>; 251 + states = <1800000 0x0>, 252 + <3300000 0x1>; 253 253 startup-delay-us = <100000>; 254 254 vin-supply = <&vddio_sdmmc_1v8_reg>; 255 255 };

+36 -33

arch/arm/boot/dts/tegra30.dtsi

··· 20 20 pcie@3000 { 21 21 compatible = "nvidia,tegra30-pcie"; 22 22 device_type = "pci"; 23 - reg = <0x00003000 0x00000800 /* PADS registers */ 24 - 0x00003800 0x00000200 /* AFI registers */ 25 - 0x10000000 0x10000000>; /* configuration space */ 23 + reg = <0x00003000 0x00000800>, /* PADS registers */ 24 + <0x00003800 0x00000200>, /* AFI registers */ 25 + <0x10000000 0x10000000>; /* configuration space */ 26 26 reg-names = "pads", "afi", "cs"; 27 - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 28 - GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 28 + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 29 29 interrupt-names = "intr", "msi"; 30 30 31 31 #interrupt-cells = <1>; ··· 36 36 #address-cells = <3>; 37 37 #size-cells = <2>; 38 38 39 - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 40 - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 41 - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 42 - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ 43 - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 44 - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 39 + ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ 40 + <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ 41 + <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ 42 + <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ 43 + <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ 44 + <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 45 45 46 46 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 47 47 <&tegra_car TEGRA30_CLK_AFI>, ··· 185 185 gr3d@54180000 { 186 186 compatible = "nvidia,tegra30-gr3d"; 187 187 reg = <0x54180000 0x00040000>; 188 - clocks = <&tegra_car TEGRA30_CLK_GR3D 189 - &tegra_car TEGRA30_CLK_GR3D2>; 188 + clocks = <&tegra_car TEGRA30_CLK_GR3D>, 189 + <&tegra_car TEGRA30_CLK_GR3D2>; 190 190 clock-names = "3d", "3d2"; 191 191 resets = <&tegra_car 24>, 192 192 <&tegra_car 98>; ··· 275 275 276 276 intc: interrupt-controller@50041000 { 277 277 compatible = "arm,cortex-a9-gic"; 278 - reg = <0x50041000 0x1000 279 - 0x50040100 0x0100>; 278 + reg = <0x50041000 0x1000>, 279 + <0x50040100 0x0100>; 280 280 interrupt-controller; 281 281 #interrupt-cells = <3>; 282 282 interrupt-parent = <&intc>; ··· 406 406 407 407 vde@6001a000 { 408 408 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 409 - reg = <0x6001a000 0x1000 /* Syntax Engine */ 410 - 0x6001b000 0x1000 /* Video Bitstream Engine */ 411 - 0x6001c000 0x100 /* Macroblock Engine */ 412 - 0x6001c200 0x100 /* Post-processing Engine */ 413 - 0x6001c400 0x100 /* Motion Compensation Engine */ 414 - 0x6001c600 0x100 /* Transform Engine */ 415 - 0x6001c800 0x100 /* Pixel prediction block */ 416 - 0x6001ca00 0x100 /* Video DMA */ 417 - 0x6001d800 0x400>; /* Video frame controls */ 409 + reg = <0x6001a000 0x1000>, /* Syntax Engine */ 410 + <0x6001b000 0x1000>, /* Video Bitstream Engine */ 411 + <0x6001c000 0x100>, /* Macroblock Engine */ 412 + <0x6001c200 0x100>, /* Post-processing Engine */ 413 + <0x6001c400 0x100>, /* Motion Compensation Engine */ 414 + <0x6001c600 0x100>, /* Transform Engine */ 415 + <0x6001c800 0x100>, /* Pixel prediction block */ 416 + <0x6001ca00 0x100>, /* Video DMA */ 417 + <0x6001d800 0x400>; /* Video frame controls */ 418 418 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 419 419 "tfe", "ppb", "vdma", "frameid"; 420 420 iram = <&vde_pool>; /* IRAM region */ ··· 430 430 431 431 apbmisc@70000800 { 432 432 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 433 - reg = <0x70000800 0x64 /* Chip revision */ 434 - 0x70000008 0x04>; /* Strapping options */ 433 + reg = <0x70000800 0x64>, /* Chip revision */ 434 + <0x70000008 0x04>; /* Strapping options */ 435 435 }; 436 436 437 437 pinmux: pinmux@70000868 { 438 438 compatible = "nvidia,tegra30-pinmux"; 439 - reg = <0x70000868 0xd4 /* Pad control registers */ 440 - 0x70003000 0x3e4>; /* Mux registers */ 439 + reg = <0x70000868 0x0d4>, /* Pad control registers */ 440 + <0x70003000 0x3e4>; /* Mux registers */ 441 441 }; 442 442 443 443 /* ··· 772 772 773 773 ahub@70080000 { 774 774 compatible = "nvidia,tegra30-ahub"; 775 - reg = <0x70080000 0x200 776 - 0x70080200 0x100>; 775 + reg = <0x70080000 0x200>, 776 + <0x70080200 0x100>; 777 777 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 778 778 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 779 779 <&tegra_car TEGRA30_CLK_APBIF>; ··· 908 908 909 909 phy1: usb-phy@7d000000 { 910 910 compatible = "nvidia,tegra30-usb-phy"; 911 - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 911 + reg = <0x7d000000 0x4000>, 912 + <0x7d000000 0x4000>; 912 913 phy_type = "utmi"; 913 914 clocks = <&tegra_car TEGRA30_CLK_USBD>, 914 915 <&tegra_car TEGRA30_CLK_PLL_U>, ··· 947 946 948 947 phy2: usb-phy@7d004000 { 949 948 compatible = "nvidia,tegra30-usb-phy"; 950 - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; 949 + reg = <0x7d004000 0x4000>, 950 + <0x7d000000 0x4000>; 951 951 phy_type = "utmi"; 952 952 clocks = <&tegra_car TEGRA30_CLK_USB2>, 953 953 <&tegra_car TEGRA30_CLK_PLL_U>, ··· 985 983 986 984 phy3: usb-phy@7d008000 { 987 985 compatible = "nvidia,tegra30-usb-phy"; 988 - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 986 + reg = <0x7d008000 0x4000>, 987 + <0x7d000000 0x4000>; 989 988 phy_type = "utmi"; 990 989 clocks = <&tegra_car TEGRA30_CLK_USB3>, 991 990 <&tegra_car TEGRA30_CLK_PLL_U>,