Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

usb: musb: da8xx: Remove mach code

Use the new phy-da8xx-usb driver to take the place of the mach code that
pokes CFGCHIP2 in the da8xx musb glue driver. This unbreaks the driver.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

David Lechner and committed by
Greg Kroah-Hartman
947c49af d458fe9a

+51 -86
+1 -1
drivers/usb/musb/Kconfig
··· 82 82 tristate "DA8xx/OMAP-L1x" 83 83 depends on ARCH_DAVINCI_DA8XX 84 84 depends on NOP_USB_XCEIV 85 - depends on BROKEN 85 + select PHY_DA8XX_USB 86 86 87 87 config USB_MUSB_TUSB6010 88 88 tristate "TUSB6010"
+50 -85
drivers/usb/musb/da8xx.c
··· 30 30 #include <linux/clk.h> 31 31 #include <linux/err.h> 32 32 #include <linux/io.h> 33 + #include <linux/phy/phy.h> 33 34 #include <linux/platform_device.h> 34 35 #include <linux/dma-mapping.h> 35 36 #include <linux/usb/usb_phy_generic.h> 36 - 37 - #include <mach/da8xx.h> 38 - #include <linux/platform_data/usb-davinci.h> 39 37 40 38 #include "musb_core.h" 41 39 ··· 78 80 79 81 #define DA8XX_MENTOR_CORE_OFFSET 0x400 80 82 81 - #define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG) 82 - 83 83 struct da8xx_glue { 84 84 struct device *dev; 85 85 struct platform_device *musb; 86 - struct platform_device *phy; 86 + struct platform_device *usb_phy; 87 87 struct clk *clk; 88 + struct phy *phy; 88 89 }; 89 - 90 - /* 91 - * REVISIT (PM): we should be able to keep the PHY in low power mode most 92 - * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0 93 - * and, when in host mode, autosuspending idle root ports... PHY_PLLON 94 - * (overriding SUSPENDM?) then likely needs to stay off. 95 - */ 96 - 97 - static inline void phy_on(void) 98 - { 99 - u32 cfgchip2 = __raw_readl(CFGCHIP2); 100 - 101 - /* 102 - * Start the on-chip PHY and its PLL. 103 - */ 104 - cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN); 105 - cfgchip2 |= CFGCHIP2_PHY_PLLON; 106 - __raw_writel(cfgchip2, CFGCHIP2); 107 - 108 - pr_info("Waiting for USB PHY clock good...\n"); 109 - while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD)) 110 - cpu_relax(); 111 - } 112 - 113 - static inline void phy_off(void) 114 - { 115 - u32 cfgchip2 = __raw_readl(CFGCHIP2); 116 - 117 - /* 118 - * Ensure that USB 1.1 reference clock is not being sourced from 119 - * USB 2.0 PHY. Otherwise do not power down the PHY. 120 - */ 121 - if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) && 122 - (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) { 123 - pr_warning("USB 1.1 clocked from USB 2.0 PHY -- " 124 - "can't power it down\n"); 125 - return; 126 - } 127 - 128 - /* 129 - * Power down the on-chip PHY. 130 - */ 131 - cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; 132 - __raw_writel(cfgchip2, CFGCHIP2); 133 - } 134 90 135 91 /* 136 92 * Because we don't set CTRL.UINT, it's "important" to: ··· 337 385 338 386 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode) 339 387 { 340 - u32 cfgchip2 = __raw_readl(CFGCHIP2); 388 + struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 389 + enum phy_mode phy_mode; 341 390 342 - cfgchip2 &= ~CFGCHIP2_OTGMODE; 343 391 switch (musb_mode) { 344 392 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 345 - cfgchip2 |= CFGCHIP2_FORCE_HOST; 393 + phy_mode = PHY_MODE_USB_HOST; 346 394 break; 347 395 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 348 - cfgchip2 |= CFGCHIP2_FORCE_DEVICE; 396 + phy_mode = PHY_MODE_USB_DEVICE; 349 397 break; 350 398 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 351 - cfgchip2 |= CFGCHIP2_NO_OVERRIDE; 399 + phy_mode = PHY_MODE_USB_OTG; 352 400 break; 353 401 default: 354 - dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode); 402 + return -EINVAL; 355 403 } 356 404 357 - __raw_writel(cfgchip2, CFGCHIP2); 358 - return 0; 405 + return phy_set_mode(glue->phy, phy_mode); 359 406 } 360 407 361 408 static int da8xx_musb_init(struct musb *musb) 362 409 { 410 + struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 363 411 void __iomem *reg_base = musb->ctrl_base; 364 412 u32 rev; 365 413 int ret = -ENODEV; ··· 377 425 goto fail; 378 426 } 379 427 428 + ret = clk_prepare_enable(glue->clk); 429 + if (ret) { 430 + dev_err(glue->dev, "failed to enable clock\n"); 431 + goto fail; 432 + } 433 + 380 434 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); 381 435 382 436 /* Reset the controller */ 383 437 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); 384 438 385 439 /* Start the on-chip PHY and its PLL. */ 386 - phy_on(); 440 + ret = phy_init(glue->phy); 441 + if (ret) { 442 + dev_err(glue->dev, "Failed to init phy.\n"); 443 + goto err_phy_init; 444 + } 445 + 446 + ret = phy_power_on(glue->phy); 447 + if (ret) { 448 + dev_err(glue->dev, "Failed to power on phy.\n"); 449 + goto err_phy_power_on; 450 + } 387 451 388 452 msleep(5); 389 453 390 454 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ 391 - pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n", 392 - rev, __raw_readl(CFGCHIP2), 455 + pr_debug("DA8xx OTG revision %08x, control %02x\n", rev, 393 456 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); 394 457 395 458 musb->isr = da8xx_musb_interrupt; 396 459 return 0; 460 + 461 + err_phy_power_on: 462 + phy_exit(glue->phy); 463 + err_phy_init: 464 + clk_disable_unprepare(glue->clk); 397 465 fail: 398 466 return ret; 399 467 } 400 468 401 469 static int da8xx_musb_exit(struct musb *musb) 402 470 { 471 + struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); 472 + 403 473 del_timer_sync(&otg_workaround); 404 474 405 - phy_off(); 475 + phy_power_off(glue->phy); 476 + phy_exit(glue->phy); 477 + clk_disable_unprepare(glue->clk); 406 478 407 479 usb_put_phy(musb->xceiv); 408 480 ··· 478 502 return PTR_ERR(clk); 479 503 } 480 504 481 - ret = clk_enable(clk); 482 - if (ret) { 483 - dev_err(&pdev->dev, "failed to enable clock\n"); 484 - goto err4; 505 + glue->phy = devm_phy_get(&pdev->dev, "usb-phy"); 506 + if (IS_ERR(glue->phy)) { 507 + dev_err(&pdev->dev, "failed to get phy\n"); 508 + return PTR_ERR(glue->phy); 485 509 } 486 510 487 511 glue->dev = &pdev->dev; ··· 489 513 490 514 pdata->platform_ops = &da8xx_ops; 491 515 492 - glue->phy = usb_phy_generic_register(); 493 - if (IS_ERR(glue->phy)) { 494 - ret = PTR_ERR(glue->phy); 495 - goto err5; 516 + glue->usb_phy = usb_phy_generic_register(); 517 + if (IS_ERR(glue->usb_phy)) { 518 + dev_err(&pdev->dev, "failed to register usb_phy\n"); 519 + return PTR_ERR(glue->usb_phy); 496 520 } 497 521 platform_set_drvdata(pdev, glue); 498 522 ··· 518 542 519 543 glue->musb = musb = platform_device_register_full(&pinfo); 520 544 if (IS_ERR(musb)) { 521 - ret = PTR_ERR(musb); 522 545 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 523 - goto err6; 546 + usb_phy_generic_unregister(glue->usb_phy); 547 + return PTR_ERR(musb); 524 548 } 525 549 526 550 return 0; 527 - 528 - err6: 529 - usb_phy_generic_unregister(glue->phy); 530 - 531 - err5: 532 - clk_disable(clk); 533 - 534 - err4: 535 - 536 - return ret; 537 551 } 538 552 539 553 static int da8xx_remove(struct platform_device *pdev) ··· 531 565 struct da8xx_glue *glue = platform_get_drvdata(pdev); 532 566 533 567 platform_device_unregister(glue->musb); 534 - usb_phy_generic_unregister(glue->phy); 535 - clk_disable(glue->clk); 568 + usb_phy_generic_unregister(glue->usb_phy); 536 569 537 570 return 0; 538 571 }