tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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intel drivers: repair missing flush operations

after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();

which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();

explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device. If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

authored by

Jesse Brandeburg and committed by
Jeff Kirsher 945a5151 d3e61457

+59
+6
drivers/net/e1000/e1000_ethtool.c
··· 838 838 839 839 /* Disable all the interrupts */ 840 840 ew32(IMC, 0xFFFFFFFF); 841 + E1000_WRITE_FLUSH(); 841 842 msleep(10); 842 843 843 844 /* Test each interrupt */ ··· 857 856 adapter->test_icr = 0; 858 857 ew32(IMC, mask); 859 858 ew32(ICS, mask); 859 + E1000_WRITE_FLUSH(); 860 860 msleep(10); 861 861 862 862 if (adapter->test_icr & mask) { ··· 875 873 adapter->test_icr = 0; 876 874 ew32(IMS, mask); 877 875 ew32(ICS, mask); 876 + E1000_WRITE_FLUSH(); 878 877 msleep(10); 879 878 880 879 if (!(adapter->test_icr & mask)) { ··· 893 890 adapter->test_icr = 0; 894 891 ew32(IMC, ~mask & 0x00007FFF); 895 892 ew32(ICS, ~mask & 0x00007FFF); 893 + E1000_WRITE_FLUSH(); 896 894 msleep(10); 897 895 898 896 if (adapter->test_icr) { ··· 905 901 906 902 /* Disable all the interrupts */ 907 903 ew32(IMC, 0xFFFFFFFF); 904 + E1000_WRITE_FLUSH(); 908 905 msleep(10); 909 906 910 907 /* Unhook test interrupt handler */ ··· 1399 1394 if (unlikely(++k == txdr->count)) k = 0; 1400 1395 } 1401 1396 ew32(TDT, k); 1397 + E1000_WRITE_FLUSH(); 1402 1398 msleep(200); 1403 1399 time = jiffies; /* set the start time for the receive */ 1404 1400 good_cnt = 0;
+3
drivers/net/e1000/e1000_hw.c
··· 446 446 /* Must reset the PHY before resetting the MAC */ 447 447 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 448 448 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 449 + E1000_WRITE_FLUSH(); 449 450 msleep(5); 450 451 } 451 452 ··· 3753 3752 /* Clear SK and CS */ 3754 3753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3755 3754 ew32(EECD, eecd); 3755 + E1000_WRITE_FLUSH(); 3756 3756 udelay(1); 3757 3757 } 3758 3758 ··· 3826 3824 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3827 3825 3828 3826 ew32(EECD, eecd); 3827 + E1000_WRITE_FLUSH(); 3829 3828 3830 3829 udelay(hw->eeprom.delay_usec); 3831 3830 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
+2
drivers/net/e1000e/es2lan.c
··· 1313 1313 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1314 1314 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1315 1315 ew32(KMRNCTRLSTA, kmrnctrlsta); 1316 + e1e_flush(); 1316 1317 1317 1318 udelay(2); 1318 1319 ··· 1348 1347 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1349 1348 E1000_KMRNCTRLSTA_OFFSET) | data; 1350 1349 ew32(KMRNCTRLSTA, kmrnctrlsta); 1350 + e1e_flush(); 1351 1351 1352 1352 udelay(2); 1353 1353
+9
drivers/net/e1000e/ethtool.c
··· 964 964 965 965 /* Disable all the interrupts */ 966 966 ew32(IMC, 0xFFFFFFFF); 967 + e1e_flush(); 967 968 usleep_range(10000, 20000); 968 969 969 970 /* Test each interrupt */ ··· 997 996 adapter->test_icr = 0; 998 997 ew32(IMC, mask); 999 998 ew32(ICS, mask); 999 + e1e_flush(); 1000 1000 usleep_range(10000, 20000); 1001 1001 1002 1002 if (adapter->test_icr & mask) { ··· 1016 1014 adapter->test_icr = 0; 1017 1015 ew32(IMS, mask); 1018 1016 ew32(ICS, mask); 1017 + e1e_flush(); 1019 1018 usleep_range(10000, 20000); 1020 1019 1021 1020 if (!(adapter->test_icr & mask)) { ··· 1035 1032 adapter->test_icr = 0; 1036 1033 ew32(IMC, ~mask & 0x00007FFF); 1037 1034 ew32(ICS, ~mask & 0x00007FFF); 1035 + e1e_flush(); 1038 1036 usleep_range(10000, 20000); 1039 1037 1040 1038 if (adapter->test_icr) { ··· 1047 1043 1048 1044 /* Disable all the interrupts */ 1049 1045 ew32(IMC, 0xFFFFFFFF); 1046 + e1e_flush(); 1050 1047 usleep_range(10000, 20000); 1051 1048 1052 1049 /* Unhook test interrupt handler */ ··· 1281 1276 E1000_CTRL_FD); /* Force Duplex to FULL */ 1282 1277 1283 1278 ew32(CTRL, ctrl_reg); 1279 + e1e_flush(); 1284 1280 udelay(500); 1285 1281 1286 1282 return 0; ··· 1424 1418 */ 1425 1419 #define E1000_SERDES_LB_ON 0x410 1426 1420 ew32(SCTL, E1000_SERDES_LB_ON); 1421 + e1e_flush(); 1427 1422 usleep_range(10000, 20000); 1428 1423 1429 1424 return 0; ··· 1520 1513 hw->phy.media_type == e1000_media_type_internal_serdes) { 1521 1514 #define E1000_SERDES_LB_OFF 0x400 1522 1515 ew32(SCTL, E1000_SERDES_LB_OFF); 1516 + e1e_flush(); 1523 1517 usleep_range(10000, 20000); 1524 1518 break; 1525 1519 } ··· 1600 1592 k = 0; 1601 1593 } 1602 1594 ew32(TDT, k); 1595 + e1e_flush(); 1603 1596 msleep(200); 1604 1597 time = jiffies; /* set the start time for the receive */ 1605 1598 good_cnt = 0;
+4
drivers/net/e1000e/ich8lan.c
··· 283 283 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 284 284 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 285 285 ew32(CTRL, ctrl); 286 + e1e_flush(); 286 287 udelay(10); 287 288 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 288 289 ew32(CTRL, ctrl); ··· 1231 1230 ew32(CTRL, reg); 1232 1231 1233 1232 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1233 + e1e_flush(); 1234 1234 udelay(20); 1235 1235 ew32(CTRL, ctrl_reg); 1236 1236 ew32(CTRL_EXT, ctrl_ext); 1237 + e1e_flush(); 1237 1238 udelay(20); 1238 1239 1239 1240 out: ··· 3093 3090 ret_val = e1000_acquire_swflag_ich8lan(hw); 3094 3091 e_dbg("Issuing a global reset to ich8lan\n"); 3095 3092 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 3093 + /* cannot issue a flush here because it hangs the hardware */ 3096 3094 msleep(20); 3097 3095 3098 3096 if (!ret_val)
+1
drivers/net/e1000e/lib.c
··· 1986 1986 /* Clear SK and CS */ 1987 1987 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 1988 1988 ew32(EECD, eecd); 1989 + e1e_flush(); 1989 1990 udelay(1); 1990 1991 1991 1992 /*
+2
drivers/net/e1000e/phy.c
··· 537 537 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 538 538 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 539 539 ew32(KMRNCTRLSTA, kmrnctrlsta); 540 + e1e_flush(); 540 541 541 542 udelay(2); 542 543 ··· 610 609 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 611 610 E1000_KMRNCTRLSTA_OFFSET) | data; 612 611 ew32(KMRNCTRLSTA, kmrnctrlsta); 612 + e1e_flush(); 613 613 614 614 udelay(2); 615 615
+1
drivers/net/igb/e1000_nvm.c
··· 285 285 /* Clear SK and CS */ 286 286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 287 287 wr32(E1000_EECD, eecd); 288 + wrfl(); 288 289 udelay(1); 289 290 timeout = NVM_MAX_RETRY_SPI; 290 291
+5
drivers/net/igb/igb_ethtool.c
··· 1225 1225 1226 1226 /* Disable all the interrupts */ 1227 1227 wr32(E1000_IMC, ~0); 1228 + wrfl(); 1228 1229 msleep(10); 1229 1230 1230 1231 /* Define all writable bits for ICS */ ··· 1269 1268 1270 1269 wr32(E1000_IMC, mask); 1271 1270 wr32(E1000_ICS, mask); 1271 + wrfl(); 1272 1272 msleep(10); 1273 1273 1274 1274 if (adapter->test_icr & mask) { ··· 1291 1289 1292 1290 wr32(E1000_IMS, mask); 1293 1291 wr32(E1000_ICS, mask); 1292 + wrfl(); 1294 1293 msleep(10); 1295 1294 1296 1295 if (!(adapter->test_icr & mask)) { ··· 1313 1310 1314 1311 wr32(E1000_IMC, ~mask); 1315 1312 wr32(E1000_ICS, ~mask); 1313 + wrfl(); 1316 1314 msleep(10); 1317 1315 1318 1316 if (adapter->test_icr & mask) { ··· 1325 1321 1326 1322 /* Disable all the interrupts */ 1327 1323 wr32(E1000_IMC, ~0); 1324 + wrfl(); 1328 1325 msleep(10); 1329 1326 1330 1327 /* Unhook test interrupt handler */
+2
drivers/net/igb/igb_main.c
··· 1052 1052 kfree(adapter->vf_data); 1053 1053 adapter->vf_data = NULL; 1054 1054 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1055 + wrfl(); 1055 1056 msleep(100); 1056 1057 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1057 1058 } ··· 2199 2198 kfree(adapter->vf_data); 2200 2199 adapter->vf_data = NULL; 2201 2200 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2201 + wrfl(); 2202 2202 msleep(100); 2203 2203 dev_info(&pdev->dev, "IOV Disabled\n"); 2204 2204 }
+2
drivers/net/igbvf/netdev.c
··· 1226 1226 /* disable transmits */ 1227 1227 txdctl = er32(TXDCTL(0)); 1228 1228 ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); 1229 + e1e_flush(); 1229 1230 msleep(10); 1230 1231 1231 1232 /* Setup the HW Tx Head and Tail descriptor pointers */ ··· 1307 1306 /* disable receives */ 1308 1307 rxdctl = er32(RXDCTL(0)); 1309 1308 ew32(RXDCTL(0), rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE); 1309 + e1e_flush(); 1310 1310 msleep(10); 1311 1311 1312 1312 rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc);
+9
drivers/net/ixgb/ixgb_ee.c
··· 57 57 */ 58 58 *eecd_reg = *eecd_reg | IXGB_EECD_SK; 59 59 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 60 + IXGB_WRITE_FLUSH(hw); 60 61 udelay(50); 61 62 } 62 63 ··· 76 75 */ 77 76 *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; 78 77 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 78 + IXGB_WRITE_FLUSH(hw); 79 79 udelay(50); 80 80 } 81 81 ··· 114 112 eecd_reg |= IXGB_EECD_DI; 115 113 116 114 IXGB_WRITE_REG(hw, EECD, eecd_reg); 115 + IXGB_WRITE_FLUSH(hw); 117 116 118 117 udelay(50); 119 118 ··· 209 206 /* Deselect EEPROM */ 210 207 eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); 211 208 IXGB_WRITE_REG(hw, EECD, eecd_reg); 209 + IXGB_WRITE_FLUSH(hw); 212 210 udelay(50); 213 211 214 212 /* Clock high */ 215 213 eecd_reg |= IXGB_EECD_SK; 216 214 IXGB_WRITE_REG(hw, EECD, eecd_reg); 215 + IXGB_WRITE_FLUSH(hw); 217 216 udelay(50); 218 217 219 218 /* Select EEPROM */ 220 219 eecd_reg |= IXGB_EECD_CS; 221 220 IXGB_WRITE_REG(hw, EECD, eecd_reg); 221 + IXGB_WRITE_FLUSH(hw); 222 222 udelay(50); 223 223 224 224 /* Clock low */ 225 225 eecd_reg &= ~IXGB_EECD_SK; 226 226 IXGB_WRITE_REG(hw, EECD, eecd_reg); 227 + IXGB_WRITE_FLUSH(hw); 227 228 udelay(50); 228 229 } 229 230 ··· 246 239 /* Rising edge of clock */ 247 240 eecd_reg |= IXGB_EECD_SK; 248 241 IXGB_WRITE_REG(hw, EECD, eecd_reg); 242 + IXGB_WRITE_FLUSH(hw); 249 243 udelay(50); 250 244 251 245 /* Falling edge of clock */ 252 246 eecd_reg &= ~IXGB_EECD_SK; 253 247 IXGB_WRITE_REG(hw, EECD, eecd_reg); 248 + IXGB_WRITE_FLUSH(hw); 254 249 udelay(50); 255 250 } 256 251
+2
drivers/net/ixgb/ixgb_hw.c
··· 149 149 */ 150 150 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 151 151 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 152 + IXGB_WRITE_FLUSH(hw); 152 153 msleep(IXGB_DELAY_BEFORE_RESET); 153 154 154 155 /* Issue a global reset to the MAC. This will reset the chip's ··· 1221 1220 ctrl &= ~IXGB_CTRL0_SDP2; 1222 1221 ctrl |= IXGB_CTRL0_SDP3; 1223 1222 IXGB_WRITE_REG(hw, CTRL0, ctrl); 1223 + IXGB_WRITE_FLUSH(hw); 1224 1224 1225 1225 /* SerDes needs extra delay */ 1226 1226 msleep(IXGB_SUN_PHY_RESET_DELAY);
+1
drivers/net/ixgbe/ixgbe_common.c
··· 2632 2632 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2633 2633 autoc_reg |= IXGBE_AUTOC_FLU; 2634 2634 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2635 + IXGBE_WRITE_FLUSH(hw); 2635 2636 usleep_range(10000, 20000); 2636 2637 } 2637 2638
+5
drivers/net/ixgbe/ixgbe_ethtool.c
··· 1378 1378 1379 1379 /* Disable all the interrupts */ 1380 1380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1381 + IXGBE_WRITE_FLUSH(&adapter->hw); 1381 1382 usleep_range(10000, 20000); 1382 1383 1383 1384 /* Test each interrupt */ ··· 1399 1398 ~mask & 0x00007FFF); 1400 1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1401 1400 ~mask & 0x00007FFF); 1401 + IXGBE_WRITE_FLUSH(&adapter->hw); 1402 1402 usleep_range(10000, 20000); 1403 1403 1404 1404 if (adapter->test_icr & mask) { ··· 1417 1415 adapter->test_icr = 0; 1418 1416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1419 1417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1418 + IXGBE_WRITE_FLUSH(&adapter->hw); 1420 1419 usleep_range(10000, 20000); 1421 1420 1422 1421 if (!(adapter->test_icr &mask)) { ··· 1438 1435 ~mask & 0x00007FFF); 1439 1436 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1440 1437 ~mask & 0x00007FFF); 1438 + IXGBE_WRITE_FLUSH(&adapter->hw); 1441 1439 usleep_range(10000, 20000); 1442 1440 1443 1441 if (adapter->test_icr) { ··· 1450 1446 1451 1447 /* Disable all the interrupts */ 1452 1448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1449 + IXGBE_WRITE_FLUSH(&adapter->hw); 1453 1450 usleep_range(10000, 20000); 1454 1451 1455 1452 /* Unhook test interrupt handler */
+1
drivers/net/ixgbe/ixgbe_main.c
··· 184 184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 185 185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 186 186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 187 + IXGBE_WRITE_FLUSH(hw); 187 188 188 189 /* take a breather then clean up driver data */ 189 190 msleep(100);
+3
drivers/net/ixgbe/ixgbe_phy.c
··· 1585 1585 *i2cctl |= IXGBE_I2C_CLK_OUT; 1586 1586 1587 1587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1588 + IXGBE_WRITE_FLUSH(hw); 1588 1589 1589 1590 /* SCL rise time (1000ns) */ 1590 1591 udelay(IXGBE_I2C_T_RISE); ··· 1606 1605 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1607 1606 1608 1607 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1608 + IXGBE_WRITE_FLUSH(hw); 1609 1609 1610 1610 /* SCL fall time (300ns) */ 1611 1611 udelay(IXGBE_I2C_T_FALL); ··· 1630 1628 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1631 1629 1632 1630 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1631 + IXGBE_WRITE_FLUSH(hw); 1633 1632 1634 1633 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1635 1634 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
+1
drivers/net/ixgbe/ixgbe_x540.c
··· 162 162 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 163 163 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 164 164 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 165 + IXGBE_WRITE_FLUSH(hw); 165 166 166 167 msleep(50); 167 168