Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'tegra-for-4.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late

Merge "arm64: tegra: Device tree changes for v4.8-rc1" from Thierry Reding:

A slew of updates for Tegra210 support: PMIC and regulator additions,
which in turn allow a bunch of features to be enabled. Some assemblies
of the Jetson TX1 come with a DSI panel that is now supported. For all
other assemblies, this set of changes enables the HDMI output. Jetson
TX1 can now also make use of the XUSB controller.

PMIC and regulator support is also added for Smaug, which will allow a
number of interesting feature additions in future releases.

* tag 'tegra-for-4.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable HDMI on Jetson TX1
arm64: tegra: Add sor1_src clock
arm64: tegra: Add XUSB powergates on Tegra210
arm64: tegra: Add DPAUX pinctrl bindings
arm64: tegra: Add ACONNECT bus node for Tegra210
arm64: tegra: Add audio powergate node for Tegra210
arm64: tegra: Add regulators for Tegra210 Smaug
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
arm64: tegra: Enable XUSB controller on Jetson TX1
arm64: tegra: Enable debug serial on Jetson TX1
arm64: tegra: Add Tegra210 XUSB controller
arm64: tegra: Add Tegra210 XUSB pad controller
arm64: tegra: Add DSI panel on Jetson TX1
arm64: tegra: p2597: Add SDMMC power supplies
arm64: tegra: Add PMIC support on Jetson TX1

+1218 -1
+249
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
··· 1 + #include <dt-bindings/mfd/max77620.h> 2 + 1 3 #include "tegra210.dtsi" 2 4 3 5 / { ··· 7 5 compatible = "nvidia,p2180", "nvidia,tegra210"; 8 6 9 7 aliases { 8 + rtc0 = "/i2c@7000d000/pmic@3c"; 10 9 rtc1 = "/rtc@7000e000"; 11 10 serial0 = &uarta; 11 + }; 12 + 13 + chosen { 14 + stdout-path = "serial0:115200n8"; 12 15 }; 13 16 14 17 memory { ··· 24 17 /* debug port */ 25 18 serial@70006000 { 26 19 status = "okay"; 20 + }; 21 + 22 + i2c@7000d000 { 23 + status = "okay"; 24 + clock-frequency = <400000>; 25 + 26 + pmic: pmic@3c { 27 + compatible = "maxim,max77620"; 28 + reg = <0x3c>; 29 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 30 + 31 + #interrupt-cells = <2>; 32 + interrupt-controller; 33 + 34 + #gpio-cells = <2>; 35 + gpio-controller; 36 + 37 + pinctrl-names = "default"; 38 + pinctrl-0 = <&max77620_default>; 39 + 40 + max77620_default: pinmux { 41 + gpio0 { 42 + pins = "gpio0"; 43 + function = "gpio"; 44 + }; 45 + 46 + gpio1 { 47 + pins = "gpio1"; 48 + function = "fps-out"; 49 + drive-push-pull = <1>; 50 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 51 + maxim,active-fps-power-up-slot = <7>; 52 + maxim,active-fps-power-down-slot = <0>; 53 + }; 54 + 55 + gpio2_3 { 56 + pins = "gpio2", "gpio3"; 57 + function = "fps-out"; 58 + drive-open-drain = <1>; 59 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 60 + }; 61 + 62 + gpio4 { 63 + pins = "gpio4"; 64 + function = "32k-out1"; 65 + }; 66 + 67 + gpio5_6_7 { 68 + pins = "gpio5", "gpio6", "gpio7"; 69 + function = "gpio"; 70 + drive-push-pull = <1>; 71 + }; 72 + }; 73 + 74 + fps { 75 + fps0 { 76 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 77 + maxim,suspend-fps-time-period-us = <1280>; 78 + }; 79 + 80 + fps1 { 81 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 82 + maxim,suspend-fps-time-period-us = <1280>; 83 + }; 84 + 85 + fps2 { 86 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 87 + }; 88 + }; 89 + 90 + regulators { 91 + in-ldo0-1-supply = <&vdd_pre>; 92 + in-ldo7-8-supply = <&vdd_pre>; 93 + in-sd3-supply = <&vdd_5v0_sys>; 94 + 95 + vdd_soc: sd0 { 96 + regulator-name = "VDD_SOC"; 97 + regulator-min-microvolt = <600000>; 98 + regulator-max-microvolt = <1400000>; 99 + regulator-always-on; 100 + regulator-boot-on; 101 + 102 + regulator-enable-ramp-delay = <146>; 103 + regulator-ramp-delay = <27500>; 104 + 105 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 106 + }; 107 + 108 + vdd_ddr: sd1 { 109 + regulator-name = "VDD_DDR_1V1_PMIC"; 110 + regulator-always-on; 111 + regulator-boot-on; 112 + 113 + regulator-enable-ramp-delay = <130>; 114 + regulator-ramp-delay = <27500>; 115 + 116 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 117 + }; 118 + 119 + vdd_pre: sd2 { 120 + regulator-name = "VDD_PRE_REG_1V35"; 121 + regulator-min-microvolt = <1350000>; 122 + regulator-max-microvolt = <1350000>; 123 + 124 + regulator-enable-ramp-delay = <176>; 125 + regulator-ramp-delay = <27500>; 126 + 127 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 128 + }; 129 + 130 + vdd_1v8: sd3 { 131 + regulator-name = "VDD_1V8"; 132 + regulator-min-microvolt = <1800000>; 133 + regulator-max-microvolt = <1800000>; 134 + regulator-always-on; 135 + regulator-boot-on; 136 + 137 + regulator-enable-ramp-delay = <242>; 138 + regulator-ramp-delay = <27500>; 139 + 140 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 141 + }; 142 + 143 + vdd_sys_1v2: ldo0 { 144 + regulator-name = "AVDD_SYS_1V2"; 145 + regulator-min-microvolt = <1200000>; 146 + regulator-max-microvolt = <1200000>; 147 + regulator-always-on; 148 + regulator-boot-on; 149 + 150 + regulator-enable-ramp-delay = <26>; 151 + regulator-ramp-delay = <100000>; 152 + 153 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 154 + }; 155 + 156 + vdd_pex_1v05: ldo1 { 157 + regulator-name = "VDD_PEX_1V05"; 158 + regulator-min-microvolt = <1050000>; 159 + regulator-max-microvolt = <1050000>; 160 + 161 + regulator-enable-ramp-delay = <22>; 162 + regulator-ramp-delay = <100000>; 163 + 164 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 165 + }; 166 + 167 + vddio_sdmmc: ldo2 { 168 + regulator-name = "VDDIO_SDMMC"; 169 + /* 170 + * Technically this supply should have 171 + * a supported range from 1.8 - 3.3 V. 172 + * However, that would cause the SDHCI 173 + * driver to request 2.7 V upon access 174 + * and that in turn will cause traffic 175 + * to be broken. Leave it at 3.3 V for 176 + * now. 177 + */ 178 + regulator-min-microvolt = <3300000>; 179 + regulator-max-microvolt = <3300000>; 180 + regulator-always-on; 181 + regulator-boot-on; 182 + 183 + regulator-enable-ramp-delay = <62>; 184 + regulator-ramp-delay = <100000>; 185 + 186 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 187 + }; 188 + 189 + vdd_cam_hv: ldo3 { 190 + regulator-name = "VDD_CAM_HV"; 191 + regulator-min-microvolt = <2800000>; 192 + regulator-max-microvolt = <2800000>; 193 + 194 + regulator-enable-ramp-delay = <50>; 195 + regulator-ramp-delay = <100000>; 196 + 197 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 198 + }; 199 + 200 + vdd_rtc: ldo4 { 201 + regulator-name = "VDD_RTC"; 202 + regulator-min-microvolt = <850000>; 203 + regulator-max-microvolt = <850000>; 204 + regulator-always-on; 205 + regulator-boot-on; 206 + 207 + regulator-enable-ramp-delay = <22>; 208 + regulator-ramp-delay = <100000>; 209 + 210 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 211 + }; 212 + 213 + vdd_ts_hv: ldo5 { 214 + regulator-name = "VDD_TS_HV"; 215 + regulator-min-microvolt = <3300000>; 216 + regulator-max-microvolt = <3300000>; 217 + 218 + regulator-enable-ramp-delay = <62>; 219 + regulator-ramp-delay = <100000>; 220 + 221 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 222 + }; 223 + 224 + vdd_ts: ldo6 { 225 + regulator-name = "VDD_TS_1V8"; 226 + regulator-min-microvolt = <1800000>; 227 + regulator-max-microvolt = <1800000>; 228 + 229 + regulator-enable-ramp-delay = <36>; 230 + regulator-ramp-delay = <100000>; 231 + 232 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 233 + maxim,active-fps-power-up-slot = <7>; 234 + maxim,active-fps-power-down-slot = <0>; 235 + }; 236 + 237 + avdd_1v05_pll: ldo7 { 238 + regulator-name = "AVDD_1V05_PLL"; 239 + regulator-min-microvolt = <1050000>; 240 + regulator-max-microvolt = <1050000>; 241 + regulator-always-on; 242 + regulator-boot-on; 243 + 244 + regulator-enable-ramp-delay = <24>; 245 + regulator-ramp-delay = <100000>; 246 + 247 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 248 + }; 249 + 250 + avdd_1v05: ldo8 { 251 + regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 252 + regulator-min-microvolt = <1050000>; 253 + regulator-max-microvolt = <1050000>; 254 + 255 + regulator-enable-ramp-delay = <22>; 256 + regulator-ramp-delay = <100000>; 257 + 258 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 259 + }; 260 + }; 261 + }; 27 262 }; 28 263 29 264 pmc@7000e400 {
+45
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
··· 6 6 / { 7 7 model = "NVIDIA Jetson TX1 Developer Kit"; 8 8 compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 9 + 10 + host1x@50000000 { 11 + dsi@54300000 { 12 + status = "okay"; 13 + 14 + avdd-dsi-csi-supply = <&vdd_dsi_csi>; 15 + 16 + panel@0 { 17 + compatible = "auo,b080uan01"; 18 + reg = <0>; 19 + 20 + enable-gpios = <&gpio TEGRA_GPIO(V, 2) 21 + GPIO_ACTIVE_HIGH>; 22 + power-supply = <&vdd_5v0_io>; 23 + backlight = <&backlight>; 24 + }; 25 + }; 26 + }; 27 + 28 + i2c@7000c400 { 29 + backlight: backlight@2c { 30 + compatible = "ti,lp8557"; 31 + reg = <0x2c>; 32 + 33 + dev-ctrl = /bits/ 8 <0x80>; 34 + init-brt = /bits/ 8 <0xff>; 35 + 36 + pwm-period = <29334>; 37 + 38 + pwms = <&pwm 0 29334>; 39 + pwm-names = "lp8557"; 40 + 41 + /* 3 LED string */ 42 + rom_14h { 43 + rom-addr = /bits/ 8 <0x14>; 44 + rom-val = /bits/ 8 <0x87>; 45 + }; 46 + 47 + /* boost frequency 1 MHz */ 48 + rom_13h { 49 + rom-addr = /bits/ 8 <0x13>; 50 + rom-val = /bits/ 8 <0x01>; 51 + }; 52 + }; 53 + }; 9 54 };
+319
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
··· 4 4 model = "NVIDIA Tegra210 P2597 I/O board"; 5 5 compatible = "nvidia,p2597", "nvidia,tegra210"; 6 6 7 + host1x@50000000 { 8 + dpaux@54040000 { 9 + status = "okay"; 10 + }; 11 + 12 + sor@54580000 { 13 + status = "okay"; 14 + 15 + avdd-io-supply = <&avdd_1v05>; 16 + vdd-pll-supply = <&vdd_1v8>; 17 + hdmi-supply = <&vdd_hdmi>; 18 + 19 + nvidia,ddc-i2c-bus = <&hdmi_ddc>; 20 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 21 + GPIO_ACTIVE_LOW>; 22 + }; 23 + }; 24 + 7 25 pinmux: pinmux@700008d4 { 8 26 pinctrl-names = "boot"; 9 27 pinctrl-0 = <&state_boot>; ··· 1279 1261 }; 1280 1262 }; 1281 1263 1264 + pwm@7000a000 { 1265 + status = "okay"; 1266 + }; 1267 + 1268 + i2c@7000c400 { 1269 + status = "okay"; 1270 + clock-frequency = <100000>; 1271 + 1272 + exp1: gpio@74 { 1273 + compatible = "ti,tca9539"; 1274 + reg = <0x74>; 1275 + 1276 + #gpio-cells = <2>; 1277 + gpio-controller; 1278 + }; 1279 + }; 1280 + 1281 + /* HDMI DDC */ 1282 + hdmi_ddc: i2c@7000c700 { 1283 + status = "okay"; 1284 + clock-frequency = <100000>; 1285 + }; 1286 + 1287 + usb@70090000 { 1288 + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 1289 + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 1290 + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1291 + <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, 1292 + <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, 1293 + <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; 1294 + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", 1295 + "usb3-1"; 1296 + 1297 + dvddio-pex-supply = <&vdd_pex_1v05>; 1298 + hvddio-pex-supply = <&vdd_1v8>; 1299 + avdd-usb-supply = <&vdd_3v3_sys>; 1300 + /* XXX what are these? */ 1301 + avdd-pll-utmip-supply = <&vdd_1v8>; 1302 + avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 1303 + dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; 1304 + hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; 1305 + 1306 + status = "okay"; 1307 + }; 1308 + 1309 + padctl@7009f000 { 1310 + status = "okay"; 1311 + 1312 + pads { 1313 + usb2 { 1314 + status = "okay"; 1315 + 1316 + lanes { 1317 + usb2-0 { 1318 + nvidia,function = "xusb"; 1319 + status = "okay"; 1320 + }; 1321 + 1322 + usb2-1 { 1323 + nvidia,function = "xusb"; 1324 + status = "okay"; 1325 + }; 1326 + 1327 + usb2-2 { 1328 + nvidia,function = "xusb"; 1329 + status = "okay"; 1330 + }; 1331 + 1332 + usb2-3 { 1333 + nvidia,function = "xusb"; 1334 + status = "okay"; 1335 + }; 1336 + }; 1337 + }; 1338 + 1339 + pcie { 1340 + status = "okay"; 1341 + 1342 + lanes { 1343 + pcie-0 { 1344 + nvidia,function = "pcie-x1"; 1345 + status = "okay"; 1346 + }; 1347 + 1348 + pcie-1 { 1349 + nvidia,function = "pcie-x4"; 1350 + status = "okay"; 1351 + }; 1352 + 1353 + pcie-2 { 1354 + nvidia,function = "pcie-x4"; 1355 + status = "okay"; 1356 + }; 1357 + 1358 + pcie-3 { 1359 + nvidia,function = "pcie-x4"; 1360 + status = "okay"; 1361 + }; 1362 + 1363 + pcie-4 { 1364 + nvidia,function = "pcie-x4"; 1365 + status = "okay"; 1366 + }; 1367 + 1368 + pcie-5 { 1369 + nvidia,function = "usb3-ss"; 1370 + status = "okay"; 1371 + }; 1372 + 1373 + pcie-6 { 1374 + nvidia,function = "usb3-ss"; 1375 + status = "okay"; 1376 + }; 1377 + }; 1378 + }; 1379 + 1380 + sata { 1381 + status = "okay"; 1382 + 1383 + lanes { 1384 + sata-0 { 1385 + nvidia,function = "sata"; 1386 + status = "okay"; 1387 + }; 1388 + }; 1389 + }; 1390 + }; 1391 + 1392 + ports { 1393 + usb2-0 { 1394 + status = "okay"; 1395 + mode = "otg"; 1396 + }; 1397 + 1398 + usb2-1 { 1399 + status = "okay"; 1400 + vbus-supply = <&vdd_5v0_rtl>; 1401 + mode = "host"; 1402 + }; 1403 + 1404 + usb2-2 { 1405 + status = "okay"; 1406 + vbus-supply = <&vdd_usb_vbus>; 1407 + mode = "host"; 1408 + }; 1409 + 1410 + usb2-3 { 1411 + status = "okay"; 1412 + mode = "host"; 1413 + }; 1414 + 1415 + usb3-0 { 1416 + nvidia,usb2-companion = <1>; 1417 + status = "okay"; 1418 + }; 1419 + 1420 + usb3-1 { 1421 + nvidia,usb2-companion = <2>; 1422 + status = "okay"; 1423 + }; 1424 + }; 1425 + }; 1426 + 1282 1427 /* MMC/SD */ 1283 1428 sdhci@700b0000 { 1284 1429 status = "okay"; ··· 1449 1268 no-1-8-v; 1450 1269 1451 1270 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 1271 + 1272 + vqmmc-supply = <&vddio_sdmmc>; 1273 + vmmc-supply = <&vdd_3v3_sd>; 1274 + }; 1275 + 1276 + regulators { 1277 + compatible = "simple-bus"; 1278 + #address-cells = <1>; 1279 + #size-cells = <0>; 1280 + 1281 + vdd_sys_mux: regulator@0 { 1282 + compatible = "regulator-fixed"; 1283 + reg = <0>; 1284 + regulator-name = "VDD_SYS_MUX"; 1285 + regulator-min-microvolt = <5000000>; 1286 + regulator-max-microvolt = <5000000>; 1287 + regulator-always-on; 1288 + regulator-boot-on; 1289 + }; 1290 + 1291 + vdd_5v0_sys: regulator@1 { 1292 + compatible = "regulator-fixed"; 1293 + reg = <1>; 1294 + regulator-name = "VDD_5V0_SYS"; 1295 + regulator-min-microvolt = <5000000>; 1296 + regulator-max-microvolt = <5000000>; 1297 + regulator-always-on; 1298 + regulator-boot-on; 1299 + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 1300 + enable-active-high; 1301 + vin-supply = <&vdd_sys_mux>; 1302 + }; 1303 + 1304 + vdd_3v3_sys: regulator@2 { 1305 + compatible = "regulator-fixed"; 1306 + reg = <2>; 1307 + regulator-name = "VDD_3V3_SYS"; 1308 + regulator-min-microvolt = <3300000>; 1309 + regulator-max-microvolt = <3300000>; 1310 + regulator-always-on; 1311 + regulator-boot-on; 1312 + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1313 + enable-active-high; 1314 + vin-supply = <&vdd_sys_mux>; 1315 + 1316 + regulator-enable-ramp-delay = <160>; 1317 + regulator-disable-ramp-delay = <10000>; 1318 + }; 1319 + 1320 + vdd_5v0_io: regulator@3 { 1321 + compatible = "regulator-fixed"; 1322 + reg = <3>; 1323 + regulator-name = "VDD_5V0_IO_SYS"; 1324 + regulator-min-microvolt = <5000000>; 1325 + regulator-max-microvolt = <5000000>; 1326 + regulator-always-on; 1327 + regulator-boot-on; 1328 + }; 1329 + 1330 + vdd_3v3_sd: regulator@4 { 1331 + compatible = "regulator-fixed"; 1332 + reg = <4>; 1333 + regulator-name = "VDD_3V3_SD"; 1334 + regulator-min-microvolt = <3300000>; 1335 + regulator-max-microvolt = <3300000>; 1336 + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; 1337 + enable-active-high; 1338 + vin-supply = <&vdd_3v3_sys>; 1339 + 1340 + regulator-enable-ramp-delay = <472>; 1341 + regulator-disable-ramp-delay = <4880>; 1342 + }; 1343 + 1344 + vdd_dsi_csi: regulator@5 { 1345 + compatible = "regulator-fixed"; 1346 + reg = <5>; 1347 + regulator-name = "AVDD_DSI_CSI_1V2"; 1348 + regulator-min-microvolt = <1200000>; 1349 + regulator-max-microvolt = <1200000>; 1350 + vin-supply = <&vdd_sys_1v2>; 1351 + }; 1352 + 1353 + vdd_3v3_dis: regulator@6 { 1354 + compatible = "regulator-fixed"; 1355 + reg = <6>; 1356 + regulator-name = "VDD_DIS_3V3_LCD"; 1357 + regulator-min-microvolt = <3300000>; 1358 + regulator-max-microvolt = <3300000>; 1359 + regulator-always-on; 1360 + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 1361 + enable-active-high; 1362 + vin-supply = <&vdd_3v3_sys>; 1363 + }; 1364 + 1365 + vdd_1v8_dis: regulator@7 { 1366 + compatible = "regulator-fixed"; 1367 + reg = <7>; 1368 + regulator-name = "VDD_LCD_1V8_DIS"; 1369 + regulator-min-microvolt = <1800000>; 1370 + regulator-max-microvolt = <1800000>; 1371 + regulator-always-on; 1372 + gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; 1373 + enable-active-high; 1374 + vin-supply = <&vdd_1v8>; 1375 + }; 1376 + 1377 + vdd_5v0_rtl: regulator@8 { 1378 + compatible = "regulator-fixed"; 1379 + reg = <8>; 1380 + regulator-name = "RTL_5V"; 1381 + regulator-min-microvolt = <5000000>; 1382 + regulator-max-microvolt = <5000000>; 1383 + gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 1384 + enable-active-high; 1385 + vin-supply = <&vdd_5v0_sys>; 1386 + }; 1387 + 1388 + vdd_usb_vbus: regulator@9 { 1389 + compatible = "regulator-fixed"; 1390 + reg = <9>; 1391 + regulator-name = "USB_VBUS_EN1"; 1392 + regulator-min-microvolt = <5000000>; 1393 + regulator-max-microvolt = <5000000>; 1394 + gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 1395 + enable-active-high; 1396 + vin-supply = <&vdd_5v0_sys>; 1397 + }; 1398 + 1399 + vdd_hdmi: regulator@10 { 1400 + compatible = "regulator-fixed"; 1401 + reg = <10>; 1402 + regulator-name = "VDD_HDMI_5V0"; 1403 + regulator-min-microvolt = <5000000>; 1404 + regulator-max-microvolt = <5000000>; 1405 + gpio = <&exp1 12 GPIO_ACTIVE_LOW>; 1406 + enable-active-high; 1407 + vin-supply = <&vdd_5v0_sys>; 1408 + }; 1452 1409 }; 1453 1410 1454 1411 gpio-keys {
+314
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
··· 1 1 /dts-v1/; 2 2 3 3 #include <dt-bindings/input/input.h> 4 + #include <dt-bindings/mfd/max77620.h> 4 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 6 6 7 #include "tegra210.dtsi" ··· 1328 1327 }; 1329 1328 }; 1330 1329 1330 + i2c@7000d000 { 1331 + status = "okay"; 1332 + clock-frequency = <1000000>; 1333 + 1334 + max77620: max77620@3c { 1335 + compatible = "maxim,max77620"; 1336 + reg = <0x3c>; 1337 + interrupts = <0 86 IRQ_TYPE_NONE>; 1338 + 1339 + #interrupt-cells = <2>; 1340 + interrupt-controller; 1341 + 1342 + gpio-controller; 1343 + #gpio-cells = <2>; 1344 + 1345 + pinctrl-names = "default"; 1346 + pinctrl-0 = <&max77620_default>; 1347 + 1348 + max77620_default: pinmux@0 { 1349 + pin_gpio { 1350 + pins = "gpio0", "gpio1", "gpio2", "gpio7"; 1351 + function = "gpio"; 1352 + }; 1353 + 1354 + /* 1355 + * GPIO3 is used to en_pp3300, and it is part of power 1356 + * sequence, So it must be sequenced up (automatically 1357 + * set by OTP) and down properly. 1358 + */ 1359 + pin_gpio3 { 1360 + pins = "gpio3"; 1361 + function = "fps-out"; 1362 + drive-open-drain = <1>; 1363 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1364 + maxim,active-fps-power-up-slot = <4>; 1365 + maxim,active-fps-power-down-slot = <2>; 1366 + }; 1367 + 1368 + pin_gpio5_6 { 1369 + pins = "gpio5", "gpio6"; 1370 + function = "gpio"; 1371 + drive-push-pull = <1>; 1372 + }; 1373 + 1374 + pin_32k { 1375 + pins = "gpio4"; 1376 + function = "32k-out1"; 1377 + }; 1378 + }; 1379 + 1380 + fps { 1381 + fps0 { 1382 + maxim,shutdown-fps-time-period-us = <5120>; 1383 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 1384 + }; 1385 + 1386 + fps1 { 1387 + maxim,shutdown-fps-time-period-us = <5120>; 1388 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 1389 + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; 1390 + }; 1391 + 1392 + fps2 { 1393 + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 1394 + }; 1395 + }; 1396 + 1397 + regulators { 1398 + in-ldo0-1-supply = <&pp1350>; 1399 + in-ldo2-supply = <&pp3300>; 1400 + in-ldo3-5-supply = <&pp3300>; 1401 + in-ldo7-8-supply = <&pp1350>; 1402 + 1403 + ppvar_soc: sd0 { 1404 + regulator-name = "PPVAR_SOC"; 1405 + regulator-min-microvolt = <825000>; 1406 + regulator-max-microvolt = <1125000>; 1407 + regulator-always-on; 1408 + regulator-boot-on; 1409 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 1410 + maxim,active-fps-power-up-slot = <1>; 1411 + maxim,active-fps-power-down-slot = <7>; 1412 + }; 1413 + 1414 + pp1100_sd1: sd1 { 1415 + regulator-name = "PP1100"; 1416 + regulator-min-microvolt = <1125000>; 1417 + regulator-max-microvolt = <1125000>; 1418 + regulator-always-on; 1419 + regulator-boot-on; 1420 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1421 + maxim,active-fps-power-up-slot = <5>; 1422 + maxim,active-fps-power-down-slot = <1>; 1423 + }; 1424 + 1425 + pp1350: sd2 { 1426 + regulator-name = "PP1350"; 1427 + regulator-min-microvolt = <1350000>; 1428 + regulator-max-microvolt = <1350000>; 1429 + regulator-always-on; 1430 + regulator-boot-on; 1431 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1432 + maxim,active-fps-power-up-slot = <2>; 1433 + maxim,active-fps-power-down-slot = <5>; 1434 + }; 1435 + 1436 + pp1800: sd3 { 1437 + regulator-name = "PP1800"; 1438 + regulator-min-microvolt = <1800000>; 1439 + regulator-max-microvolt = <1800000>; 1440 + regulator-always-on; 1441 + regulator-boot-on; 1442 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1443 + maxim,active-fps-power-up-slot = <3>; 1444 + maxim,active-fps-power-down-slot = <3>; 1445 + }; 1446 + 1447 + pp1200_avdd: ldo0 { 1448 + regulator-name = "PP1200_AVDD"; 1449 + regulator-min-microvolt = <1200000>; 1450 + regulator-max-microvolt = <1200000>; 1451 + regulator-enable-ramp-delay = <26>; 1452 + regulator-ramp-delay = <100000>; 1453 + regulator-boot-on; 1454 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1455 + maxim,active-fps-power-up-slot = <0>; 1456 + maxim,active-fps-power-down-slot = <7>; 1457 + }; 1458 + 1459 + pp1200_rcam: ldo1 { 1460 + regulator-name = "PP1200_RCAM"; 1461 + regulator-min-microvolt = <1200000>; 1462 + regulator-max-microvolt = <1200000>; 1463 + regulator-enable-ramp-delay = <22>; 1464 + regulator-ramp-delay = <100000>; 1465 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1466 + maxim,active-fps-power-up-slot = <0>; 1467 + maxim,active-fps-power-down-slot = <7>; 1468 + }; 1469 + 1470 + pp_ldo2: ldo2 { 1471 + regulator-name = "PP_LDO2"; 1472 + regulator-min-microvolt = <1800000>; 1473 + regulator-max-microvolt = <1800000>; 1474 + regulator-enable-ramp-delay = <62>; 1475 + regulator-ramp-delay = <11000>; 1476 + regulator-always-on; 1477 + regulator-boot-on; 1478 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1479 + maxim,active-fps-power-up-slot = <0>; 1480 + maxim,active-fps-power-down-slot = <7>; 1481 + }; 1482 + 1483 + pp2800l_rcam: ldo3 { 1484 + regulator-name = "PP2800L_RCAM"; 1485 + regulator-min-microvolt = <2800000>; 1486 + regulator-max-microvolt = <2800000>; 1487 + regulator-enable-ramp-delay = <50>; 1488 + regulator-ramp-delay = <100000>; 1489 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1490 + maxim,active-fps-power-up-slot = <0>; 1491 + maxim,active-fps-power-down-slot = <7>; 1492 + }; 1493 + 1494 + pp100_soc_rtc: ldo4 { 1495 + regulator-name = "PP1100_SOC_RTC"; 1496 + regulator-min-microvolt = <850000>; 1497 + regulator-max-microvolt = <850000>; 1498 + regulator-enable-ramp-delay = <22>; 1499 + regulator-ramp-delay = <100000>; 1500 + regulator-always-on; /* Check this */ 1501 + regulator-boot-on; 1502 + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1503 + maxim,active-fps-power-up-slot = <1>; 1504 + maxim,active-fps-power-down-slot = <7>; 1505 + }; 1506 + 1507 + pp2800l_fcam: ldo5 { 1508 + regulator-name = "PP2800L_FCAM"; 1509 + regulator-min-microvolt = <2800000>; 1510 + regulator-max-microvolt = <2800000>; 1511 + regulator-enable-ramp-delay = <62>; 1512 + regulator-ramp-delay = <100000>; 1513 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1514 + maxim,active-fps-power-up-slot = <0>; 1515 + maxim,active-fps-power-down-slot = <7>; 1516 + }; 1517 + 1518 + ldo6 { 1519 + /* Unused. */ 1520 + regulator-name = "PP_LDO6"; 1521 + regulator-min-microvolt = <1800000>; 1522 + regulator-max-microvolt = <1800000>; 1523 + regulator-enable-ramp-delay = <36>; 1524 + regulator-ramp-delay = <100000>; 1525 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1526 + maxim,active-fps-power-up-slot = <0>; 1527 + maxim,active-fps-power-down-slot = <7>; 1528 + }; 1529 + 1530 + pp1050_avdd: ldo7 { 1531 + regulator-name = "PP1050_AVDD"; 1532 + regulator-min-microvolt = <1050000>; 1533 + regulator-max-microvolt = <1050000>; 1534 + regulator-enable-ramp-delay = <24>; 1535 + regulator-ramp-delay = <100000>; 1536 + regulator-always-on; 1537 + regulator-boot-on; 1538 + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 1539 + maxim,active-fps-power-up-slot = <3>; 1540 + maxim,active-fps-power-down-slot = <4>; 1541 + }; 1542 + 1543 + avddio_1v05: ldo8 { 1544 + regulator-name = "AVDDIO_1V05"; 1545 + regulator-min-microvolt = <1050000>; 1546 + regulator-max-microvolt = <1050000>; 1547 + regulator-enable-ramp-delay = <22>; 1548 + regulator-ramp-delay = <100000>; 1549 + regulator-boot-on; 1550 + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1551 + maxim,active-fps-power-up-slot = <0>; 1552 + maxim,active-fps-power-down-slot = <7>; 1553 + }; 1554 + }; 1555 + }; 1556 + }; 1557 + 1331 1558 pmc@7000e400 { 1332 1559 nvidia,invert-interrupt; 1333 1560 nvidia,suspend-mode = <0>; ··· 1649 1420 psci { 1650 1421 compatible = "arm,psci-1.0"; 1651 1422 method = "smc"; 1423 + }; 1424 + 1425 + regulators { 1426 + compatible = "simple-bus"; 1427 + device_type = "fixed-regulators"; 1428 + #address-cells = <1>; 1429 + #size-cells = <0>; 1430 + 1431 + ppvar_sys: regulator@0 { 1432 + compatible = "regulator-fixed"; 1433 + reg = <0>; 1434 + regulator-name = "PPVAR_SYS"; 1435 + regulator-min-microvolt = <4400000>; 1436 + regulator-max-microvolt = <4400000>; 1437 + regulator-always-on; 1438 + }; 1439 + 1440 + pplcd_vdd: regulator@1 { 1441 + compatible = "regulator-fixed"; 1442 + reg = <1>; 1443 + regulator-name = "PPLCD_VDD"; 1444 + regulator-min-microvolt = <4400000>; 1445 + regulator-max-microvolt = <4400000>; 1446 + gpio = <&gpio TEGRA_GPIO(V, 4) 0>; 1447 + enable-active-high; 1448 + regulator-boot-on; 1449 + }; 1450 + 1451 + pp3000_always: regulator@2 { 1452 + compatible = "regulator-fixed"; 1453 + reg = <2>; 1454 + regulator-name = "PP3000_ALWAYS"; 1455 + regulator-min-microvolt = <3000000>; 1456 + regulator-max-microvolt = <3000000>; 1457 + regulator-always-on; 1458 + }; 1459 + 1460 + pp3300: regulator@3 { 1461 + compatible = "regulator-fixed"; 1462 + reg = <3>; 1463 + regulator-name = "PP3300"; 1464 + regulator-min-microvolt = <3300000>; 1465 + regulator-max-microvolt = <3300000>; 1466 + regulator-boot-on; 1467 + regulator-always-on; 1468 + enable-active-high; 1469 + }; 1470 + 1471 + pp5000: regulator@4 { 1472 + compatible = "regulator-fixed"; 1473 + reg = <4>; 1474 + regulator-name = "PP5000"; 1475 + regulator-min-microvolt = <5000000>; 1476 + regulator-max-microvolt = <5000000>; 1477 + regulator-always-on; 1478 + }; 1479 + 1480 + pp1800_lcdio: regulator@5 { 1481 + compatible = "regulator-fixed"; 1482 + reg = <5>; 1483 + regulator-name = "PP1800_LCDIO"; 1484 + regulator-min-microvolt = <1800000>; 1485 + regulator-max-microvolt = <1800000>; 1486 + gpio = <&gpio TEGRA_GPIO(V, 3) 0>; 1487 + enable-active-high; 1488 + regulator-boot-on; 1489 + }; 1490 + 1491 + pp1800_cam: regulator@6 { 1492 + compatible = "regulator-fixed"; 1493 + reg= <6>; 1494 + regulator-name = "PP1800_CAM"; 1495 + regulator-min-microvolt = <1800000>; 1496 + regulator-max-microvolt = <1800000>; 1497 + gpio = <&gpio TEGRA_GPIO(K, 3) 0>; 1498 + enable-active-high; 1499 + }; 1500 + 1501 + usbc_vbus: regulator@7 { 1502 + compatible = "regulator-fixed"; 1503 + reg = <7>; 1504 + regulator-name = "USBC_VBUS"; 1505 + regulator-min-microvolt = <5000000>; 1506 + regulator-max-microvolt = <5000000>; 1507 + }; 1652 1508 }; 1653 1509 };
+291 -1
arch/arm64/boot/dts/nvidia/tegra210.dtsi
··· 35 35 resets = <&tegra_car 207>; 36 36 reset-names = "dpaux"; 37 37 status = "disabled"; 38 + 39 + state_dpaux1_aux: pinmux-aux { 40 + groups = "dpaux-io"; 41 + function = "aux"; 42 + }; 43 + 44 + state_dpaux1_i2c: pinmux-i2c { 45 + groups = "dpaux-io"; 46 + function = "i2c"; 47 + }; 48 + 49 + state_dpaux1_off: pinmux-off { 50 + groups = "dpaux-io"; 51 + function = "off"; 52 + }; 53 + 54 + i2c-bus { 55 + #address-cells = <1>; 56 + #size-cells = <0>; 57 + }; 38 58 }; 39 59 40 60 vi@54080000 { ··· 174 154 clock-names = "sor", "parent", "dp", "safe"; 175 155 resets = <&tegra_car 182>; 176 156 reset-names = "sor"; 157 + pinctrl-0 = <&state_dpaux_aux>; 158 + pinctrl-1 = <&state_dpaux_i2c>; 159 + pinctrl-2 = <&state_dpaux_off>; 160 + pinctrl-names = "aux", "i2c", "off"; 177 161 status = "disabled"; 178 162 }; 179 163 ··· 186 162 reg = <0x0 0x54580000 0x0 0x00040000>; 187 163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 188 164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 165 + <&tegra_car TEGRA210_CLK_SOR1_SRC>, 189 166 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 190 167 <&tegra_car TEGRA210_CLK_PLL_DP>, 191 168 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 192 - clock-names = "sor", "parent", "dp", "safe"; 169 + clock-names = "sor", "source", "parent", "dp", "safe"; 193 170 resets = <&tegra_car 183>; 194 171 reset-names = "sor"; 172 + pinctrl-0 = <&state_dpaux1_aux>; 173 + pinctrl-1 = <&state_dpaux1_i2c>; 174 + pinctrl-2 = <&state_dpaux1_off>; 175 + pinctrl-names = "aux", "i2c", "off"; 195 176 status = "disabled"; 196 177 }; 197 178 ··· 210 181 resets = <&tegra_car 181>; 211 182 reset-names = "dpaux"; 212 183 status = "disabled"; 184 + 185 + state_dpaux_aux: pinmux-aux { 186 + groups = "dpaux-io"; 187 + function = "aux"; 188 + }; 189 + 190 + state_dpaux_i2c: pinmux-i2c { 191 + groups = "dpaux-io"; 192 + function = "i2c"; 193 + }; 194 + 195 + state_dpaux_off: pinmux-off { 196 + groups = "dpaux-io"; 197 + function = "off"; 198 + }; 199 + 200 + i2c-bus { 201 + #address-cells = <1>; 202 + #size-cells = <0>; 203 + }; 213 204 }; 214 205 215 206 isp@54600000 { ··· 527 478 reset-names = "i2c"; 528 479 dmas = <&apbdma 26>, <&apbdma 26>; 529 480 dma-names = "rx", "tx"; 481 + pinctrl-0 = <&state_dpaux1_i2c>; 482 + pinctrl-1 = <&state_dpaux1_off>; 483 + pinctrl-names = "default", "idle"; 530 484 status = "disabled"; 531 485 }; 532 486 ··· 560 508 reset-names = "i2c"; 561 509 dmas = <&apbdma 30>, <&apbdma 30>; 562 510 dma-names = "rx", "tx"; 511 + pinctrl-0 = <&state_dpaux_i2c>; 512 + pinctrl-1 = <&state_dpaux_off>; 513 + pinctrl-names = "default", "idle"; 563 514 status = "disabled"; 564 515 }; 565 516 ··· 639 584 reg = <0x0 0x7000e400 0x0 0x400>; 640 585 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 641 586 clock-names = "pclk", "clk32k_in"; 587 + 588 + powergates { 589 + pd_audio: aud { 590 + clocks = <&tegra_car TEGRA210_CLK_APE>, 591 + <&tegra_car TEGRA210_CLK_APB2APE>; 592 + resets = <&tegra_car 198>; 593 + #power-domain-cells = <0>; 594 + }; 595 + 596 + pd_xusbss: xusba { 597 + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 598 + clock-names = "xusb-ss"; 599 + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 600 + reset-names = "xusb-ss"; 601 + #power-domain-cells = <0>; 602 + }; 603 + 604 + pd_xusbdev: xusbb { 605 + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 606 + clock-names = "xusb-dev"; 607 + resets = <&tegra_car 95>; 608 + reset-names = "xusb-dev"; 609 + #power-domain-cells = <0>; 610 + }; 611 + 612 + pd_xusbhost: xusbc { 613 + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 614 + clock-names = "xusb-host"; 615 + resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 616 + reset-names = "xusb-host"; 617 + #power-domain-cells = <0>; 618 + }; 619 + }; 642 620 }; 643 621 644 622 fuse@7000f800 { ··· 707 619 <&tegra_car 111>; /* hda2codec_2x */ 708 620 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 709 621 status = "disabled"; 622 + }; 623 + 624 + usb@70090000 { 625 + compatible = "nvidia,tegra210-xusb"; 626 + reg = <0x0 0x70090000 0x0 0x8000>, 627 + <0x0 0x70098000 0x0 0x1000>, 628 + <0x0 0x70099000 0x0 0x1000>; 629 + reg-names = "hcd", "fpci", "ipfs"; 630 + 631 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 632 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 633 + 634 + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 635 + <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 636 + <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 637 + <&tegra_car TEGRA210_CLK_XUSB_SS>, 638 + <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 639 + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 640 + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 641 + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 642 + <&tegra_car TEGRA210_CLK_PLL_U_480M>, 643 + <&tegra_car TEGRA210_CLK_CLK_M>, 644 + <&tegra_car TEGRA210_CLK_PLL_E>; 645 + clock-names = "xusb_host", "xusb_host_src", 646 + "xusb_falcon_src", "xusb_ss", 647 + "xusb_ss_div2", "xusb_ss_src", 648 + "xusb_hs_src", "xusb_fs_src", 649 + "pll_u_480m", "clk_m", "pll_e"; 650 + resets = <&tegra_car 89>, <&tegra_car 156>, 651 + <&tegra_car 143>; 652 + reset-names = "xusb_host", "xusb_ss", "xusb_src"; 653 + 654 + nvidia,xusb-padctl = <&padctl>; 655 + 656 + status = "disabled"; 657 + }; 658 + 659 + padctl: padctl@7009f000 { 660 + compatible = "nvidia,tegra210-xusb-padctl"; 661 + reg = <0x0 0x7009f000 0x0 0x1000>; 662 + resets = <&tegra_car 142>; 663 + reset-names = "padctl"; 664 + 665 + status = "disabled"; 666 + 667 + pads { 668 + usb2 { 669 + clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 670 + clock-names = "trk"; 671 + status = "disabled"; 672 + 673 + lanes { 674 + usb2-0 { 675 + status = "disabled"; 676 + #phy-cells = <0>; 677 + }; 678 + 679 + usb2-1 { 680 + status = "disabled"; 681 + #phy-cells = <0>; 682 + }; 683 + 684 + usb2-2 { 685 + status = "disabled"; 686 + #phy-cells = <0>; 687 + }; 688 + 689 + usb2-3 { 690 + status = "disabled"; 691 + #phy-cells = <0>; 692 + }; 693 + }; 694 + }; 695 + 696 + hsic { 697 + clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 698 + clock-names = "trk"; 699 + status = "disabled"; 700 + 701 + lanes { 702 + hsic-0 { 703 + status = "disabled"; 704 + #phy-cells = <0>; 705 + }; 706 + 707 + hsic-1 { 708 + status = "disabled"; 709 + #phy-cells = <0>; 710 + }; 711 + }; 712 + }; 713 + 714 + pcie { 715 + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 716 + clock-names = "pll"; 717 + resets = <&tegra_car 205>; 718 + reset-names = "phy"; 719 + status = "disabled"; 720 + 721 + lanes { 722 + pcie-0 { 723 + status = "disabled"; 724 + #phy-cells = <0>; 725 + }; 726 + 727 + pcie-1 { 728 + status = "disabled"; 729 + #phy-cells = <0>; 730 + }; 731 + 732 + pcie-2 { 733 + status = "disabled"; 734 + #phy-cells = <0>; 735 + }; 736 + 737 + pcie-3 { 738 + status = "disabled"; 739 + #phy-cells = <0>; 740 + }; 741 + 742 + pcie-4 { 743 + status = "disabled"; 744 + #phy-cells = <0>; 745 + }; 746 + 747 + pcie-5 { 748 + status = "disabled"; 749 + #phy-cells = <0>; 750 + }; 751 + 752 + pcie-6 { 753 + status = "disabled"; 754 + #phy-cells = <0>; 755 + }; 756 + }; 757 + }; 758 + 759 + sata { 760 + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 761 + clock-names = "pll"; 762 + resets = <&tegra_car 204>; 763 + reset-names = "phy"; 764 + status = "disabled"; 765 + 766 + lanes { 767 + sata-0 { 768 + status = "disabled"; 769 + #phy-cells = <0>; 770 + }; 771 + }; 772 + }; 773 + }; 774 + 775 + ports { 776 + usb2-0 { 777 + status = "disabled"; 778 + }; 779 + 780 + usb2-1 { 781 + status = "disabled"; 782 + }; 783 + 784 + usb2-2 { 785 + status = "disabled"; 786 + }; 787 + 788 + usb2-3 { 789 + status = "disabled"; 790 + }; 791 + 792 + hsic-0 { 793 + status = "disabled"; 794 + }; 795 + 796 + usb3-0 { 797 + status = "disabled"; 798 + }; 799 + 800 + usb3-1 { 801 + status = "disabled"; 802 + }; 803 + 804 + usb3-2 { 805 + status = "disabled"; 806 + }; 807 + 808 + usb3-3 { 809 + status = "disabled"; 810 + }; 811 + }; 710 812 }; 711 813 712 814 sdhci@700b0000 { ··· 949 671 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 950 672 clock-names = "mipi-cal"; 951 673 #nvidia,mipi-calibrate-cells = <1>; 674 + }; 675 + 676 + aconnect@702c0000 { 677 + compatible = "nvidia,tegra210-aconnect"; 678 + clocks = <&tegra_car TEGRA210_CLK_APE>, 679 + <&tegra_car TEGRA210_CLK_APB2APE>; 680 + clock-names = "ape", "apb2ape"; 681 + power-domains = <&pd_audio>; 682 + #address-cells = <1>; 683 + #size-cells = <1>; 684 + ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 685 + status = "disabled"; 952 686 }; 953 687 954 688 spi@70410000 {