Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck:
- add support for the watchdog on Meson8 and Meson8m2
- add support for MediaTek MT7623 and MT7622 SoC
- add support for the r8a77995 wdt
- explicitly request exclusive reset control for asm9260_wdt,
zx2967_wdt, rt2880_wdt and mt7621_wdt
- improvements to asm9260_wdt, aspeed_wdt, renesas_wdt and cadence_wdt
- add support for reading freq via CCF + suspend/resume support for
of_xilinx_wdt
- constify watchdog_ops and various device-id structures
- revert of commit 1fccb73011ea ("iTCO_wdt: all versions count down
twice") (Bug 196509)
* git://www.linux-watchdog.org/linux-watchdog: (40 commits)
watchdog: mei_wdt: constify mei_cl_device_id
watchdog: sp805: constify amba_id
watchdog: ziirave: constify i2c_device_id
watchdog: sc1200: constify pnp_device_id
dt-bindings: watchdog: renesas-wdt: Add support for the r8a77995 wdt
watchdog: renesas_wdt: update copyright dates
watchdog: renesas_wdt: make 'clk' a variable local to probe()
watchdog: renesas_wdt: consistently use RuntimePM for clock management
watchdog: aspeed: Support configuration of external signal properties
dt-bindings: watchdog: aspeed: External reset signal properties
drivers/watchdog: Add optional ASPEED device tree properties
drivers/watchdog: ASPEED reference dev tree properties for config
watchdog: da9063_wdt: Simplify by removing unneeded struct...
watchdog: bcm7038: Check the return value from clk_prepare_enable()
watchdog: qcom: Check for platform_get_resource() failure
watchdog: of_xilinx_wdt: Add suspend/resume support
watchdog: of_xilinx_wdt: Add support for reading freq via CCF
dt-bindings: watchdog: mediatek: add support for MediaTek MT7623 and MT7622 SoC
watchdog: max77620_wdt: constify platform_device_id
watchdog: pcwd_usb: constify usb_device_id
...
+40
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+40
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
···
8
- reg: physical base address of the controller and length of memory mapped
9
region
10
11
+
Optional properties:
12
+
13
+
- aspeed,reset-type = "cpu|soc|system|none"
14
+
15
+
Reset behavior - Whenever a timeout occurs the watchdog can be programmed
16
+
to generate one of three different, mutually exclusive, types of resets.
17
+
18
+
Type "none" can be specified to indicate that no resets are to be done.
19
+
This is useful in situations where another watchdog engine on chip is
20
+
to perform the reset.
21
+
22
+
If 'aspeed,reset-type=' is not specfied the default is to enable system
23
+
reset.
24
+
25
+
Reset types:
26
+
27
+
- cpu: Reset CPU on watchdog timeout
28
+
29
+
- soc: Reset 'System on Chip' on watchdog timeout
30
+
31
+
- system: Reset system on watchdog timeout
32
+
33
+
- none: No reset is performed on timeout. Assumes another watchdog
34
+
engine is responsible for this.
35
+
36
+
- aspeed,alt-boot: If property is present then boot from alternate block.
37
+
- aspeed,external-signal: If property is present then signal is sent to
38
+
external reset counter (only WDT1 and WDT2). If not
39
+
specified no external signal is sent.
40
+
- aspeed,ext-pulse-duration: External signal pulse duration in microseconds
41
+
42
+
Optional properties for AST2500-compatible watchdogs:
43
+
- aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's
44
+
drive type to push-pull. The default is open-drain.
45
+
- aspeed,ext-active-high: If aspeed,external-signal is present and and the pin
46
+
is configured as push-pull, then set the pulse
47
+
polarity to active-high. The default is active-low.
48
+
49
Example:
50
51
wdt1: watchdog@1e785000 {
52
compatible = "aspeed,ast2400-wdt";
53
reg = <0x1e785000 0x1c>;
54
+
aspeed,reset-type = "system";
55
+
aspeed,external-signal;
56
};
+5
-1
Documentation/devicetree/bindings/watchdog/meson-wdt.txt
+5
-1
Documentation/devicetree/bindings/watchdog/meson-wdt.txt
···
2
3
Required properties:
4
5
+
- compatible : depending on the SoC this should be one of:
6
+
"amlogic,meson6-wdt" on Meson6 SoCs
7
+
"amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs
8
+
"amlogic,meson8b-wdt" on Meson8b SoCs
9
+
"amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
10
- reg : Specifies base physical address and size of the registers.
11
12
Example:
+2
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+2
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
···
6
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
7
"mediatek,mt6589-wdt": for MT6589
8
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
9
+
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
10
+
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
11
12
- reg : Specifies base physical address and size of the registers.
13
+1
Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+1
Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+1
-1
Documentation/watchdog/watchdog-parameters.txt
+1
-1
Documentation/watchdog/watchdog-parameters.txt
···
117
-------------------------------------------------
118
iTCO_wdt:
119
heartbeat: Watchdog heartbeat in seconds.
120
-
(5<=heartbeat<=74 (TCO v1) or 1226 (TCO v2), default=30)
121
nowayout: Watchdog cannot be stopped once started
122
(default=kernel config parameter)
123
-------------------------------------------------
···
117
-------------------------------------------------
118
iTCO_wdt:
119
heartbeat: Watchdog heartbeat in seconds.
120
+
(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=30)
121
nowayout: Watchdog cannot be stopped once started
122
(default=kernel config parameter)
123
-------------------------------------------------
+2
-2
drivers/watchdog/asm9260_wdt.c
+2
-2
drivers/watchdog/asm9260_wdt.c
···
82
83
counter = ioread32(priv->iobase + HW_WDTV);
84
85
-
return DIV_ROUND_CLOSEST(counter, priv->wdt_freq);
86
}
87
88
static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd)
···
296
if (ret)
297
return ret;
298
299
-
priv->rst = devm_reset_control_get(&pdev->dev, "wdt_rst");
300
if (IS_ERR(priv->rst))
301
return PTR_ERR(priv->rst);
302
···
82
83
counter = ioread32(priv->iobase + HW_WDTV);
84
85
+
return counter / priv->wdt_freq;
86
}
87
88
static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd)
···
296
if (ret)
297
return ret;
298
299
+
priv->rst = devm_reset_control_get_exclusive(&pdev->dev, "wdt_rst");
300
if (IS_ERR(priv->rst))
301
return PTR_ERR(priv->rst);
302
+125
-7
drivers/watchdog/aspeed_wdt.c
+125
-7
drivers/watchdog/aspeed_wdt.c
···
23
u32 ctrl;
24
};
25
26
static const struct of_device_id aspeed_wdt_of_table[] = {
27
-
{ .compatible = "aspeed,ast2400-wdt" },
28
-
{ .compatible = "aspeed,ast2500-wdt" },
29
{ },
30
};
31
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
···
48
#define WDT_CTRL 0x0C
49
#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
50
#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
51
#define WDT_CTRL_1MHZ_CLK BIT(4)
52
#define WDT_CTRL_WDT_EXT BIT(3)
53
#define WDT_CTRL_WDT_INTR BIT(2)
54
#define WDT_CTRL_RESET_SYSTEM BIT(1)
55
#define WDT_CTRL_ENABLE BIT(0)
56
57
#define WDT_RESTART_MAGIC 0x4755
58
···
183
184
static int aspeed_wdt_probe(struct platform_device *pdev)
185
{
186
struct aspeed_wdt *wdt;
187
struct resource *res;
188
int ret;
189
190
wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
···
214
wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
215
watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
216
217
/*
218
* Control reset on a per-device basis to ensure the
219
-
* host is not affected by a BMC reboot, so only reset
220
-
* the SOC and not the full chip
221
*/
222
-
wdt->ctrl = WDT_CTRL_RESET_MODE_SOC |
223
-
WDT_CTRL_1MHZ_CLK |
224
-
WDT_CTRL_RESET_SYSTEM;
225
226
if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
227
aspeed_wdt_start(&wdt->wdd);
228
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
229
}
230
231
ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
···
23
u32 ctrl;
24
};
25
26
+
struct aspeed_wdt_config {
27
+
u32 ext_pulse_width_mask;
28
+
};
29
+
30
+
static const struct aspeed_wdt_config ast2400_config = {
31
+
.ext_pulse_width_mask = 0xff,
32
+
};
33
+
34
+
static const struct aspeed_wdt_config ast2500_config = {
35
+
.ext_pulse_width_mask = 0xfffff,
36
+
};
37
+
38
static const struct of_device_id aspeed_wdt_of_table[] = {
39
+
{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
40
+
{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
41
{ },
42
};
43
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
···
36
#define WDT_CTRL 0x0C
37
#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
38
#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
39
+
#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
40
#define WDT_CTRL_1MHZ_CLK BIT(4)
41
#define WDT_CTRL_WDT_EXT BIT(3)
42
#define WDT_CTRL_WDT_INTR BIT(2)
43
#define WDT_CTRL_RESET_SYSTEM BIT(1)
44
#define WDT_CTRL_ENABLE BIT(0)
45
+
46
+
/*
47
+
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
48
+
* enabled), specifically:
49
+
*
50
+
* * Pulse duration
51
+
* * Drive mode: push-pull vs open-drain
52
+
* * Polarity: Active high or active low
53
+
*
54
+
* Pulse duration configuration is available on both the AST2400 and AST2500,
55
+
* though the field changes between SoCs:
56
+
*
57
+
* AST2400: Bits 7:0
58
+
* AST2500: Bits 19:0
59
+
*
60
+
* This difference is captured in struct aspeed_wdt_config.
61
+
*
62
+
* The AST2500 exposes the drive mode and polarity options, but not in a
63
+
* regular fashion. For read purposes, bit 31 represents active high or low,
64
+
* and bit 30 represents push-pull or open-drain. With respect to write, magic
65
+
* values need to be written to the top byte to change the state of the drive
66
+
* mode and polarity bits. Any other value written to the top byte has no
67
+
* effect on the state of the drive mode or polarity bits. However, the pulse
68
+
* width value must be preserved (as desired) if written.
69
+
*/
70
+
#define WDT_RESET_WIDTH 0x18
71
+
#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
72
+
#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
73
+
#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
74
+
#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
75
+
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
76
+
#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
77
78
#define WDT_RESTART_MAGIC 0x4755
79
···
138
139
static int aspeed_wdt_probe(struct platform_device *pdev)
140
{
141
+
const struct aspeed_wdt_config *config;
142
+
const struct of_device_id *ofdid;
143
struct aspeed_wdt *wdt;
144
struct resource *res;
145
+
struct device_node *np;
146
+
const char *reset_type;
147
+
u32 duration;
148
int ret;
149
150
wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
···
164
wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
165
watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
166
167
+
np = pdev->dev.of_node;
168
+
169
+
ofdid = of_match_node(aspeed_wdt_of_table, np);
170
+
if (!ofdid)
171
+
return -EINVAL;
172
+
config = ofdid->data;
173
+
174
+
wdt->ctrl = WDT_CTRL_1MHZ_CLK;
175
+
176
/*
177
* Control reset on a per-device basis to ensure the
178
+
* host is not affected by a BMC reboot
179
*/
180
+
ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
181
+
if (ret) {
182
+
wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
183
+
} else {
184
+
if (!strcmp(reset_type, "cpu"))
185
+
wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;
186
+
else if (!strcmp(reset_type, "soc"))
187
+
wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
188
+
else if (!strcmp(reset_type, "system"))
189
+
wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
190
+
else if (strcmp(reset_type, "none"))
191
+
return -EINVAL;
192
+
}
193
+
if (of_property_read_bool(np, "aspeed,external-signal"))
194
+
wdt->ctrl |= WDT_CTRL_WDT_EXT;
195
+
196
+
writel(wdt->ctrl, wdt->base + WDT_CTRL);
197
198
if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
199
aspeed_wdt_start(&wdt->wdd);
200
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
201
+
}
202
+
203
+
if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
204
+
u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
205
+
206
+
reg &= config->ext_pulse_width_mask;
207
+
if (of_property_read_bool(np, "aspeed,ext-push-pull"))
208
+
reg |= WDT_PUSH_PULL_MAGIC;
209
+
else
210
+
reg |= WDT_OPEN_DRAIN_MAGIC;
211
+
212
+
writel(reg, wdt->base + WDT_RESET_WIDTH);
213
+
214
+
reg &= config->ext_pulse_width_mask;
215
+
if (of_property_read_bool(np, "aspeed,ext-active-high"))
216
+
reg |= WDT_ACTIVE_HIGH_MAGIC;
217
+
else
218
+
reg |= WDT_ACTIVE_LOW_MAGIC;
219
+
220
+
writel(reg, wdt->base + WDT_RESET_WIDTH);
221
+
}
222
+
223
+
if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
224
+
u32 max_duration = config->ext_pulse_width_mask + 1;
225
+
226
+
if (duration == 0 || duration > max_duration) {
227
+
dev_err(&pdev->dev, "Invalid pulse duration: %uus\n",
228
+
duration);
229
+
duration = max(1U, min(max_duration, duration));
230
+
dev_info(&pdev->dev, "Pulse duration set to %uus\n",
231
+
duration);
232
+
}
233
+
234
+
/*
235
+
* The watchdog is always configured with a 1MHz source, so
236
+
* there is no need to scale the microsecond value. However we
237
+
* need to offset it - from the datasheet:
238
+
*
239
+
* "This register decides the asserting duration of wdt_ext and
240
+
* wdt_rstarm signal. The default value is 0xFF. It means the
241
+
* default asserting duration of wdt_ext and wdt_rstarm is
242
+
* 256us."
243
+
*
244
+
* This implies a value of 0 gives a 1us pulse.
245
+
*/
246
+
writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
247
}
248
249
ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
+3
-1
drivers/watchdog/bcm7038_wdt.c
+3
-1
drivers/watchdog/bcm7038_wdt.c
···
136
wdt->clk = devm_clk_get(dev, NULL);
137
/* If unable to get clock, use default frequency */
138
if (!IS_ERR(wdt->clk)) {
139
+
err = clk_prepare_enable(wdt->clk);
140
+
if (err)
141
+
return err;
142
wdt->rate = clk_get_rate(wdt->clk);
143
/* Prevent divide-by-zero exception */
144
if (!wdt->rate)
+3
-3
drivers/watchdog/cadence_wdt.c
+3
-3
drivers/watchdog/cadence_wdt.c
···
52
static int wdt_timeout;
53
static int nowayout = WATCHDOG_NOWAYOUT;
54
55
-
module_param(wdt_timeout, int, 0);
56
MODULE_PARM_DESC(wdt_timeout,
57
"Watchdog time in seconds. (default="
58
__MODULE_STRING(CDNS_WDT_DEFAULT_TIMEOUT) ")");
59
60
-
module_param(nowayout, int, 0);
61
MODULE_PARM_DESC(nowayout,
62
"Watchdog cannot be stopped once started (default="
63
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
···
368
}
369
platform_set_drvdata(pdev, wdt);
370
371
-
dev_dbg(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds%s\n",
372
wdt->regs, cdns_wdt_device->timeout,
373
nowayout ? ", nowayout" : "");
374
···
52
static int wdt_timeout;
53
static int nowayout = WATCHDOG_NOWAYOUT;
54
55
+
module_param(wdt_timeout, int, 0644);
56
MODULE_PARM_DESC(wdt_timeout,
57
"Watchdog time in seconds. (default="
58
__MODULE_STRING(CDNS_WDT_DEFAULT_TIMEOUT) ")");
59
60
+
module_param(nowayout, int, 0644);
61
MODULE_PARM_DESC(nowayout,
62
"Watchdog cannot be stopped once started (default="
63
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
···
368
}
369
platform_set_drvdata(pdev, wdt);
370
371
+
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds%s\n",
372
wdt->regs, cdns_wdt_device->timeout,
373
nowayout ? ", nowayout" : "");
374
+1
-1
drivers/watchdog/coh901327_wdt.c
+1
-1
drivers/watchdog/coh901327_wdt.c
+30
-37
drivers/watchdog/da9063_wdt.c
+30
-37
drivers/watchdog/da9063_wdt.c
···
36
#define DA9063_WDG_TIMEOUT wdt_timeout[3]
37
#define DA9063_RESET_PROTECTION_MS 256
38
39
-
struct da9063_watchdog {
40
-
struct da9063 *da9063;
41
-
struct watchdog_device wdtdev;
42
-
};
43
-
44
static unsigned int da9063_wdt_timeout_to_sel(unsigned int secs)
45
{
46
unsigned int i;
···
56
57
static int da9063_wdt_start(struct watchdog_device *wdd)
58
{
59
-
struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd);
60
unsigned int selector;
61
int ret;
62
63
-
selector = da9063_wdt_timeout_to_sel(wdt->wdtdev.timeout);
64
-
ret = _da9063_wdt_set_timeout(wdt->da9063, selector);
65
if (ret)
66
-
dev_err(wdt->da9063->dev, "Watchdog failed to start (err = %d)\n",
67
ret);
68
69
return ret;
···
71
72
static int da9063_wdt_stop(struct watchdog_device *wdd)
73
{
74
-
struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd);
75
int ret;
76
77
-
ret = regmap_update_bits(wdt->da9063->regmap, DA9063_REG_CONTROL_D,
78
DA9063_TWDSCALE_MASK, DA9063_TWDSCALE_DISABLE);
79
if (ret)
80
-
dev_alert(wdt->da9063->dev, "Watchdog failed to stop (err = %d)\n",
81
ret);
82
83
return ret;
···
85
86
static int da9063_wdt_ping(struct watchdog_device *wdd)
87
{
88
-
struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd);
89
int ret;
90
91
-
ret = regmap_write(wdt->da9063->regmap, DA9063_REG_CONTROL_F,
92
DA9063_WATCHDOG);
93
if (ret)
94
-
dev_alert(wdt->da9063->dev, "Failed to ping the watchdog (err = %d)\n",
95
ret);
96
97
return ret;
···
100
static int da9063_wdt_set_timeout(struct watchdog_device *wdd,
101
unsigned int timeout)
102
{
103
-
struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd);
104
unsigned int selector;
105
int ret;
106
107
selector = da9063_wdt_timeout_to_sel(timeout);
108
-
ret = _da9063_wdt_set_timeout(wdt->da9063, selector);
109
if (ret)
110
-
dev_err(wdt->da9063->dev, "Failed to set watchdog timeout (err = %d)\n",
111
ret);
112
else
113
wdd->timeout = wdt_timeout[selector];
···
118
static int da9063_wdt_restart(struct watchdog_device *wdd, unsigned long action,
119
void *data)
120
{
121
-
struct da9063_watchdog *wdt = watchdog_get_drvdata(wdd);
122
int ret;
123
124
-
ret = regmap_write(wdt->da9063->regmap, DA9063_REG_CONTROL_F,
125
DA9063_SHUTDOWN);
126
if (ret)
127
-
dev_alert(wdt->da9063->dev, "Failed to shutdown (err = %d)\n",
128
ret);
129
130
return ret;
···
147
static int da9063_wdt_probe(struct platform_device *pdev)
148
{
149
struct da9063 *da9063;
150
-
struct da9063_watchdog *wdt;
151
152
if (!pdev->dev.parent)
153
return -EINVAL;
···
156
if (!da9063)
157
return -EINVAL;
158
159
-
wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
160
-
if (!wdt)
161
return -ENOMEM;
162
163
-
wdt->da9063 = da9063;
164
165
-
wdt->wdtdev.info = &da9063_watchdog_info;
166
-
wdt->wdtdev.ops = &da9063_watchdog_ops;
167
-
wdt->wdtdev.min_timeout = DA9063_WDT_MIN_TIMEOUT;
168
-
wdt->wdtdev.max_timeout = DA9063_WDT_MAX_TIMEOUT;
169
-
wdt->wdtdev.min_hw_heartbeat_ms = DA9063_RESET_PROTECTION_MS;
170
-
wdt->wdtdev.timeout = DA9063_WDG_TIMEOUT;
171
-
wdt->wdtdev.parent = &pdev->dev;
172
173
-
wdt->wdtdev.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
174
175
-
watchdog_set_restart_priority(&wdt->wdtdev, 128);
176
177
-
watchdog_set_drvdata(&wdt->wdtdev, wdt);
178
-
179
-
return devm_watchdog_register_device(&pdev->dev, &wdt->wdtdev);
180
}
181
182
static struct platform_driver da9063_wdt_driver = {
···
36
#define DA9063_WDG_TIMEOUT wdt_timeout[3]
37
#define DA9063_RESET_PROTECTION_MS 256
38
39
static unsigned int da9063_wdt_timeout_to_sel(unsigned int secs)
40
{
41
unsigned int i;
···
61
62
static int da9063_wdt_start(struct watchdog_device *wdd)
63
{
64
+
struct da9063 *da9063 = watchdog_get_drvdata(wdd);
65
unsigned int selector;
66
int ret;
67
68
+
selector = da9063_wdt_timeout_to_sel(wdd->timeout);
69
+
ret = _da9063_wdt_set_timeout(da9063, selector);
70
if (ret)
71
+
dev_err(da9063->dev, "Watchdog failed to start (err = %d)\n",
72
ret);
73
74
return ret;
···
76
77
static int da9063_wdt_stop(struct watchdog_device *wdd)
78
{
79
+
struct da9063 *da9063 = watchdog_get_drvdata(wdd);
80
int ret;
81
82
+
ret = regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_D,
83
DA9063_TWDSCALE_MASK, DA9063_TWDSCALE_DISABLE);
84
if (ret)
85
+
dev_alert(da9063->dev, "Watchdog failed to stop (err = %d)\n",
86
ret);
87
88
return ret;
···
90
91
static int da9063_wdt_ping(struct watchdog_device *wdd)
92
{
93
+
struct da9063 *da9063 = watchdog_get_drvdata(wdd);
94
int ret;
95
96
+
ret = regmap_write(da9063->regmap, DA9063_REG_CONTROL_F,
97
DA9063_WATCHDOG);
98
if (ret)
99
+
dev_alert(da9063->dev, "Failed to ping the watchdog (err = %d)\n",
100
ret);
101
102
return ret;
···
105
static int da9063_wdt_set_timeout(struct watchdog_device *wdd,
106
unsigned int timeout)
107
{
108
+
struct da9063 *da9063 = watchdog_get_drvdata(wdd);
109
unsigned int selector;
110
int ret;
111
112
selector = da9063_wdt_timeout_to_sel(timeout);
113
+
ret = _da9063_wdt_set_timeout(da9063, selector);
114
if (ret)
115
+
dev_err(da9063->dev, "Failed to set watchdog timeout (err = %d)\n",
116
ret);
117
else
118
wdd->timeout = wdt_timeout[selector];
···
123
static int da9063_wdt_restart(struct watchdog_device *wdd, unsigned long action,
124
void *data)
125
{
126
+
struct da9063 *da9063 = watchdog_get_drvdata(wdd);
127
int ret;
128
129
+
ret = regmap_write(da9063->regmap, DA9063_REG_CONTROL_F,
130
DA9063_SHUTDOWN);
131
if (ret)
132
+
dev_alert(da9063->dev, "Failed to shutdown (err = %d)\n",
133
ret);
134
135
return ret;
···
152
static int da9063_wdt_probe(struct platform_device *pdev)
153
{
154
struct da9063 *da9063;
155
+
struct watchdog_device *wdd;
156
157
if (!pdev->dev.parent)
158
return -EINVAL;
···
161
if (!da9063)
162
return -EINVAL;
163
164
+
wdd = devm_kzalloc(&pdev->dev, sizeof(*wdd), GFP_KERNEL);
165
+
if (!wdd)
166
return -ENOMEM;
167
168
+
wdd->info = &da9063_watchdog_info;
169
+
wdd->ops = &da9063_watchdog_ops;
170
+
wdd->min_timeout = DA9063_WDT_MIN_TIMEOUT;
171
+
wdd->max_timeout = DA9063_WDT_MAX_TIMEOUT;
172
+
wdd->min_hw_heartbeat_ms = DA9063_RESET_PROTECTION_MS;
173
+
wdd->timeout = DA9063_WDG_TIMEOUT;
174
+
wdd->parent = &pdev->dev;
175
176
+
wdd->status = WATCHDOG_NOWAYOUT_INIT_STATUS;
177
178
+
watchdog_set_restart_priority(wdd, 128);
179
180
+
watchdog_set_drvdata(wdd, da9063);
181
182
+
return devm_watchdog_register_device(&pdev->dev, wdd);
183
}
184
185
static struct platform_driver da9063_wdt_driver = {
+1
-1
drivers/watchdog/diag288_wdt.c
+1
-1
drivers/watchdog/diag288_wdt.c
+12
-10
drivers/watchdog/iTCO_wdt.c
+12
-10
drivers/watchdog/iTCO_wdt.c
···
306
307
iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
308
309
-
/* Reset the timeout status bit so that the timer
310
-
* needs to count down twice again before rebooting */
311
-
outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
312
-
313
/* Reload the timer by writing to the TCO Timer Counter register */
314
-
if (p->iTCO_version >= 2)
315
outw(0x01, TCO_RLD(p));
316
-
else if (p->iTCO_version == 1)
317
outb(0x01, TCO_RLD(p));
318
319
spin_unlock(&p->io_lock);
320
return 0;
···
328
unsigned char val8;
329
unsigned int tmrval;
330
331
-
/* The timer counts down twice before rebooting */
332
-
tmrval = seconds_to_ticks(p, t) / 2;
333
334
/* from the specs: */
335
/* "Values of 0h-3h are ignored and should not be attempted" */
···
385
spin_lock(&p->io_lock);
386
val16 = inw(TCO_RLD(p));
387
val16 &= 0x3ff;
388
-
if (!(inw(TCO1_STS(p)) & 0x0008))
389
-
val16 += (inw(TCOv2_TMR(p)) & 0x3ff);
390
spin_unlock(&p->io_lock);
391
392
time_left = ticks_to_seconds(p, val16);
···
306
307
iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
308
309
/* Reload the timer by writing to the TCO Timer Counter register */
310
+
if (p->iTCO_version >= 2) {
311
outw(0x01, TCO_RLD(p));
312
+
} else if (p->iTCO_version == 1) {
313
+
/* Reset the timeout status bit so that the timer
314
+
* needs to count down twice again before rebooting */
315
+
outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
316
+
317
outb(0x01, TCO_RLD(p));
318
+
}
319
320
spin_unlock(&p->io_lock);
321
return 0;
···
327
unsigned char val8;
328
unsigned int tmrval;
329
330
+
tmrval = seconds_to_ticks(p, t);
331
+
332
+
/* For TCO v1 the timer counts down twice before rebooting */
333
+
if (p->iTCO_version == 1)
334
+
tmrval /= 2;
335
336
/* from the specs: */
337
/* "Values of 0h-3h are ignored and should not be attempted" */
···
381
spin_lock(&p->io_lock);
382
val16 = inw(TCO_RLD(p));
383
val16 &= 0x3ff;
384
spin_unlock(&p->io_lock);
385
386
time_left = ticks_to_seconds(p, val16);
+1
-1
drivers/watchdog/it87_wdt.c
+1
-1
drivers/watchdog/it87_wdt.c
+1
-1
drivers/watchdog/max77620_wdt.c
+1
-1
drivers/watchdog/max77620_wdt.c
+1
-1
drivers/watchdog/mei_wdt.c
+1
-1
drivers/watchdog/mei_wdt.c
+2
drivers/watchdog/meson_wdt.c
+2
drivers/watchdog/meson_wdt.c
···
155
156
static const struct of_device_id meson_wdt_dt_ids[] = {
157
{ .compatible = "amlogic,meson6-wdt", .data = &meson6_wdt_data },
158
+
{ .compatible = "amlogic,meson8-wdt", .data = &meson6_wdt_data },
159
{ .compatible = "amlogic,meson8b-wdt", .data = &meson8b_wdt_data },
160
+
{ .compatible = "amlogic,meson8m2-wdt", .data = &meson8b_wdt_data },
161
{ /* sentinel */ }
162
};
163
MODULE_DEVICE_TABLE(of, meson_wdt_dt_ids);
+2
-2
drivers/watchdog/mt7621_wdt.c
+2
-2
drivers/watchdog/mt7621_wdt.c
···
105
return 0;
106
}
107
108
-
static struct watchdog_info mt7621_wdt_info = {
109
.identity = "Mediatek Watchdog",
110
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
111
};
···
135
if (IS_ERR(mt7621_wdt_base))
136
return PTR_ERR(mt7621_wdt_base);
137
138
-
mt7621_wdt_reset = devm_reset_control_get(&pdev->dev, NULL);
139
if (!IS_ERR(mt7621_wdt_reset))
140
reset_control_deassert(mt7621_wdt_reset);
141
···
105
return 0;
106
}
107
108
+
static const struct watchdog_info mt7621_wdt_info = {
109
.identity = "Mediatek Watchdog",
110
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
111
};
···
135
if (IS_ERR(mt7621_wdt_base))
136
return PTR_ERR(mt7621_wdt_base);
137
138
+
mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
139
if (!IS_ERR(mt7621_wdt_reset))
140
reset_control_deassert(mt7621_wdt_reset);
141
+70
-13
drivers/watchdog/of_xilinx_wdt.c
+70
-13
drivers/watchdog/of_xilinx_wdt.c
···
51
52
static int xilinx_wdt_start(struct watchdog_device *wdd)
53
{
54
u32 control_status_reg;
55
struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
56
57
spin_lock(&xdev->spinlock);
58
···
92
iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
93
94
spin_unlock(&xdev->spinlock);
95
pr_info("Stopped!\n");
96
97
return 0;
···
177
if (IS_ERR(xdev->base))
178
return PTR_ERR(xdev->base);
179
180
-
rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
181
-
if (rc)
182
-
dev_warn(&pdev->dev,
183
-
"The watchdog clock frequency cannot be obtained\n");
184
-
185
rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
186
&xdev->wdt_interval);
187
if (rc)
···
191
192
watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
193
194
/*
195
* Twice of the 2^wdt_interval / freq because the first wdt overflow is
196
* ignored (interrupt), reset is only generated at second wdt overflow
···
221
222
spin_lock_init(&xdev->spinlock);
223
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
224
-
225
-
xdev->clk = devm_clk_get(&pdev->dev, NULL);
226
-
if (IS_ERR(xdev->clk)) {
227
-
if (PTR_ERR(xdev->clk) == -ENOENT)
228
-
xdev->clk = NULL;
229
-
else
230
-
return PTR_ERR(xdev->clk);
231
-
}
232
233
rc = clk_prepare_enable(xdev->clk);
234
if (rc) {
···
239
dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
240
goto err_clk_disable;
241
}
242
243
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
244
xdev->base, xilinx_wdt_wdd->timeout);
···
264
return 0;
265
}
266
267
/* Match table for of_platform binding */
268
static const struct of_device_id xwdt_of_match[] = {
269
{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
···
315
.driver = {
316
.name = WATCHDOG_NAME,
317
.of_match_table = xwdt_of_match,
318
},
319
};
320
···
51
52
static int xilinx_wdt_start(struct watchdog_device *wdd)
53
{
54
+
int ret;
55
u32 control_status_reg;
56
struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
57
+
58
+
ret = clk_enable(xdev->clk);
59
+
if (ret) {
60
+
dev_err(wdd->parent, "Failed to enable clock\n");
61
+
return ret;
62
+
}
63
64
spin_lock(&xdev->spinlock);
65
···
85
iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
86
87
spin_unlock(&xdev->spinlock);
88
+
89
+
clk_disable(xdev->clk);
90
+
91
pr_info("Stopped!\n");
92
93
return 0;
···
167
if (IS_ERR(xdev->base))
168
return PTR_ERR(xdev->base);
169
170
rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
171
&xdev->wdt_interval);
172
if (rc)
···
186
187
watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
188
189
+
xdev->clk = devm_clk_get(&pdev->dev, NULL);
190
+
if (IS_ERR(xdev->clk)) {
191
+
if (PTR_ERR(xdev->clk) != -ENOENT)
192
+
return PTR_ERR(xdev->clk);
193
+
194
+
/*
195
+
* Clock framework support is optional, continue on
196
+
* anyways if we don't find a matching clock.
197
+
*/
198
+
xdev->clk = NULL;
199
+
200
+
rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
201
+
&pfreq);
202
+
if (rc)
203
+
dev_warn(&pdev->dev,
204
+
"The watchdog clock freq cannot be obtained\n");
205
+
} else {
206
+
pfreq = clk_get_rate(xdev->clk);
207
+
}
208
+
209
/*
210
* Twice of the 2^wdt_interval / freq because the first wdt overflow is
211
* ignored (interrupt), reset is only generated at second wdt overflow
···
196
197
spin_lock_init(&xdev->spinlock);
198
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
199
200
rc = clk_prepare_enable(xdev->clk);
201
if (rc) {
···
222
dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
223
goto err_clk_disable;
224
}
225
+
226
+
clk_disable(xdev->clk);
227
228
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
229
xdev->base, xilinx_wdt_wdd->timeout);
···
245
return 0;
246
}
247
248
+
/**
249
+
* xwdt_suspend - Suspend the device.
250
+
*
251
+
* @dev: handle to the device structure.
252
+
* Return: 0 always.
253
+
*/
254
+
static int __maybe_unused xwdt_suspend(struct device *dev)
255
+
{
256
+
struct platform_device *pdev = to_platform_device(dev);
257
+
struct xwdt_device *xdev = platform_get_drvdata(pdev);
258
+
259
+
if (watchdog_active(&xdev->xilinx_wdt_wdd))
260
+
xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
261
+
262
+
return 0;
263
+
}
264
+
265
+
/**
266
+
* xwdt_resume - Resume the device.
267
+
*
268
+
* @dev: handle to the device structure.
269
+
* Return: 0 on success, errno otherwise.
270
+
*/
271
+
static int __maybe_unused xwdt_resume(struct device *dev)
272
+
{
273
+
struct platform_device *pdev = to_platform_device(dev);
274
+
struct xwdt_device *xdev = platform_get_drvdata(pdev);
275
+
int ret = 0;
276
+
277
+
if (watchdog_active(&xdev->xilinx_wdt_wdd))
278
+
ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
279
+
280
+
return ret;
281
+
}
282
+
283
+
static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
284
+
285
/* Match table for of_platform binding */
286
static const struct of_device_id xwdt_of_match[] = {
287
{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
···
259
.driver = {
260
.name = WATCHDOG_NAME,
261
.of_match_table = xwdt_of_match,
262
+
.pm = &xwdt_pm_ops,
263
},
264
};
265
+1
-1
drivers/watchdog/pcwd_usb.c
+1
-1
drivers/watchdog/pcwd_usb.c
+2
drivers/watchdog/qcom-wdt.c
+2
drivers/watchdog/qcom-wdt.c
+48
-32
drivers/watchdog/renesas_wdt.c
+48
-32
drivers/watchdog/renesas_wdt.c
···
1
/*
2
* Watchdog driver for Renesas WDT watchdog
3
*
4
-
* Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
5
-
* Copyright (C) 2015-16 Renesas Electronics Corporation
6
*
7
* This program is free software; you can redistribute it and/or modify it
8
* under the terms of the GNU General Public License version 2 as published by
···
23
#define RWTCSRA_WOVF BIT(4)
24
#define RWTCSRA_WRFLG BIT(5)
25
#define RWTCSRA_TME BIT(7)
26
27
#define RWDT_DEFAULT_TIMEOUT 60U
28
29
-
static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024 };
30
31
static bool nowayout = WATCHDOG_NOWAYOUT;
32
module_param(nowayout, bool, 0);
···
48
struct rwdt_priv {
49
void __iomem *base;
50
struct watchdog_device wdev;
51
-
struct clk *clk;
52
-
unsigned int clks_per_sec;
53
u8 cks;
54
};
55
···
66
{
67
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
68
69
-
rwdt_write(priv, 65536 - wdev->timeout * priv->clks_per_sec, RWTCNT);
70
71
return 0;
72
}
···
75
{
76
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
77
78
-
clk_prepare_enable(priv->clk);
79
80
rwdt_write(priv, priv->cks, RWTCSRA);
81
rwdt_init_timeout(wdev);
82
···
94
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
95
96
rwdt_write(priv, priv->cks, RWTCSRA);
97
-
clk_disable_unprepare(priv->clk);
98
99
return 0;
100
}
···
104
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
105
u16 val = readw_relaxed(priv->base + RWTCNT);
106
107
-
return DIV_ROUND_CLOSEST(65536 - val, priv->clks_per_sec);
108
}
109
110
static const struct watchdog_info rwdt_ident = {
···
124
{
125
struct rwdt_priv *priv;
126
struct resource *res;
127
-
unsigned long rate;
128
-
unsigned int clks_per_sec;
129
int ret, i;
130
131
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
···
137
if (IS_ERR(priv->base))
138
return PTR_ERR(priv->base);
139
140
-
priv->clk = devm_clk_get(&pdev->dev, NULL);
141
-
if (IS_ERR(priv->clk))
142
-
return PTR_ERR(priv->clk);
143
144
-
rate = clk_get_rate(priv->clk);
145
-
if (!rate)
146
-
return -ENOENT;
147
148
for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
149
-
clks_per_sec = DIV_ROUND_UP(rate, clk_divs[i]);
150
-
if (clks_per_sec) {
151
-
priv->clks_per_sec = clks_per_sec;
152
priv->cks = i;
153
break;
154
}
155
}
156
157
-
if (!clks_per_sec) {
158
dev_err(&pdev->dev, "Can't find suitable clock divider\n");
159
-
return -ERANGE;
160
}
161
-
162
-
pm_runtime_enable(&pdev->dev);
163
-
pm_runtime_get_sync(&pdev->dev);
164
165
priv->wdev.info = &rwdt_ident,
166
priv->wdev.ops = &rwdt_ops,
167
priv->wdev.parent = &pdev->dev;
168
priv->wdev.min_timeout = 1;
169
-
priv->wdev.max_timeout = 65536 / clks_per_sec;
170
priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
171
172
platform_set_drvdata(pdev, priv);
···
183
dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
184
185
ret = watchdog_register_device(&priv->wdev);
186
-
if (ret < 0) {
187
-
pm_runtime_put(&pdev->dev);
188
-
pm_runtime_disable(&pdev->dev);
189
-
return ret;
190
-
}
191
192
return 0;
193
}
194
195
static int rwdt_remove(struct platform_device *pdev)
···
198
struct rwdt_priv *priv = platform_get_drvdata(pdev);
199
200
watchdog_unregister_device(&priv->wdev);
201
-
pm_runtime_put(&pdev->dev);
202
pm_runtime_disable(&pdev->dev);
203
204
return 0;
···
1
/*
2
* Watchdog driver for Renesas WDT watchdog
3
*
4
+
* Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
5
+
* Copyright (C) 2015-17 Renesas Electronics Corporation
6
*
7
* This program is free software; you can redistribute it and/or modify it
8
* under the terms of the GNU General Public License version 2 as published by
···
23
#define RWTCSRA_WOVF BIT(4)
24
#define RWTCSRA_WRFLG BIT(5)
25
#define RWTCSRA_TME BIT(7)
26
+
#define RWTCSRB 8
27
28
#define RWDT_DEFAULT_TIMEOUT 60U
29
30
+
/*
31
+
* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
32
+
* divider (12 bits). d is only a factor to fully utilize the WDT counter and
33
+
* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
34
+
*/
35
+
#define MUL_BY_CLKS_PER_SEC(p, d) \
36
+
DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
37
+
38
+
/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
39
+
#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
40
+
41
+
static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
42
43
static bool nowayout = WATCHDOG_NOWAYOUT;
44
module_param(nowayout, bool, 0);
···
36
struct rwdt_priv {
37
void __iomem *base;
38
struct watchdog_device wdev;
39
+
unsigned long clk_rate;
40
u8 cks;
41
};
42
···
55
{
56
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
57
58
+
rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
59
60
return 0;
61
}
···
64
{
65
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
66
67
+
pm_runtime_get_sync(wdev->parent);
68
69
+
rwdt_write(priv, 0, RWTCSRB);
70
rwdt_write(priv, priv->cks, RWTCSRA);
71
rwdt_init_timeout(wdev);
72
···
82
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
83
84
rwdt_write(priv, priv->cks, RWTCSRA);
85
+
pm_runtime_put(wdev->parent);
86
87
return 0;
88
}
···
92
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
93
u16 val = readw_relaxed(priv->base + RWTCNT);
94
95
+
return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
96
}
97
98
static const struct watchdog_info rwdt_ident = {
···
112
{
113
struct rwdt_priv *priv;
114
struct resource *res;
115
+
struct clk *clk;
116
+
unsigned long clks_per_sec;
117
int ret, i;
118
119
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
···
125
if (IS_ERR(priv->base))
126
return PTR_ERR(priv->base);
127
128
+
clk = devm_clk_get(&pdev->dev, NULL);
129
+
if (IS_ERR(clk))
130
+
return PTR_ERR(clk);
131
132
+
pm_runtime_enable(&pdev->dev);
133
+
134
+
pm_runtime_get_sync(&pdev->dev);
135
+
priv->clk_rate = clk_get_rate(clk);
136
+
pm_runtime_put(&pdev->dev);
137
+
138
+
if (!priv->clk_rate) {
139
+
ret = -ENOENT;
140
+
goto out_pm_disable;
141
+
}
142
143
for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
144
+
clks_per_sec = priv->clk_rate / clk_divs[i];
145
+
if (clks_per_sec && clks_per_sec < 65536) {
146
priv->cks = i;
147
break;
148
}
149
}
150
151
+
if (i < 0) {
152
dev_err(&pdev->dev, "Can't find suitable clock divider\n");
153
+
ret = -ERANGE;
154
+
goto out_pm_disable;
155
}
156
157
priv->wdev.info = &rwdt_ident,
158
priv->wdev.ops = &rwdt_ops,
159
priv->wdev.parent = &pdev->dev;
160
priv->wdev.min_timeout = 1;
161
+
priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
162
priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
163
164
platform_set_drvdata(pdev, priv);
···
167
dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
168
169
ret = watchdog_register_device(&priv->wdev);
170
+
if (ret < 0)
171
+
goto out_pm_disable;
172
173
return 0;
174
+
175
+
out_pm_disable:
176
+
pm_runtime_disable(&pdev->dev);
177
+
return ret;
178
}
179
180
static int rwdt_remove(struct platform_device *pdev)
···
181
struct rwdt_priv *priv = platform_get_drvdata(pdev);
182
183
watchdog_unregister_device(&priv->wdev);
184
pm_runtime_disable(&pdev->dev);
185
186
return 0;
+2
-2
drivers/watchdog/rt2880_wdt.c
+2
-2
drivers/watchdog/rt2880_wdt.c
···
119
return 0;
120
}
121
122
-
static struct watchdog_info rt288x_wdt_info = {
123
.identity = "Ralink Watchdog",
124
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
125
};
···
152
if (IS_ERR(rt288x_wdt_clk))
153
return PTR_ERR(rt288x_wdt_clk);
154
155
-
rt288x_wdt_reset = devm_reset_control_get(&pdev->dev, NULL);
156
if (!IS_ERR(rt288x_wdt_reset))
157
reset_control_deassert(rt288x_wdt_reset);
158
···
119
return 0;
120
}
121
122
+
static const struct watchdog_info rt288x_wdt_info = {
123
.identity = "Ralink Watchdog",
124
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
125
};
···
152
if (IS_ERR(rt288x_wdt_clk))
153
return PTR_ERR(rt288x_wdt_clk);
154
155
+
rt288x_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
156
if (!IS_ERR(rt288x_wdt_reset))
157
reset_control_deassert(rt288x_wdt_reset);
158
+1
-1
drivers/watchdog/sc1200wdt.c
+1
-1
drivers/watchdog/sc1200wdt.c
+1
-1
drivers/watchdog/sp805_wdt.c
+1
-1
drivers/watchdog/sp805_wdt.c
+1
-1
drivers/watchdog/stm32_iwdg.c
+1
-1
drivers/watchdog/stm32_iwdg.c
+1
-1
drivers/watchdog/ts72xx_wdt.c
+1
-1
drivers/watchdog/ts72xx_wdt.c
+1
-1
drivers/watchdog/w83627hf_wdt.c
+1
-1
drivers/watchdog/w83627hf_wdt.c
+1
-1
drivers/watchdog/ziirave_wdt.c
+1
-1
drivers/watchdog/ziirave_wdt.c
+1
-1
drivers/watchdog/zx2967_wdt.c
+1
-1
drivers/watchdog/zx2967_wdt.c