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dt-bindings: display/xlnx/zynqmp-dpsub: Add audio DMAs

The DP subsystem for ZynqMP supports audio via two channels, and the DP
DMA has dma-engines for those channels. For some reason the DT binding
has not specified those channels, even if the picture included in
xlnx,zynqmp-dpsub.yaml shows "2 x aud" DMAs.

This hasn't caused any issues as the drivers have not supported audio,
and has thus gone unnoticed.

To make it possible to add the audio support to the driver, add the two
audio DMAs to the binding. While strictly speaking this is an ABI break,
there should be no regressions caused by this as we're adding new
entries at the end of the dmas list, and, after the audio support has
been added in "arm64: dts: zynqmp: Add DMA for DP audio", the driver
will treat the audio DMAs as optional to also support the old bindings.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023-xilinx-dp-audio-v4-1-5128881457be@ideasonboard.com

+8 -2
+8 -2
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
··· 100 100 - description: Video layer, plane 1 (U/V or U) 101 101 - description: Video layer, plane 2 (V) 102 102 - description: Graphics layer 103 + - description: Audio channel 0 104 + - description: Audio channel 1 103 105 dma-names: 104 106 items: 105 107 - const: vid0 106 108 - const: vid1 107 109 - const: vid2 108 110 - const: gfx0 111 + - const: aud0 112 + - const: aud1 109 113 110 114 phys: 111 115 description: PHYs for the DP data lanes ··· 198 194 power-domains = <&pd_dp>; 199 195 resets = <&reset ZYNQMP_RESET_DP>; 200 196 201 - dma-names = "vid0", "vid1", "vid2", "gfx0"; 197 + dma-names = "vid0", "vid1", "vid2", "gfx0", "aud0", "aud1"; 202 198 dmas = <&xlnx_dpdma 0>, 203 199 <&xlnx_dpdma 1>, 204 200 <&xlnx_dpdma 2>, 205 - <&xlnx_dpdma 3>; 201 + <&xlnx_dpdma 3>, 202 + <&xlnx_dpdma 4>, 203 + <&xlnx_dpdma 5>; 206 204 207 205 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 208 206 <&psgtr 0 PHY_TYPE_DP 1 3>;