clk: samsung: exynos7: add gate clock for ADC block

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

authored by

Abhilash Kesavan and committed by

Sylwester Nawrocki 11 years ago 932e9822 2ab2dfe5

+4 -1

2 changed files

expand all

drivers

clk

samsung

clk-exynos7.c

include

dt-bindings

clock

exynos7-clk.h

drivers/clk/samsung/clk-exynos7.c

··· 486 486 ENABLE_PCLK_PERIC0, 14, 0, 0), 487 487 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 488 488 ENABLE_PCLK_PERIC0, 16, 0, 0), 489 + GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 490 + ENABLE_PCLK_PERIC0, 20, 0, 0), 489 491 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 490 492 ENABLE_PCLK_PERIC0, 21, 0, 0), 491 493

+2 -1

include/dt-bindings/clock/exynos7-clk.h

··· 55 55 #define PCLK_HSI2C11 9 56 56 #define PCLK_PWM 10 57 57 #define SCLK_PWM 11 58 - #define PERIC0_NR_CLK 12 58 + #define PCLK_ADCIF 12 59 + #define PERIC0_NR_CLK 13 59 60 60 61 /* PERIC1 */ 61 62 #define PCLK_UART1 1