tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ptp: clockmatrix: use rsmu driver to access i2c/spi bus

rsmu (Renesas Synchronization Management Unit ) driver is located in
drivers/mfd and responsible for creating multiple devices including
clockmatrix phc, which will then use the exposed regmap and mutex
handle to access i2c/spi bus.

Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Min Li and committed by
David S. Miller 930dfa56 b69c9946

+467 -1248
-783
drivers/ptp/idt8a340_reg.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* idt8a340_reg.h 3 - * 4 - * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019 5 - * https://github.com/richardcochran/regen 6 - * 7 - * Hand modified to include some HW registers. 8 - * Based on 5.2.0, Family Programming Guide (Sept 30, 2020) 9 - */ 10 - #ifndef HAVE_IDT8A340_REG 11 - #define HAVE_IDT8A340_REG 12 - 13 - #define PAGE_ADDR_BASE 0x0000 14 - #define PAGE_ADDR 0x00fc 15 - 16 - #define HW_REVISION 0x8180 17 - #define REV_ID 0x007a 18 - 19 - #define HW_DPLL_0 (0x8a00) 20 - #define HW_DPLL_1 (0x8b00) 21 - #define HW_DPLL_2 (0x8c00) 22 - #define HW_DPLL_3 (0x8d00) 23 - #define HW_DPLL_4 (0x8e00) 24 - #define HW_DPLL_5 (0x8f00) 25 - #define HW_DPLL_6 (0x9000) 26 - #define HW_DPLL_7 (0x9100) 27 - 28 - #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080) 29 - #define HW_DPLL_TOD_CTRL_1 (0x089) 30 - #define HW_DPLL_TOD_CTRL_2 (0x08A) 31 - #define HW_DPLL_TOD_OVR__0 (0x098) 32 - #define HW_DPLL_TOD_OUT_0__0 (0x0B0) 33 - 34 - #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740) 35 - #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741) 36 - #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742) 37 - #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743) 38 - #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744) 39 - #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745) 40 - #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746) 41 - #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747) 42 - #define HW_Q8_CH_SYNC_CTRL_0 (0xa748) 43 - #define HW_Q8_CH_SYNC_CTRL_1 (0xa749) 44 - #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a) 45 - #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b) 46 - #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c) 47 - #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d) 48 - #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e) 49 - #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f) 50 - 51 - #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14 52 - #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15 53 - #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16 54 - #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17 55 - 56 - #define SYNCTRL1_MASTER_SYNC_RST BIT(7) 57 - #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5) 58 - #define SYNCTRL1_TOD_SYNC_TRIG BIT(4) 59 - #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3) 60 - #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2) 61 - #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1) 62 - #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0) 63 - 64 - #define HW_Q8_CTRL_SPARE (0xa7d4) 65 - #define HW_Q11_CTRL_SPARE (0xa7ec) 66 - 67 - /** 68 - * Select FOD5 as sync_trigger for Q8 divider. 69 - * Transition from logic zero to one 70 - * sets trigger to sync Q8 divider. 71 - * 72 - * Unused when FOD4 is driving Q8 divider (normal operation). 73 - */ 74 - #define Q9_TO_Q8_SYNC_TRIG BIT(1) 75 - 76 - /** 77 - * Enable FOD5 as driver for clock and sync for Q8 divider. 78 - * Enable fanout buffer for FOD5. 79 - * 80 - * Unused when FOD4 is driving Q8 divider (normal operation). 81 - */ 82 - #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 83 - 84 - /** 85 - * Select FOD6 as sync_trigger for Q11 divider. 86 - * Transition from logic zero to one 87 - * sets trigger to sync Q11 divider. 88 - * 89 - * Unused when FOD7 is driving Q11 divider (normal operation). 90 - */ 91 - #define Q10_TO_Q11_SYNC_TRIG BIT(1) 92 - 93 - /** 94 - * Enable FOD6 as driver for clock and sync for Q11 divider. 95 - * Enable fanout buffer for FOD6. 96 - * 97 - * Unused when FOD7 is driving Q11 divider (normal operation). 98 - */ 99 - #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 100 - 101 - #define RESET_CTRL 0xc000 102 - #define SM_RESET 0x0012 103 - #define SM_RESET_V520 0x0013 104 - #define SM_RESET_CMD 0x5A 105 - 106 - #define GENERAL_STATUS 0xc014 107 - #define BOOT_STATUS 0x0000 108 - #define HW_REV_ID 0x000A 109 - #define BOND_ID 0x000B 110 - #define HW_CSR_ID 0x000C 111 - #define HW_IRQ_ID 0x000E 112 - 113 - #define MAJ_REL 0x0010 114 - #define MIN_REL 0x0011 115 - #define HOTFIX_REL 0x0012 116 - 117 - #define PIPELINE_ID 0x0014 118 - #define BUILD_ID 0x0018 119 - 120 - #define JTAG_DEVICE_ID 0x001c 121 - #define PRODUCT_ID 0x001e 122 - 123 - #define OTP_SCSR_CONFIG_SELECT 0x0022 124 - 125 - #define STATUS 0xc03c 126 - #define DPLL_SYS_STATUS 0x0020 127 - #define DPLL_SYS_APLL_STATUS 0x0021 128 - #define USER_GPIO0_TO_7_STATUS 0x008a 129 - #define USER_GPIO8_TO_15_STATUS 0x008b 130 - 131 - #define GPIO_USER_CONTROL 0xc160 132 - #define GPIO0_TO_7_OUT 0x0000 133 - #define GPIO8_TO_15_OUT 0x0001 134 - #define GPIO0_TO_7_OUT_V520 0x0002 135 - #define GPIO8_TO_15_OUT_V520 0x0003 136 - 137 - #define STICKY_STATUS_CLEAR 0xc164 138 - 139 - #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c 140 - 141 - #define ALERT_CFG 0xc188 142 - 143 - #define SYS_DPLL_XO 0xc194 144 - 145 - #define SYS_APLL 0xc19c 146 - 147 - #define INPUT_0 0xc1b0 148 - 149 - #define INPUT_1 0xc1c0 150 - 151 - #define INPUT_2 0xc1d0 152 - 153 - #define INPUT_3 0xc200 154 - 155 - #define INPUT_4 0xc210 156 - 157 - #define INPUT_5 0xc220 158 - 159 - #define INPUT_6 0xc230 160 - 161 - #define INPUT_7 0xc240 162 - 163 - #define INPUT_8 0xc250 164 - 165 - #define INPUT_9 0xc260 166 - 167 - #define INPUT_10 0xc280 168 - 169 - #define INPUT_11 0xc290 170 - 171 - #define INPUT_12 0xc2a0 172 - 173 - #define INPUT_13 0xc2b0 174 - 175 - #define INPUT_14 0xc2c0 176 - 177 - #define INPUT_15 0xc2d0 178 - 179 - #define REF_MON_0 0xc2e0 180 - 181 - #define REF_MON_1 0xc2ec 182 - 183 - #define REF_MON_2 0xc300 184 - 185 - #define REF_MON_3 0xc30c 186 - 187 - #define REF_MON_4 0xc318 188 - 189 - #define REF_MON_5 0xc324 190 - 191 - #define REF_MON_6 0xc330 192 - 193 - #define REF_MON_7 0xc33c 194 - 195 - #define REF_MON_8 0xc348 196 - 197 - #define REF_MON_9 0xc354 198 - 199 - #define REF_MON_10 0xc360 200 - 201 - #define REF_MON_11 0xc36c 202 - 203 - #define REF_MON_12 0xc380 204 - 205 - #define REF_MON_13 0xc38c 206 - 207 - #define REF_MON_14 0xc398 208 - 209 - #define REF_MON_15 0xc3a4 210 - 211 - #define DPLL_0 0xc3b0 212 - #define DPLL_CTRL_REG_0 0x0002 213 - #define DPLL_CTRL_REG_1 0x0003 214 - #define DPLL_CTRL_REG_2 0x0004 215 - #define DPLL_TOD_SYNC_CFG 0x0031 216 - #define DPLL_COMBO_SLAVE_CFG_0 0x0032 217 - #define DPLL_COMBO_SLAVE_CFG_1 0x0033 218 - #define DPLL_SLAVE_REF_CFG 0x0034 219 - #define DPLL_REF_MODE 0x0035 220 - #define DPLL_PHASE_MEASUREMENT_CFG 0x0036 221 - #define DPLL_MODE 0x0037 222 - #define DPLL_MODE_V520 0x003B 223 - 224 - #define DPLL_1 0xc400 225 - 226 - #define DPLL_2 0xc438 227 - #define DPLL_2_V520 0xc43c 228 - 229 - #define DPLL_3 0xc480 230 - 231 - #define DPLL_4 0xc4b8 232 - #define DPLL_4_V520 0xc4bc 233 - 234 - #define DPLL_5 0xc500 235 - 236 - #define DPLL_6 0xc538 237 - #define DPLL_6_V520 0xc53c 238 - 239 - #define DPLL_7 0xc580 240 - 241 - #define SYS_DPLL 0xc5b8 242 - #define SYS_DPLL_V520 0xc5bc 243 - 244 - #define DPLL_CTRL_0 0xc600 245 - #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001 246 - #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a 247 - 248 - #define DPLL_CTRL_1 0xc63c 249 - 250 - #define DPLL_CTRL_2 0xc680 251 - 252 - #define DPLL_CTRL_3 0xc6bc 253 - 254 - #define DPLL_CTRL_4 0xc700 255 - 256 - #define DPLL_CTRL_5 0xc73c 257 - 258 - #define DPLL_CTRL_6 0xc780 259 - 260 - #define DPLL_CTRL_7 0xc7bc 261 - 262 - #define SYS_DPLL_CTRL 0xc800 263 - 264 - #define DPLL_PHASE_0 0xc818 265 - 266 - /* Signed 42-bit FFO in units of 2^(-53) */ 267 - #define DPLL_WR_PHASE 0x0000 268 - 269 - #define DPLL_PHASE_1 0xc81c 270 - 271 - #define DPLL_PHASE_2 0xc820 272 - 273 - #define DPLL_PHASE_3 0xc824 274 - 275 - #define DPLL_PHASE_4 0xc828 276 - 277 - #define DPLL_PHASE_5 0xc82c 278 - 279 - #define DPLL_PHASE_6 0xc830 280 - 281 - #define DPLL_PHASE_7 0xc834 282 - 283 - #define DPLL_FREQ_0 0xc838 284 - 285 - /* Signed 42-bit FFO in units of 2^(-53) */ 286 - #define DPLL_WR_FREQ 0x0000 287 - 288 - #define DPLL_FREQ_1 0xc840 289 - 290 - #define DPLL_FREQ_2 0xc848 291 - 292 - #define DPLL_FREQ_3 0xc850 293 - 294 - #define DPLL_FREQ_4 0xc858 295 - 296 - #define DPLL_FREQ_5 0xc860 297 - 298 - #define DPLL_FREQ_6 0xc868 299 - 300 - #define DPLL_FREQ_7 0xc870 301 - 302 - #define DPLL_PHASE_PULL_IN_0 0xc880 303 - #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */ 304 - #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */ 305 - #define PULL_IN_CTRL 0x0007 306 - 307 - #define DPLL_PHASE_PULL_IN_1 0xc888 308 - 309 - #define DPLL_PHASE_PULL_IN_2 0xc890 310 - 311 - #define DPLL_PHASE_PULL_IN_3 0xc898 312 - 313 - #define DPLL_PHASE_PULL_IN_4 0xc8a0 314 - 315 - #define DPLL_PHASE_PULL_IN_5 0xc8a8 316 - 317 - #define DPLL_PHASE_PULL_IN_6 0xc8b0 318 - 319 - #define DPLL_PHASE_PULL_IN_7 0xc8b8 320 - 321 - #define GPIO_CFG 0xc8c0 322 - #define GPIO_CFG_GBL 0x0000 323 - 324 - #define GPIO_0 0xc8c2 325 - #define GPIO_DCO_INC_DEC 0x0000 326 - #define GPIO_OUT_CTRL_0 0x0001 327 - #define GPIO_OUT_CTRL_1 0x0002 328 - #define GPIO_TOD_TRIG 0x0003 329 - #define GPIO_DPLL_INDICATOR 0x0004 330 - #define GPIO_LOS_INDICATOR 0x0005 331 - #define GPIO_REF_INPUT_DSQ_0 0x0006 332 - #define GPIO_REF_INPUT_DSQ_1 0x0007 333 - #define GPIO_REF_INPUT_DSQ_2 0x0008 334 - #define GPIO_REF_INPUT_DSQ_3 0x0009 335 - #define GPIO_MAN_CLK_SEL_0 0x000a 336 - #define GPIO_MAN_CLK_SEL_1 0x000b 337 - #define GPIO_MAN_CLK_SEL_2 0x000c 338 - #define GPIO_SLAVE 0x000d 339 - #define GPIO_ALERT_OUT_CFG 0x000e 340 - #define GPIO_TOD_NOTIFICATION_CFG 0x000f 341 - #define GPIO_CTRL 0x0010 342 - #define GPIO_CTRL_V520 0x0011 343 - 344 - #define GPIO_1 0xc8d4 345 - 346 - #define GPIO_2 0xc8e6 347 - 348 - #define GPIO_3 0xc900 349 - 350 - #define GPIO_4 0xc912 351 - 352 - #define GPIO_5 0xc924 353 - 354 - #define GPIO_6 0xc936 355 - 356 - #define GPIO_7 0xc948 357 - 358 - #define GPIO_8 0xc95a 359 - 360 - #define GPIO_9 0xc980 361 - 362 - #define GPIO_10 0xc992 363 - 364 - #define GPIO_11 0xc9a4 365 - 366 - #define GPIO_12 0xc9b6 367 - 368 - #define GPIO_13 0xc9c8 369 - 370 - #define GPIO_14 0xc9da 371 - 372 - #define GPIO_15 0xca00 373 - 374 - #define OUT_DIV_MUX 0xca12 375 - 376 - #define OUTPUT_0 0xca14 377 - #define OUTPUT_0_V520 0xca20 378 - /* FOD frequency output divider value */ 379 - #define OUT_DIV 0x0000 380 - #define OUT_DUTY_CYCLE_HIGH 0x0004 381 - #define OUT_CTRL_0 0x0008 382 - #define OUT_CTRL_1 0x0009 383 - /* Phase adjustment in FOD cycles */ 384 - #define OUT_PHASE_ADJ 0x000c 385 - 386 - #define OUTPUT_1 0xca24 387 - #define OUTPUT_1_V520 0xca30 388 - 389 - #define OUTPUT_2 0xca34 390 - #define OUTPUT_2_V520 0xca40 391 - 392 - #define OUTPUT_3 0xca44 393 - #define OUTPUT_3_V520 0xca50 394 - 395 - #define OUTPUT_4 0xca54 396 - #define OUTPUT_4_V520 0xca60 397 - 398 - #define OUTPUT_5 0xca64 399 - #define OUTPUT_5_V520 0xca80 400 - 401 - #define OUTPUT_6 0xca80 402 - #define OUTPUT_6_V520 0xca90 403 - 404 - #define OUTPUT_7 0xca90 405 - #define OUTPUT_7_V520 0xcaa0 406 - 407 - #define OUTPUT_8 0xcaa0 408 - #define OUTPUT_8_V520 0xcab0 409 - 410 - #define OUTPUT_9 0xcab0 411 - #define OUTPUT_9_V520 0xcac0 412 - 413 - #define OUTPUT_10 0xcac0 414 - #define OUTPUT_10_V520 0xcad0 415 - 416 - #define OUTPUT_11 0xcad0 417 - #define OUTPUT_11_V520 0xcae0 418 - 419 - #define SERIAL 0xcae0 420 - #define SERIAL_V520 0xcaf0 421 - 422 - #define PWM_ENCODER_0 0xcb00 423 - 424 - #define PWM_ENCODER_1 0xcb08 425 - 426 - #define PWM_ENCODER_2 0xcb10 427 - 428 - #define PWM_ENCODER_3 0xcb18 429 - 430 - #define PWM_ENCODER_4 0xcb20 431 - 432 - #define PWM_ENCODER_5 0xcb28 433 - 434 - #define PWM_ENCODER_6 0xcb30 435 - 436 - #define PWM_ENCODER_7 0xcb38 437 - 438 - #define PWM_DECODER_0 0xcb40 439 - 440 - #define PWM_DECODER_1 0xcb48 441 - #define PWM_DECODER_1_V520 0xcb4a 442 - 443 - #define PWM_DECODER_2 0xcb50 444 - #define PWM_DECODER_2_V520 0xcb54 445 - 446 - #define PWM_DECODER_3 0xcb58 447 - #define PWM_DECODER_3_V520 0xcb5e 448 - 449 - #define PWM_DECODER_4 0xcb60 450 - #define PWM_DECODER_4_V520 0xcb68 451 - 452 - #define PWM_DECODER_5 0xcb68 453 - #define PWM_DECODER_5_V520 0xcb80 454 - 455 - #define PWM_DECODER_6 0xcb70 456 - #define PWM_DECODER_6_V520 0xcb8a 457 - 458 - #define PWM_DECODER_7 0xcb80 459 - #define PWM_DECODER_7_V520 0xcb94 460 - 461 - #define PWM_DECODER_8 0xcb88 462 - #define PWM_DECODER_8_V520 0xcb9e 463 - 464 - #define PWM_DECODER_9 0xcb90 465 - #define PWM_DECODER_9_V520 0xcba8 466 - 467 - #define PWM_DECODER_10 0xcb98 468 - #define PWM_DECODER_10_V520 0xcbb2 469 - 470 - #define PWM_DECODER_11 0xcba0 471 - #define PWM_DECODER_11_V520 0xcbbc 472 - 473 - #define PWM_DECODER_12 0xcba8 474 - #define PWM_DECODER_12_V520 0xcbc6 475 - 476 - #define PWM_DECODER_13 0xcbb0 477 - #define PWM_DECODER_13_V520 0xcbd0 478 - 479 - #define PWM_DECODER_14 0xcbb8 480 - #define PWM_DECODER_14_V520 0xcbda 481 - 482 - #define PWM_DECODER_15 0xcbc0 483 - #define PWM_DECODER_15_V520 0xcbe4 484 - 485 - #define PWM_USER_DATA 0xcbc8 486 - #define PWM_USER_DATA_V520 0xcbf0 487 - 488 - #define TOD_0 0xcbcc 489 - #define TOD_0_V520 0xcc00 490 - 491 - /* Enable TOD counter, output channel sync and even-PPS mode */ 492 - #define TOD_CFG 0x0000 493 - #define TOD_CFG_V520 0x0001 494 - 495 - #define TOD_1 0xcbce 496 - #define TOD_1_V520 0xcc02 497 - 498 - #define TOD_2 0xcbd0 499 - #define TOD_2_V520 0xcc04 500 - 501 - #define TOD_3 0xcbd2 502 - #define TOD_3_V520 0xcc06 503 - 504 - 505 - #define TOD_WRITE_0 0xcc00 506 - #define TOD_WRITE_0_V520 0xcc10 507 - /* 8-bit subns, 32-bit ns, 48-bit seconds */ 508 - #define TOD_WRITE 0x0000 509 - /* Counter increments after TOD write is completed */ 510 - #define TOD_WRITE_COUNTER 0x000c 511 - /* TOD write trigger configuration */ 512 - #define TOD_WRITE_SELECT_CFG_0 0x000d 513 - /* TOD write trigger selection */ 514 - #define TOD_WRITE_CMD 0x000f 515 - 516 - #define TOD_WRITE_1 0xcc10 517 - #define TOD_WRITE_1_V520 0xcc20 518 - 519 - #define TOD_WRITE_2 0xcc20 520 - #define TOD_WRITE_2_V520 0xcc30 521 - 522 - #define TOD_WRITE_3 0xcc30 523 - #define TOD_WRITE_3_V520 0xcc40 524 - 525 - #define TOD_READ_PRIMARY_0 0xcc40 526 - #define TOD_READ_PRIMARY_0_V520 0xcc50 527 - /* 8-bit subns, 32-bit ns, 48-bit seconds */ 528 - #define TOD_READ_PRIMARY 0x0000 529 - /* Counter increments after TOD write is completed */ 530 - #define TOD_READ_PRIMARY_COUNTER 0x000b 531 - /* Read trigger configuration */ 532 - #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c 533 - /* Read trigger selection */ 534 - #define TOD_READ_PRIMARY_CMD 0x000e 535 - #define TOD_READ_PRIMARY_CMD_V520 0x000f 536 - 537 - #define TOD_READ_PRIMARY_1 0xcc50 538 - #define TOD_READ_PRIMARY_1_V520 0xcc60 539 - 540 - #define TOD_READ_PRIMARY_2 0xcc60 541 - #define TOD_READ_PRIMARY_2_V520 0xcc80 542 - 543 - #define TOD_READ_PRIMARY_3 0xcc80 544 - #define TOD_READ_PRIMARY_3_V520 0xcc90 545 - 546 - #define TOD_READ_SECONDARY_0 0xcc90 547 - #define TOD_READ_SECONDARY_0_V520 0xcca0 548 - 549 - #define TOD_READ_SECONDARY_1 0xcca0 550 - #define TOD_READ_SECONDARY_1_V520 0xccb0 551 - 552 - #define TOD_READ_SECONDARY_2 0xccb0 553 - #define TOD_READ_SECONDARY_2_V520 0xccc0 554 - 555 - #define TOD_READ_SECONDARY_3 0xccc0 556 - #define TOD_READ_SECONDARY_3_V520 0xccd0 557 - 558 - #define OUTPUT_TDC_CFG 0xccd0 559 - #define OUTPUT_TDC_CFG_V520 0xcce0 560 - 561 - #define OUTPUT_TDC_0 0xcd00 562 - 563 - #define OUTPUT_TDC_1 0xcd08 564 - 565 - #define OUTPUT_TDC_2 0xcd10 566 - 567 - #define OUTPUT_TDC_3 0xcd18 568 - 569 - #define INPUT_TDC 0xcd20 570 - 571 - #define SCRATCH 0xcf50 572 - #define SCRATCH_V520 0xcf4c 573 - 574 - #define EEPROM 0xcf68 575 - #define EEPROM_V520 0xcf64 576 - 577 - #define OTP 0xcf70 578 - 579 - #define BYTE 0xcf80 580 - 581 - /* Bit definitions for the MAJ_REL register */ 582 - #define MAJOR_SHIFT (1) 583 - #define MAJOR_MASK (0x7f) 584 - #define PR_BUILD BIT(0) 585 - 586 - /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ 587 - #define GPIO0_LEVEL BIT(0) 588 - #define GPIO1_LEVEL BIT(1) 589 - #define GPIO2_LEVEL BIT(2) 590 - #define GPIO3_LEVEL BIT(3) 591 - #define GPIO4_LEVEL BIT(4) 592 - #define GPIO5_LEVEL BIT(5) 593 - #define GPIO6_LEVEL BIT(6) 594 - #define GPIO7_LEVEL BIT(7) 595 - 596 - /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ 597 - #define GPIO8_LEVEL BIT(0) 598 - #define GPIO9_LEVEL BIT(1) 599 - #define GPIO10_LEVEL BIT(2) 600 - #define GPIO11_LEVEL BIT(3) 601 - #define GPIO12_LEVEL BIT(4) 602 - #define GPIO13_LEVEL BIT(5) 603 - #define GPIO14_LEVEL BIT(6) 604 - #define GPIO15_LEVEL BIT(7) 605 - 606 - /* Bit definitions for the GPIO0_TO_7_OUT register */ 607 - #define GPIO0_DRIVE_LEVEL BIT(0) 608 - #define GPIO1_DRIVE_LEVEL BIT(1) 609 - #define GPIO2_DRIVE_LEVEL BIT(2) 610 - #define GPIO3_DRIVE_LEVEL BIT(3) 611 - #define GPIO4_DRIVE_LEVEL BIT(4) 612 - #define GPIO5_DRIVE_LEVEL BIT(5) 613 - #define GPIO6_DRIVE_LEVEL BIT(6) 614 - #define GPIO7_DRIVE_LEVEL BIT(7) 615 - 616 - /* Bit definitions for the GPIO8_TO_15_OUT register */ 617 - #define GPIO8_DRIVE_LEVEL BIT(0) 618 - #define GPIO9_DRIVE_LEVEL BIT(1) 619 - #define GPIO10_DRIVE_LEVEL BIT(2) 620 - #define GPIO11_DRIVE_LEVEL BIT(3) 621 - #define GPIO12_DRIVE_LEVEL BIT(4) 622 - #define GPIO13_DRIVE_LEVEL BIT(5) 623 - #define GPIO14_DRIVE_LEVEL BIT(6) 624 - #define GPIO15_DRIVE_LEVEL BIT(7) 625 - 626 - /* Bit definitions for the DPLL_TOD_SYNC_CFG register */ 627 - #define TOD_SYNC_SOURCE_SHIFT (1) 628 - #define TOD_SYNC_SOURCE_MASK (0x3) 629 - #define TOD_SYNC_EN BIT(0) 630 - 631 - /* Bit definitions for the DPLL_MODE register */ 632 - #define WRITE_TIMER_MODE BIT(6) 633 - #define PLL_MODE_SHIFT (3) 634 - #define PLL_MODE_MASK (0x7) 635 - #define STATE_MODE_SHIFT (0) 636 - #define STATE_MODE_MASK (0x7) 637 - 638 - /* Bit definitions for the DPLL_MANU_REF_CFG register */ 639 - #define MANUAL_REFERENCE_SHIFT (0) 640 - #define MANUAL_REFERENCE_MASK (0x1f) 641 - 642 - /* Bit definitions for the GPIO_CFG_GBL register */ 643 - #define SUPPLY_MODE_SHIFT (0) 644 - #define SUPPLY_MODE_MASK (0x3) 645 - 646 - /* Bit definitions for the GPIO_DCO_INC_DEC register */ 647 - #define INCDEC_DPLL_INDEX_SHIFT (0) 648 - #define INCDEC_DPLL_INDEX_MASK (0x7) 649 - 650 - /* Bit definitions for the GPIO_OUT_CTRL_0 register */ 651 - #define CTRL_OUT_0 BIT(0) 652 - #define CTRL_OUT_1 BIT(1) 653 - #define CTRL_OUT_2 BIT(2) 654 - #define CTRL_OUT_3 BIT(3) 655 - #define CTRL_OUT_4 BIT(4) 656 - #define CTRL_OUT_5 BIT(5) 657 - #define CTRL_OUT_6 BIT(6) 658 - #define CTRL_OUT_7 BIT(7) 659 - 660 - /* Bit definitions for the GPIO_OUT_CTRL_1 register */ 661 - #define CTRL_OUT_8 BIT(0) 662 - #define CTRL_OUT_9 BIT(1) 663 - #define CTRL_OUT_10 BIT(2) 664 - #define CTRL_OUT_11 BIT(3) 665 - #define CTRL_OUT_12 BIT(4) 666 - #define CTRL_OUT_13 BIT(5) 667 - #define CTRL_OUT_14 BIT(6) 668 - #define CTRL_OUT_15 BIT(7) 669 - 670 - /* Bit definitions for the GPIO_TOD_TRIG register */ 671 - #define TOD_TRIG_0 BIT(0) 672 - #define TOD_TRIG_1 BIT(1) 673 - #define TOD_TRIG_2 BIT(2) 674 - #define TOD_TRIG_3 BIT(3) 675 - 676 - /* Bit definitions for the GPIO_DPLL_INDICATOR register */ 677 - #define IND_DPLL_INDEX_SHIFT (0) 678 - #define IND_DPLL_INDEX_MASK (0x7) 679 - 680 - /* Bit definitions for the GPIO_LOS_INDICATOR register */ 681 - #define REFMON_INDEX_SHIFT (0) 682 - #define REFMON_INDEX_MASK (0xf) 683 - /* Active level of LOS indicator, 0=low 1=high */ 684 - #define ACTIVE_LEVEL BIT(4) 685 - 686 - /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ 687 - #define DSQ_INP_0 BIT(0) 688 - #define DSQ_INP_1 BIT(1) 689 - #define DSQ_INP_2 BIT(2) 690 - #define DSQ_INP_3 BIT(3) 691 - #define DSQ_INP_4 BIT(4) 692 - #define DSQ_INP_5 BIT(5) 693 - #define DSQ_INP_6 BIT(6) 694 - #define DSQ_INP_7 BIT(7) 695 - 696 - /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ 697 - #define DSQ_INP_8 BIT(0) 698 - #define DSQ_INP_9 BIT(1) 699 - #define DSQ_INP_10 BIT(2) 700 - #define DSQ_INP_11 BIT(3) 701 - #define DSQ_INP_12 BIT(4) 702 - #define DSQ_INP_13 BIT(5) 703 - #define DSQ_INP_14 BIT(6) 704 - #define DSQ_INP_15 BIT(7) 705 - 706 - /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ 707 - #define DSQ_DPLL_0 BIT(0) 708 - #define DSQ_DPLL_1 BIT(1) 709 - #define DSQ_DPLL_2 BIT(2) 710 - #define DSQ_DPLL_3 BIT(3) 711 - #define DSQ_DPLL_4 BIT(4) 712 - #define DSQ_DPLL_5 BIT(5) 713 - #define DSQ_DPLL_6 BIT(6) 714 - #define DSQ_DPLL_7 BIT(7) 715 - 716 - /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ 717 - #define DSQ_DPLL_SYS BIT(0) 718 - #define GPIO_DSQ_LEVEL BIT(1) 719 - 720 - /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ 721 - #define DPLL_TOD_SHIFT (0) 722 - #define DPLL_TOD_MASK (0x3) 723 - #define TOD_READ_SECONDARY BIT(2) 724 - #define GPIO_ASSERT_LEVEL BIT(3) 725 - 726 - /* Bit definitions for the GPIO_CTRL register */ 727 - #define GPIO_FUNCTION_EN BIT(0) 728 - #define GPIO_CMOS_OD_MODE BIT(1) 729 - #define GPIO_CONTROL_DIR BIT(2) 730 - #define GPIO_PU_PD_MODE BIT(3) 731 - #define GPIO_FUNCTION_SHIFT (4) 732 - #define GPIO_FUNCTION_MASK (0xf) 733 - 734 - /* Bit definitions for the OUT_CTRL_1 register */ 735 - #define OUT_SYNC_DISABLE BIT(7) 736 - #define SQUELCH_VALUE BIT(6) 737 - #define SQUELCH_DISABLE BIT(5) 738 - #define PAD_VDDO_SHIFT (2) 739 - #define PAD_VDDO_MASK (0x7) 740 - #define PAD_CMOSDRV_SHIFT (0) 741 - #define PAD_CMOSDRV_MASK (0x3) 742 - 743 - /* Bit definitions for the TOD_CFG register */ 744 - #define TOD_EVEN_PPS_MODE BIT(2) 745 - #define TOD_OUT_SYNC_ENABLE BIT(1) 746 - #define TOD_ENABLE BIT(0) 747 - 748 - /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ 749 - #define WR_PWM_DECODER_INDEX_SHIFT (4) 750 - #define WR_PWM_DECODER_INDEX_MASK (0xf) 751 - #define WR_REF_INDEX_SHIFT (0) 752 - #define WR_REF_INDEX_MASK (0xf) 753 - 754 - /* Bit definitions for the TOD_WRITE_CMD register */ 755 - #define TOD_WRITE_SELECTION_SHIFT (0) 756 - #define TOD_WRITE_SELECTION_MASK (0xf) 757 - /* 4.8.7 */ 758 - #define TOD_WRITE_TYPE_SHIFT (4) 759 - #define TOD_WRITE_TYPE_MASK (0x3) 760 - 761 - /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ 762 - #define RD_PWM_DECODER_INDEX_SHIFT (4) 763 - #define RD_PWM_DECODER_INDEX_MASK (0xf) 764 - #define RD_REF_INDEX_SHIFT (0) 765 - #define RD_REF_INDEX_MASK (0xf) 766 - 767 - /* Bit definitions for the TOD_READ_PRIMARY_CMD register */ 768 - #define TOD_READ_TRIGGER_MODE BIT(4) 769 - #define TOD_READ_TRIGGER_SHIFT (0) 770 - #define TOD_READ_TRIGGER_MASK (0xf) 771 - 772 - /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ 773 - #define COMBO_MASTER_HOLD BIT(0) 774 - 775 - /* Bit definitions for DPLL_SYS_STATUS register */ 776 - #define DPLL_SYS_STATE_MASK (0xf) 777 - 778 - /* Bit definitions for SYS_APLL_STATUS register */ 779 - #define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0) 780 - #define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0 781 - #define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1 782 - 783 - #endif
+417 -367
drivers/ptp/ptp_clockmatrix.c
··· 6 6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. 7 7 */ 8 8 #include <linux/firmware.h> 9 - #include <linux/i2c.h> 9 + #include <linux/platform_device.h> 10 10 #include <linux/module.h> 11 11 #include <linux/ptp_clock_kernel.h> 12 12 #include <linux/delay.h> ··· 14 14 #include <linux/kernel.h> 15 15 #include <linux/timekeeping.h> 16 16 #include <linux/string.h> 17 + #include <linux/of.h> 18 + #include <linux/mfd/rsmu.h> 19 + #include <linux/mfd/idt8a340_reg.h> 20 + #include <asm/unaligned.h> 17 21 18 22 #include "ptp_private.h" 19 23 #include "ptp_clockmatrix.h" ··· 36 32 module_param(firmware, charp, 0); 37 33 38 34 #define SETTIME_CORRECTION (0) 35 + #define EXTTS_PERIOD_MS (95) 39 36 40 37 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm); 38 + 39 + static inline int idtcm_read(struct idtcm *idtcm, 40 + u16 module, 41 + u16 regaddr, 42 + u8 *buf, 43 + u16 count) 44 + { 45 + return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); 46 + } 47 + 48 + static inline int idtcm_write(struct idtcm *idtcm, 49 + u16 module, 50 + u16 regaddr, 51 + u8 *buf, 52 + u16 count) 53 + { 54 + return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); 55 + } 41 56 42 57 static int contains_full_configuration(struct idtcm *idtcm, 43 58 const struct firmware *fw) ··· 196 173 return ver; 197 174 } 198 175 199 - static int idtcm_xfer_read(struct idtcm *idtcm, 200 - u8 regaddr, 201 - u8 *buf, 202 - u16 count) 203 - { 204 - struct i2c_client *client = idtcm->client; 205 - struct i2c_msg msg[2]; 206 - int cnt; 207 - 208 - msg[0].addr = client->addr; 209 - msg[0].flags = 0; 210 - msg[0].len = 1; 211 - msg[0].buf = &regaddr; 212 - 213 - msg[1].addr = client->addr; 214 - msg[1].flags = I2C_M_RD; 215 - msg[1].len = count; 216 - msg[1].buf = buf; 217 - 218 - cnt = i2c_transfer(client->adapter, msg, 2); 219 - 220 - if (cnt < 0) { 221 - dev_err(&client->dev, 222 - "i2c_transfer failed at %d in %s, at addr: %04x!", 223 - __LINE__, __func__, regaddr); 224 - return cnt; 225 - } else if (cnt != 2) { 226 - dev_err(&client->dev, 227 - "i2c_transfer sent only %d of %d messages", cnt, 2); 228 - return -EIO; 229 - } 230 - 231 - return 0; 232 - } 233 - 234 - static int idtcm_xfer_write(struct idtcm *idtcm, 235 - u8 regaddr, 236 - u8 *buf, 237 - u16 count) 238 - { 239 - struct i2c_client *client = idtcm->client; 240 - /* we add 1 byte for device register */ 241 - u8 msg[IDTCM_MAX_WRITE_COUNT + 1]; 242 - int cnt; 243 - 244 - if (count > IDTCM_MAX_WRITE_COUNT) 245 - return -EINVAL; 246 - 247 - msg[0] = regaddr; 248 - memcpy(&msg[1], buf, count); 249 - 250 - cnt = i2c_master_send(client, msg, count + 1); 251 - 252 - if (cnt < 0) { 253 - dev_err(&client->dev, 254 - "i2c_master_send failed at %d in %s, at addr: %04x!", 255 - __LINE__, __func__, regaddr); 256 - return cnt; 257 - } 258 - 259 - return 0; 260 - } 261 - 262 - static int idtcm_page_offset(struct idtcm *idtcm, u8 val) 263 - { 264 - u8 buf[4]; 265 - int err; 266 - 267 - if (idtcm->page_offset == val) 268 - return 0; 269 - 270 - buf[0] = 0x0; 271 - buf[1] = val; 272 - buf[2] = 0x10; 273 - buf[3] = 0x20; 274 - 275 - err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf)); 276 - if (err) { 277 - idtcm->page_offset = 0xff; 278 - dev_err(&idtcm->client->dev, "failed to set page offset"); 279 - } else { 280 - idtcm->page_offset = val; 281 - } 282 - 283 - return err; 284 - } 285 - 286 - static int _idtcm_rdwr(struct idtcm *idtcm, 287 - u16 regaddr, 288 - u8 *buf, 289 - u16 count, 290 - bool write) 291 - { 292 - u8 hi; 293 - u8 lo; 294 - int err; 295 - 296 - hi = (regaddr >> 8) & 0xff; 297 - lo = regaddr & 0xff; 298 - 299 - err = idtcm_page_offset(idtcm, hi); 300 - if (err) 301 - return err; 302 - 303 - if (write) 304 - return idtcm_xfer_write(idtcm, lo, buf, count); 305 - 306 - return idtcm_xfer_read(idtcm, lo, buf, count); 307 - } 308 - 309 - static int idtcm_read(struct idtcm *idtcm, 310 - u16 module, 311 - u16 regaddr, 312 - u8 *buf, 313 - u16 count) 314 - { 315 - return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); 316 - } 317 - 318 - static int idtcm_write(struct idtcm *idtcm, 319 - u16 module, 320 - u16 regaddr, 321 - u8 *buf, 322 - u16 count) 323 - { 324 - return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); 325 - } 326 - 327 176 static int clear_boot_status(struct idtcm *idtcm) 328 177 { 329 178 u8 buf[4] = {0}; ··· 234 339 235 340 } while (i); 236 341 237 - dev_warn(&idtcm->client->dev, "%s timed out", __func__); 342 + dev_warn(idtcm->dev, "%s timed out", __func__); 238 343 239 344 return -EBUSY; 345 + } 346 + 347 + static int _idtcm_set_scsr_read_trig(struct idtcm_channel *channel, 348 + enum scsr_read_trig_sel trig, u8 ref) 349 + { 350 + struct idtcm *idtcm = channel->idtcm; 351 + u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); 352 + u8 val; 353 + int err; 354 + 355 + if (trig == SCSR_TOD_READ_TRIG_SEL_REFCLK) { 356 + err = idtcm_read(idtcm, channel->tod_read_primary, 357 + TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val)); 358 + if (err) 359 + return err; 360 + 361 + val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT); 362 + val |= (ref << WR_REF_INDEX_SHIFT); 363 + 364 + err = idtcm_write(idtcm, channel->tod_read_primary, 365 + TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val)); 366 + if (err) 367 + return err; 368 + } 369 + 370 + err = idtcm_read(idtcm, channel->tod_read_primary, 371 + tod_read_cmd, &val, sizeof(val)); 372 + if (err) 373 + return err; 374 + 375 + val &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 376 + val |= (trig << TOD_READ_TRIGGER_SHIFT); 377 + val &= ~TOD_READ_TRIGGER_MODE; /* single shot */ 378 + 379 + err = idtcm_write(idtcm, channel->tod_read_primary, 380 + tod_read_cmd, &val, sizeof(val)); 381 + return err; 382 + } 383 + 384 + static int idtcm_enable_extts(struct idtcm_channel *channel, u8 todn, u8 ref, 385 + bool enable) 386 + { 387 + struct idtcm *idtcm = channel->idtcm; 388 + u8 old_mask = idtcm->extts_mask; 389 + u8 mask = 1 << todn; 390 + int err = 0; 391 + 392 + if (todn >= MAX_TOD) 393 + return -EINVAL; 394 + 395 + if (enable) { 396 + if (ref > 0xF) /* E_REF_CLK15 */ 397 + return -EINVAL; 398 + if (idtcm->extts_mask & mask) 399 + return 0; 400 + err = _idtcm_set_scsr_read_trig(&idtcm->channel[todn], 401 + SCSR_TOD_READ_TRIG_SEL_REFCLK, 402 + ref); 403 + if (err == 0) { 404 + idtcm->extts_mask |= mask; 405 + idtcm->event_channel[todn] = channel; 406 + idtcm->channel[todn].refn = ref; 407 + } 408 + } else 409 + idtcm->extts_mask &= ~mask; 410 + 411 + if (old_mask == 0 && idtcm->extts_mask) 412 + schedule_delayed_work(&idtcm->extts_work, 413 + msecs_to_jiffies(EXTTS_PERIOD_MS)); 414 + 415 + return err; 240 416 } 241 417 242 418 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status) ··· 346 380 } else if (dpll == DPLL_STATE_FREERUN || 347 381 dpll == DPLL_STATE_HOLDOVER || 348 382 dpll == DPLL_STATE_OPEN_LOOP) { 349 - dev_warn(&idtcm->client->dev, 383 + dev_warn(idtcm->dev, 350 384 "No wait state: DPLL_SYS_STATE %d", dpll); 351 385 return -EPERM; 352 386 } ··· 354 388 msleep(LOCK_POLL_INTERVAL_MS); 355 389 } while (time_is_after_jiffies(timeout)); 356 390 357 - dev_warn(&idtcm->client->dev, 391 + dev_warn(idtcm->dev, 358 392 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d", 359 393 LOCK_TIMEOUT_MS, apll, dpll); 360 394 ··· 364 398 static void wait_for_chip_ready(struct idtcm *idtcm) 365 399 { 366 400 if (wait_for_boot_status_ready(idtcm)) 367 - dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0"); 401 + dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0"); 368 402 369 403 if (wait_for_sys_apll_dpll_lock(idtcm)) 370 - dev_warn(&idtcm->client->dev, 404 + dev_warn(idtcm->dev, 371 405 "Continuing while SYS APLL/DPLL is not locked"); 372 406 } 373 407 374 408 static int _idtcm_gettime(struct idtcm_channel *channel, 375 - struct timespec64 *ts) 409 + struct timespec64 *ts, u8 timeout) 376 410 { 377 411 struct idtcm *idtcm = channel->idtcm; 378 412 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); 379 413 u8 buf[TOD_BYTE_COUNT]; 380 - u8 timeout = 10; 381 414 u8 trigger; 382 415 int err; 383 416 384 - err = idtcm_read(idtcm, channel->tod_read_primary, 385 - tod_read_cmd, &trigger, sizeof(trigger)); 386 - if (err) 387 - return err; 388 - 389 - trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); 390 - trigger |= (1 << TOD_READ_TRIGGER_SHIFT); 391 - trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */ 392 - 393 - err = idtcm_write(idtcm, channel->tod_read_primary, 394 - tod_read_cmd, &trigger, sizeof(trigger)); 395 - if (err) 396 - return err; 397 - 398 417 /* wait trigger to be 0 */ 399 - while (trigger & TOD_READ_TRIGGER_MASK) { 418 + do { 419 + if (timeout-- == 0) 420 + return -EIO; 421 + 400 422 if (idtcm->calculate_overhead_flag) 401 423 idtcm->start_time = ktime_get_raw(); 402 424 ··· 393 439 sizeof(trigger)); 394 440 if (err) 395 441 return err; 396 - 397 - if (--timeout == 0) 398 - return -EIO; 399 - } 442 + } while (trigger & TOD_READ_TRIGGER_MASK); 400 443 401 444 err = idtcm_read(idtcm, channel->tod_read_primary, 402 445 TOD_READ_PRIMARY, buf, sizeof(buf)); ··· 401 450 return err; 402 451 403 452 err = char_array_to_timespec(buf, sizeof(buf), ts); 453 + 454 + return err; 455 + } 456 + 457 + static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn) 458 + { 459 + struct idtcm_channel *ptp_channel, *extts_channel; 460 + struct ptp_clock_event event; 461 + struct timespec64 ts; 462 + u32 dco_delay = 0; 463 + int err; 464 + 465 + extts_channel = &idtcm->channel[todn]; 466 + ptp_channel = idtcm->event_channel[todn]; 467 + if (extts_channel == ptp_channel) 468 + dco_delay = ptp_channel->dco_delay; 469 + 470 + err = _idtcm_gettime(extts_channel, &ts, 1); 471 + if (err == 0) { 472 + event.type = PTP_CLOCK_EXTTS; 473 + event.index = todn; 474 + event.timestamp = timespec64_to_ns(&ts) - dco_delay; 475 + ptp_clock_event(ptp_channel->ptp_clock, &event); 476 + } 477 + return err; 478 + } 479 + 480 + static u8 idtcm_enable_extts_mask(struct idtcm_channel *channel, 481 + u8 extts_mask, bool enable) 482 + { 483 + struct idtcm *idtcm = channel->idtcm; 484 + int i, err; 485 + 486 + for (i = 0; i < MAX_TOD; i++) { 487 + u8 mask = 1 << i; 488 + u8 refn = idtcm->channel[i].refn; 489 + 490 + if (extts_mask & mask) { 491 + /* check extts before disabling it */ 492 + if (enable == false) { 493 + err = idtcm_extts_check_channel(idtcm, i); 494 + /* trigger happened so we won't re-enable it */ 495 + if (err == 0) 496 + extts_mask &= ~mask; 497 + } 498 + (void)idtcm_enable_extts(channel, i, refn, enable); 499 + } 500 + } 501 + 502 + return extts_mask; 503 + } 504 + 505 + static int _idtcm_gettime_immediate(struct idtcm_channel *channel, 506 + struct timespec64 *ts) 507 + { 508 + struct idtcm *idtcm = channel->idtcm; 509 + u8 extts_mask = 0; 510 + int err; 511 + 512 + /* Disable extts */ 513 + if (idtcm->extts_mask) { 514 + extts_mask = idtcm_enable_extts_mask(channel, idtcm->extts_mask, 515 + false); 516 + } 517 + 518 + err = _idtcm_set_scsr_read_trig(channel, 519 + SCSR_TOD_READ_TRIG_SEL_IMMEDIATE, 0); 520 + if (err == 0) 521 + err = _idtcm_gettime(channel, ts, 10); 522 + 523 + /* Re-enable extts */ 524 + if (extts_mask) 525 + idtcm_enable_extts_mask(channel, extts_mask, true); 404 526 405 527 return err; 406 528 } ··· 801 777 break; 802 778 803 779 if (++count > 20) { 804 - dev_err(&idtcm->client->dev, 780 + dev_err(idtcm->dev, 805 781 "Timed out waiting for the write counter"); 806 782 return -EIO; 807 783 } ··· 866 842 867 843 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); 868 844 if (err) { 869 - dev_err(&idtcm->client->dev, 845 + dev_err(idtcm->dev, 870 846 "%s: Set HW ToD failed", __func__); 871 847 return err; 872 848 } ··· 1025 1001 if (err) 1026 1002 return err; 1027 1003 1028 - err = _idtcm_gettime(channel, &ts); 1004 + err = _idtcm_gettime_immediate(channel, &ts); 1029 1005 if (err) 1030 1006 return err; 1031 1007 ··· 1059 1035 read_boot_status(idtcm, &status); 1060 1036 1061 1037 if (status == 0xA0) { 1062 - dev_dbg(&idtcm->client->dev, 1038 + dev_dbg(idtcm->dev, 1063 1039 "SM_RESET completed in %d ms", i * 100); 1064 1040 break; 1065 1041 } 1066 1042 } 1067 1043 1068 1044 if (!status) 1069 - dev_err(&idtcm->client->dev, 1045 + dev_err(idtcm->dev, 1070 1046 "Timed out waiting for CM_RESET to complete"); 1071 1047 } 1072 1048 ··· 1163 1139 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) 1164 1140 { 1165 1141 if (index >= MAX_TOD) { 1166 - dev_err(&idtcm->client->dev, "ToD%d not supported", index); 1142 + dev_err(idtcm->dev, "ToD%d not supported", index); 1167 1143 return -EINVAL; 1168 1144 } 1169 1145 1170 1146 if (pll >= MAX_PLL) { 1171 - dev_err(&idtcm->client->dev, "Pll%d not supported", pll); 1147 + dev_err(idtcm->dev, "Pll%d not supported", pll); 1172 1148 return -EINVAL; 1173 1149 } 1174 1150 ··· 1186 1162 switch (regaddr) { 1187 1163 case TOD_MASK_ADDR: 1188 1164 if ((val & 0xf0) || !(val & 0x0f)) { 1189 - dev_err(&idtcm->client->dev, "Invalid TOD mask 0x%02x", val); 1165 + dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val); 1190 1166 err = -EINVAL; 1191 1167 } else { 1192 1168 idtcm->tod_mask = val; ··· 1217 1193 u8 i; 1218 1194 u8 mask; 1219 1195 1220 - dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x", idtcm->tod_mask); 1196 + dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask); 1221 1197 1222 1198 for (i = 0; i < MAX_TOD; i++) { 1223 1199 mask = 1 << i; 1224 1200 1225 1201 if (mask & idtcm->tod_mask) 1226 - dev_dbg(&idtcm->client->dev, 1202 + dev_dbg(idtcm->dev, 1227 1203 "TOD%d pll = %d output_mask = 0x%04x", 1228 1204 i, idtcm->channel[i].pll, 1229 1205 idtcm->channel[i].output_mask); ··· 1246 1222 if (firmware) /* module parameter */ 1247 1223 snprintf(fname, sizeof(fname), "%s", firmware); 1248 1224 1249 - dev_info(&idtcm->client->dev, "firmware '%s'", fname); 1225 + dev_info(idtcm->dev, "requesting firmware '%s'", fname); 1250 1226 1251 1227 err = request_firmware(&fw, fname, dev); 1252 1228 if (err) { 1253 - dev_err(&idtcm->client->dev, 1229 + dev_err(idtcm->dev, 1254 1230 "Failed at line %d in %s!", __LINE__, __func__); 1255 1231 return err; 1256 1232 } 1257 1233 1258 - dev_dbg(&idtcm->client->dev, "firmware size %zu bytes", fw->size); 1234 + dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size); 1259 1235 1260 1236 rec = (struct idtcm_fwrc *) fw->data; 1261 1237 ··· 1264 1240 1265 1241 for (len = fw->size; len > 0; len -= sizeof(*rec)) { 1266 1242 if (rec->reserved) { 1267 - dev_err(&idtcm->client->dev, 1243 + dev_err(idtcm->dev, 1268 1244 "bad firmware, reserved field non-zero"); 1269 1245 err = -EINVAL; 1270 1246 } else { ··· 1315 1291 base = get_output_base_addr(idtcm->fw_ver, outn); 1316 1292 1317 1293 if (!(base > 0)) { 1318 - dev_err(&idtcm->client->dev, 1294 + dev_err(idtcm->dev, 1319 1295 "%s - Unsupported out%d", __func__, outn); 1320 1296 return base; 1321 1297 } ··· 1357 1333 } 1358 1334 1359 1335 static int idtcm_perout_enable(struct idtcm_channel *channel, 1360 - bool enable, 1361 - struct ptp_perout_request *perout) 1336 + struct ptp_perout_request *perout, 1337 + bool enable) 1362 1338 { 1363 1339 struct idtcm *idtcm = channel->idtcm; 1364 1340 unsigned int flags = perout->flags; ··· 1371 1347 err = idtcm_output_enable(channel, enable, perout->index); 1372 1348 1373 1349 if (err) { 1374 - dev_err(&idtcm->client->dev, "Unable to set output enable"); 1350 + dev_err(idtcm->dev, "Unable to set output enable"); 1375 1351 return err; 1376 1352 } 1377 1353 ··· 1472 1448 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); 1473 1449 1474 1450 if (err) 1475 - dev_err(&idtcm->client->dev, "Failed to set pll mode to write frequency"); 1451 + dev_err(idtcm->dev, "Failed to set pll mode to write frequency"); 1476 1452 else 1477 1453 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1478 1454 ··· 1487 1463 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE); 1488 1464 1489 1465 if (err) 1490 - dev_err(&idtcm->client->dev, "Failed to set pll mode to write phase"); 1466 + dev_err(idtcm->dev, "Failed to set pll mode to write phase"); 1491 1467 else 1492 1468 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1493 1469 ··· 1502 1478 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY); 1503 1479 1504 1480 if (err) 1505 - dev_err(&idtcm->client->dev, "Failed to set manual reference to write frequency"); 1481 + dev_err(idtcm->dev, "Failed to set manual reference to write frequency"); 1506 1482 else 1507 1483 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1508 1484 ··· 1517 1493 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE); 1518 1494 1519 1495 if (err) 1520 - dev_err(&idtcm->client->dev, "Failed to set manual reference to write phase"); 1496 + dev_err(idtcm->dev, "Failed to set manual reference to write phase"); 1521 1497 else 1522 1498 channel->mode = PTP_PLL_MODE_WRITE_PHASE; 1523 1499 ··· 1542 1518 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1543 1519 struct idtcm *idtcm = channel->idtcm; 1544 1520 1545 - mutex_lock(&idtcm->reg_lock); 1521 + mutex_lock(idtcm->lock); 1546 1522 1547 1523 (void)idtcm_stop_phase_pull_in(channel); 1548 1524 1549 - mutex_unlock(&idtcm->reg_lock); 1525 + mutex_unlock(idtcm->lock); 1550 1526 1551 1527 /* Return a negative value here to not reschedule */ 1552 1528 return -1; ··· 1557 1533 /* ppb = scaled_ppm * 125 / 2^13 */ 1558 1534 /* scaled_ppm = ppb * 2^13 / 125 */ 1559 1535 1560 - s64 max_scaled_ppm = (PHASE_PULL_IN_MAX_PPB << 13) / 125; 1561 - s64 scaled_ppm = (phase_pull_in_ppb << 13) / 125; 1536 + s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125); 1537 + s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125); 1562 1538 1563 1539 current_ppm += scaled_ppm; 1564 1540 ··· 1631 1607 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1632 1608 break; 1633 1609 default: 1634 - dev_warn(&idtcm->client->dev, 1610 + dev_warn(idtcm->dev, 1635 1611 "Unsupported MANUAL_REFERENCE: 0x%02x", ref); 1636 1612 } 1637 1613 ··· 1657 1633 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; 1658 1634 break; 1659 1635 default: 1660 - dev_err(&idtcm->client->dev, 1636 + dev_err(idtcm->dev, 1661 1637 "Unsupported PLL_MODE: 0x%02x", mode); 1662 1638 err = -EINVAL; 1663 1639 } ··· 1676 1652 1677 1653 err = idtcm_get_pll_mode(channel, &mode); 1678 1654 if (err) { 1679 - dev_err(&idtcm->client->dev, "Unable to read pll mode!"); 1655 + dev_err(idtcm->dev, "Unable to read pll mode!"); 1680 1656 return err; 1681 1657 } 1682 1658 1683 1659 if (mode == PLL_MODE_PLL) { 1684 1660 err = idtcm_get_manual_reference(channel, &ref); 1685 1661 if (err) { 1686 - dev_err(&idtcm->client->dev, "Unable to read manual reference!"); 1662 + dev_err(idtcm->dev, "Unable to read manual reference!"); 1687 1663 return err; 1688 1664 } 1689 1665 err = initialize_operating_mode_with_manual_reference(channel, ref); ··· 1799 1775 struct idtcm *idtcm = channel->idtcm; 1800 1776 int err; 1801 1777 1802 - mutex_lock(&idtcm->reg_lock); 1778 + mutex_lock(idtcm->lock); 1779 + err = _idtcm_gettime_immediate(channel, ts); 1780 + mutex_unlock(idtcm->lock); 1803 1781 1804 - err = _idtcm_gettime(channel, ts); 1805 1782 if (err) 1806 - dev_err(&idtcm->client->dev, "Failed at line %d in %s!", 1783 + dev_err(idtcm->dev, "Failed at line %d in %s!", 1807 1784 __LINE__, __func__); 1808 - 1809 - mutex_unlock(&idtcm->reg_lock); 1810 1785 1811 1786 return err; 1812 1787 } ··· 1817 1794 struct idtcm *idtcm = channel->idtcm; 1818 1795 int err; 1819 1796 1820 - mutex_lock(&idtcm->reg_lock); 1821 - 1797 + mutex_lock(idtcm->lock); 1822 1798 err = _idtcm_settime_deprecated(channel, ts); 1823 - if (err) 1824 - dev_err(&idtcm->client->dev, 1825 - "Failed at line %d in %s!", __LINE__, __func__); 1799 + mutex_unlock(idtcm->lock); 1826 1800 1827 - mutex_unlock(&idtcm->reg_lock); 1801 + if (err) 1802 + dev_err(idtcm->dev, 1803 + "Failed at line %d in %s!", __LINE__, __func__); 1828 1804 1829 1805 return err; 1830 1806 } ··· 1835 1813 struct idtcm *idtcm = channel->idtcm; 1836 1814 int err; 1837 1815 1838 - mutex_lock(&idtcm->reg_lock); 1839 - 1816 + mutex_lock(idtcm->lock); 1840 1817 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE); 1841 - if (err) 1842 - dev_err(&idtcm->client->dev, 1843 - "Failed at line %d in %s!", __LINE__, __func__); 1818 + mutex_unlock(idtcm->lock); 1844 1819 1845 - mutex_unlock(&idtcm->reg_lock); 1820 + if (err) 1821 + dev_err(idtcm->dev, 1822 + "Failed at line %d in %s!", __LINE__, __func__); 1846 1823 1847 1824 return err; 1848 1825 } ··· 1852 1831 struct idtcm *idtcm = channel->idtcm; 1853 1832 int err; 1854 1833 1855 - mutex_lock(&idtcm->reg_lock); 1856 - 1834 + mutex_lock(idtcm->lock); 1857 1835 err = _idtcm_adjtime_deprecated(channel, delta); 1858 - if (err) 1859 - dev_err(&idtcm->client->dev, 1860 - "Failed at line %d in %s!", __LINE__, __func__); 1836 + mutex_unlock(idtcm->lock); 1861 1837 1862 - mutex_unlock(&idtcm->reg_lock); 1838 + if (err) 1839 + dev_err(idtcm->dev, 1840 + "Failed at line %d in %s!", __LINE__, __func__); 1863 1841 1864 1842 return err; 1865 1843 } ··· 1874 1854 if (channel->phase_pull_in == true) 1875 1855 return 0; 1876 1856 1877 - mutex_lock(&idtcm->reg_lock); 1857 + mutex_lock(idtcm->lock); 1878 1858 1879 1859 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { 1880 1860 err = channel->do_phase_pull_in(channel, delta, 0); 1881 - if (err) 1882 - dev_err(&idtcm->client->dev, 1883 - "Failed at line %d in %s!", __LINE__, __func__); 1884 1861 } else { 1885 1862 if (delta >= 0) { 1886 1863 ts = ns_to_timespec64(delta); ··· 1887 1870 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS; 1888 1871 } 1889 1872 err = _idtcm_settime(channel, &ts, type); 1890 - if (err) 1891 - dev_err(&idtcm->client->dev, 1892 - "Failed at line %d in %s!", __LINE__, __func__); 1893 1873 } 1894 - mutex_unlock(&idtcm->reg_lock); 1874 + 1875 + mutex_unlock(idtcm->lock); 1876 + 1877 + if (err) 1878 + dev_err(idtcm->dev, 1879 + "Failed at line %d in %s!", __LINE__, __func__); 1895 1880 1896 1881 return err; 1897 1882 } ··· 1904 1885 struct idtcm *idtcm = channel->idtcm; 1905 1886 int err; 1906 1887 1907 - mutex_lock(&idtcm->reg_lock); 1908 - 1888 + mutex_lock(idtcm->lock); 1909 1889 err = _idtcm_adjphase(channel, delta); 1910 - if (err) 1911 - dev_err(&idtcm->client->dev, 1912 - "Failed at line %d in %s!", __LINE__, __func__); 1890 + mutex_unlock(idtcm->lock); 1913 1891 1914 - mutex_unlock(&idtcm->reg_lock); 1892 + if (err) 1893 + dev_err(idtcm->dev, 1894 + "Failed at line %d in %s!", __LINE__, __func__); 1915 1895 1916 1896 return err; 1917 1897 } ··· 1927 1909 if (scaled_ppm == channel->current_freq_scaled_ppm) 1928 1910 return 0; 1929 1911 1930 - mutex_lock(&idtcm->reg_lock); 1931 - 1912 + mutex_lock(idtcm->lock); 1932 1913 err = _idtcm_adjfine(channel, scaled_ppm); 1914 + mutex_unlock(idtcm->lock); 1933 1915 1934 - mutex_unlock(&idtcm->reg_lock); 1935 - 1936 - if (!err) 1916 + if (err) 1917 + dev_err(idtcm->dev, 1918 + "Failed at line %d in %s!", __LINE__, __func__); 1919 + else 1937 1920 channel->current_freq_scaled_ppm = scaled_ppm; 1938 1921 1939 1922 return err; ··· 1943 1924 static int idtcm_enable(struct ptp_clock_info *ptp, 1944 1925 struct ptp_clock_request *rq, int on) 1945 1926 { 1946 - int err; 1947 1927 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); 1928 + struct idtcm *idtcm = channel->idtcm; 1929 + int err = -EOPNOTSUPP; 1930 + 1931 + mutex_lock(idtcm->lock); 1948 1932 1949 1933 switch (rq->type) { 1950 1934 case PTP_CLK_REQ_PEROUT: 1951 - if (!on) { 1952 - err = idtcm_perout_enable(channel, false, &rq->perout); 1953 - if (err) 1954 - dev_err(&channel->idtcm->client->dev, 1955 - "Failed at line %d in %s!", 1956 - __LINE__, __func__); 1957 - return err; 1958 - } 1959 - 1935 + if (!on) 1936 + err = idtcm_perout_enable(channel, &rq->perout, false); 1960 1937 /* Only accept a 1-PPS aligned to the second. */ 1961 - if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1962 - rq->perout.period.nsec) 1963 - return -ERANGE; 1964 - 1965 - err = idtcm_perout_enable(channel, true, &rq->perout); 1966 - if (err) 1967 - dev_err(&channel->idtcm->client->dev, 1968 - "Failed at line %d in %s!", __LINE__, __func__); 1969 - return err; 1938 + else if (rq->perout.start.nsec || rq->perout.period.sec != 1 || 1939 + rq->perout.period.nsec) 1940 + err = -ERANGE; 1941 + else 1942 + err = idtcm_perout_enable(channel, &rq->perout, true); 1943 + break; 1944 + case PTP_CLK_REQ_EXTTS: 1945 + err = idtcm_enable_extts(channel, rq->extts.index, 1946 + rq->extts.rsv[0], on); 1947 + break; 1970 1948 default: 1971 1949 break; 1972 1950 } 1973 1951 1974 - return -EOPNOTSUPP; 1952 + mutex_unlock(idtcm->lock); 1953 + 1954 + if (err) 1955 + dev_err(channel->idtcm->dev, 1956 + "Failed in %s with err %d!", __func__, err); 1957 + 1958 + return err; 1975 1959 } 1976 1960 1977 1961 static int idtcm_enable_tod(struct idtcm_channel *channel) ··· 2035 2013 2036 2014 idtcm->fw_ver = idtcm_fw_version(idtcm->version); 2037 2015 2038 - dev_info(&idtcm->client->dev, 2016 + dev_info(idtcm->dev, 2039 2017 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d", 2040 2018 major, minor, hotfix, 2041 2019 product_id, hw_rev_id, config_select); ··· 2045 2023 .owner = THIS_MODULE, 2046 2024 .max_adj = 244000, 2047 2025 .n_per_out = 12, 2026 + .n_ext_ts = MAX_TOD, 2048 2027 .adjphase = &idtcm_adjphase, 2049 2028 .adjfine = &idtcm_adjfine, 2050 2029 .adjtime = &idtcm_adjtime, ··· 2059 2036 .owner = THIS_MODULE, 2060 2037 .max_adj = 244000, 2061 2038 .n_per_out = 12, 2039 + .n_ext_ts = MAX_TOD, 2062 2040 .adjphase = &idtcm_adjphase, 2063 2041 .adjfine = &idtcm_adjfine, 2064 2042 .adjtime = &idtcm_adjtime_deprecated, ··· 2146 2122 return err; 2147 2123 } 2148 2124 2149 - static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 2125 + /* 2126 + * Compensate for the PTP DCO input-to-output delay. 2127 + * This delay is 18 FOD cycles. 2128 + */ 2129 + static u32 idtcm_get_dco_delay(struct idtcm_channel *channel) 2150 2130 { 2151 - enum fw_version fw_ver = idtcm->fw_ver; 2152 - struct idtcm_channel *channel; 2131 + struct idtcm *idtcm = channel->idtcm; 2132 + u8 mbuf[8] = {0}; 2133 + u8 nbuf[2] = {0}; 2134 + u32 fodFreq; 2153 2135 int err; 2136 + u64 m; 2137 + u16 n; 2154 2138 2155 - if (!(index < MAX_TOD)) 2156 - return -EINVAL; 2157 - 2158 - channel = &idtcm->channel[index]; 2159 - 2160 - channel->idtcm = idtcm; 2161 - channel->current_freq_scaled_ppm = 0; 2162 - 2163 - /* Set pll addresses */ 2164 - err = configure_channel_pll(channel); 2139 + err = idtcm_read(idtcm, channel->dpll_ctrl_n, 2140 + DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6); 2165 2141 if (err) 2166 - return err; 2142 + return 0; 2143 + 2144 + err = idtcm_read(idtcm, channel->dpll_ctrl_n, 2145 + DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2); 2146 + if (err) 2147 + return 0; 2148 + 2149 + m = get_unaligned_le64(mbuf); 2150 + n = get_unaligned_le16(nbuf); 2151 + 2152 + if (n == 0) 2153 + n = 1; 2154 + 2155 + fodFreq = (u32)div_u64(m, n); 2156 + if (fodFreq >= 500000000) 2157 + return 18 * (u32)div_u64(NSEC_PER_SEC, fodFreq); 2158 + 2159 + return 0; 2160 + } 2161 + 2162 + static int configure_channel_tod(struct idtcm_channel *channel, u32 index) 2163 + { 2164 + enum fw_version fw_ver = channel->idtcm->fw_ver; 2167 2165 2168 2166 /* Set tod addresses */ 2169 2167 switch (index) { ··· 2217 2171 return -EINVAL; 2218 2172 } 2219 2173 2174 + return 0; 2175 + } 2176 + 2177 + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) 2178 + { 2179 + struct idtcm_channel *channel; 2180 + int err; 2181 + 2182 + if (!(index < MAX_TOD)) 2183 + return -EINVAL; 2184 + 2185 + channel = &idtcm->channel[index]; 2186 + 2187 + channel->idtcm = idtcm; 2188 + channel->current_freq_scaled_ppm = 0; 2189 + 2190 + /* Set pll addresses */ 2191 + err = configure_channel_pll(channel); 2192 + if (err) 2193 + return err; 2194 + 2195 + /* Set tod addresses */ 2196 + err = configure_channel_tod(channel, index); 2197 + if (err) 2198 + return err; 2199 + 2220 2200 if (idtcm->fw_ver < V487) 2221 2201 channel->caps = idtcm_caps_deprecated; 2222 2202 else ··· 2257 2185 2258 2186 err = idtcm_enable_tod(channel); 2259 2187 if (err) { 2260 - dev_err(&idtcm->client->dev, 2188 + dev_err(idtcm->dev, 2261 2189 "Failed at line %d in %s!", __LINE__, __func__); 2262 2190 return err; 2263 2191 } 2192 + 2193 + channel->dco_delay = idtcm_get_dco_delay(channel); 2264 2194 2265 2195 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); 2266 2196 ··· 2275 2201 if (!channel->ptp_clock) 2276 2202 return -ENOTSUPP; 2277 2203 2278 - dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d", 2204 + dev_info(idtcm->dev, "PLL%d registered as ptp%d", 2279 2205 index, channel->ptp_clock->index); 2280 2206 2281 2207 return 0; 2208 + } 2209 + 2210 + static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index) 2211 + { 2212 + struct idtcm_channel *channel; 2213 + int err; 2214 + 2215 + if (!(index < MAX_TOD)) 2216 + return -EINVAL; 2217 + 2218 + channel = &idtcm->channel[index]; 2219 + channel->idtcm = idtcm; 2220 + 2221 + /* Set tod addresses */ 2222 + err = configure_channel_tod(channel, index); 2223 + if (err) 2224 + return err; 2225 + 2226 + channel->idtcm = idtcm; 2227 + 2228 + return 0; 2229 + } 2230 + 2231 + static void idtcm_extts_check(struct work_struct *work) 2232 + { 2233 + struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work); 2234 + int err, i; 2235 + 2236 + if (idtcm->extts_mask == 0) 2237 + return; 2238 + 2239 + mutex_lock(idtcm->lock); 2240 + for (i = 0; i < MAX_TOD; i++) { 2241 + u8 mask = 1 << i; 2242 + 2243 + if (idtcm->extts_mask & mask) { 2244 + err = idtcm_extts_check_channel(idtcm, i); 2245 + /* trigger clears itself, so clear the mask */ 2246 + if (err == 0) 2247 + idtcm->extts_mask &= ~mask; 2248 + } 2249 + } 2250 + 2251 + if (idtcm->extts_mask) 2252 + schedule_delayed_work(&idtcm->extts_work, 2253 + msecs_to_jiffies(EXTTS_PERIOD_MS)); 2254 + mutex_unlock(idtcm->lock); 2282 2255 } 2283 2256 2284 2257 static void ptp_clock_unregister_all(struct idtcm *idtcm) ··· 2343 2222 static void set_default_masks(struct idtcm *idtcm) 2344 2223 { 2345 2224 idtcm->tod_mask = DEFAULT_TOD_MASK; 2225 + idtcm->extts_mask = 0; 2346 2226 2347 2227 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL; 2348 2228 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL; ··· 2356 2234 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; 2357 2235 } 2358 2236 2359 - static int idtcm_probe(struct i2c_client *client, 2360 - const struct i2c_device_id *id) 2237 + static int idtcm_probe(struct platform_device *pdev) 2361 2238 { 2239 + struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent); 2362 2240 struct idtcm *idtcm; 2363 2241 int err; 2364 2242 u8 i; 2365 2243 2366 - /* Unused for now */ 2367 - (void)id; 2368 - 2369 - idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); 2244 + idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL); 2370 2245 2371 2246 if (!idtcm) 2372 2247 return -ENOMEM; 2373 2248 2374 - idtcm->client = client; 2375 - idtcm->page_offset = 0xff; 2249 + idtcm->dev = &pdev->dev; 2250 + idtcm->mfd = pdev->dev.parent; 2251 + idtcm->lock = &ddata->lock; 2252 + idtcm->regmap = ddata->regmap; 2376 2253 idtcm->calculate_overhead_flag = 0; 2254 + 2255 + INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check); 2377 2256 2378 2257 set_default_masks(idtcm); 2379 2258 2380 - mutex_init(&idtcm->reg_lock); 2381 - mutex_lock(&idtcm->reg_lock); 2259 + mutex_lock(idtcm->lock); 2382 2260 2383 2261 idtcm_set_version_info(idtcm); 2384 2262 2385 - err = idtcm_load_firmware(idtcm, &client->dev); 2263 + err = idtcm_load_firmware(idtcm, &pdev->dev); 2264 + 2386 2265 if (err) 2387 - dev_warn(&idtcm->client->dev, "loading firmware failed with %d", err); 2266 + dev_warn(idtcm->dev, "loading firmware failed with %d", err); 2388 2267 2389 2268 wait_for_chip_ready(idtcm); 2390 2269 2391 2270 if (idtcm->tod_mask) { 2392 2271 for (i = 0; i < MAX_TOD; i++) { 2393 - if (idtcm->tod_mask & (1 << i)) { 2272 + if (idtcm->tod_mask & (1 << i)) 2394 2273 err = idtcm_enable_channel(idtcm, i); 2395 - if (err) { 2396 - dev_err(&idtcm->client->dev, 2397 - "idtcm_enable_channel %d failed!", i); 2398 - break; 2399 - } 2274 + else 2275 + err = idtcm_enable_extts_channel(idtcm, i); 2276 + if (err) { 2277 + dev_err(idtcm->dev, 2278 + "idtcm_enable_channel %d failed!", i); 2279 + break; 2400 2280 } 2401 2281 } 2402 2282 } else { 2403 - dev_err(&idtcm->client->dev, 2283 + dev_err(idtcm->dev, 2404 2284 "no PLLs flagged as PHCs, nothing to do"); 2405 2285 err = -ENODEV; 2406 2286 } 2407 2287 2408 - mutex_unlock(&idtcm->reg_lock); 2288 + mutex_unlock(idtcm->lock); 2409 2289 2410 2290 if (err) { 2411 2291 ptp_clock_unregister_all(idtcm); 2412 2292 return err; 2413 2293 } 2414 2294 2415 - i2c_set_clientdata(client, idtcm); 2295 + platform_set_drvdata(pdev, idtcm); 2416 2296 2417 2297 return 0; 2418 2298 } 2419 2299 2420 - static int idtcm_remove(struct i2c_client *client) 2300 + static int idtcm_remove(struct platform_device *pdev) 2421 2301 { 2422 - struct idtcm *idtcm = i2c_get_clientdata(client); 2302 + struct idtcm *idtcm = platform_get_drvdata(pdev); 2423 2303 2424 2304 ptp_clock_unregister_all(idtcm); 2425 2305 2426 - mutex_destroy(&idtcm->reg_lock); 2306 + cancel_delayed_work_sync(&idtcm->extts_work); 2427 2307 2428 2308 return 0; 2429 2309 } 2430 2310 2431 - #ifdef CONFIG_OF 2432 - static const struct of_device_id idtcm_dt_id[] = { 2433 - { .compatible = "idt,8a34000" }, 2434 - { .compatible = "idt,8a34001" }, 2435 - { .compatible = "idt,8a34002" }, 2436 - { .compatible = "idt,8a34003" }, 2437 - { .compatible = "idt,8a34004" }, 2438 - { .compatible = "idt,8a34005" }, 2439 - { .compatible = "idt,8a34006" }, 2440 - { .compatible = "idt,8a34007" }, 2441 - { .compatible = "idt,8a34008" }, 2442 - { .compatible = "idt,8a34009" }, 2443 - { .compatible = "idt,8a34010" }, 2444 - { .compatible = "idt,8a34011" }, 2445 - { .compatible = "idt,8a34012" }, 2446 - { .compatible = "idt,8a34013" }, 2447 - { .compatible = "idt,8a34014" }, 2448 - { .compatible = "idt,8a34015" }, 2449 - { .compatible = "idt,8a34016" }, 2450 - { .compatible = "idt,8a34017" }, 2451 - { .compatible = "idt,8a34018" }, 2452 - { .compatible = "idt,8a34019" }, 2453 - { .compatible = "idt,8a34040" }, 2454 - { .compatible = "idt,8a34041" }, 2455 - { .compatible = "idt,8a34042" }, 2456 - { .compatible = "idt,8a34043" }, 2457 - { .compatible = "idt,8a34044" }, 2458 - { .compatible = "idt,8a34045" }, 2459 - { .compatible = "idt,8a34046" }, 2460 - { .compatible = "idt,8a34047" }, 2461 - { .compatible = "idt,8a34048" }, 2462 - { .compatible = "idt,8a34049" }, 2463 - {}, 2464 - }; 2465 - MODULE_DEVICE_TABLE(of, idtcm_dt_id); 2466 - #endif 2467 - 2468 - static const struct i2c_device_id idtcm_i2c_id[] = { 2469 - { "8a34000" }, 2470 - { "8a34001" }, 2471 - { "8a34002" }, 2472 - { "8a34003" }, 2473 - { "8a34004" }, 2474 - { "8a34005" }, 2475 - { "8a34006" }, 2476 - { "8a34007" }, 2477 - { "8a34008" }, 2478 - { "8a34009" }, 2479 - { "8a34010" }, 2480 - { "8a34011" }, 2481 - { "8a34012" }, 2482 - { "8a34013" }, 2483 - { "8a34014" }, 2484 - { "8a34015" }, 2485 - { "8a34016" }, 2486 - { "8a34017" }, 2487 - { "8a34018" }, 2488 - { "8a34019" }, 2489 - { "8a34040" }, 2490 - { "8a34041" }, 2491 - { "8a34042" }, 2492 - { "8a34043" }, 2493 - { "8a34044" }, 2494 - { "8a34045" }, 2495 - { "8a34046" }, 2496 - { "8a34047" }, 2497 - { "8a34048" }, 2498 - { "8a34049" }, 2499 - {}, 2500 - }; 2501 - MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); 2502 - 2503 - static struct i2c_driver idtcm_driver = { 2311 + static struct platform_driver idtcm_driver = { 2504 2312 .driver = { 2505 - .of_match_table = of_match_ptr(idtcm_dt_id), 2506 - .name = "idtcm", 2313 + .name = "8a3400x-phc", 2507 2314 }, 2508 - .probe = idtcm_probe, 2509 - .remove = idtcm_remove, 2510 - .id_table = idtcm_i2c_id, 2315 + .probe = idtcm_probe, 2316 + .remove = idtcm_remove, 2511 2317 }; 2512 2318 2513 - module_i2c_driver(idtcm_driver); 2319 + module_platform_driver(idtcm_driver);
+20 -97
drivers/ptp/ptp_clockmatrix.h
··· 9 9 #define PTP_IDTCLOCKMATRIX_H 10 10 11 11 #include <linux/ktime.h> 12 - 13 - #include "idt8a340_reg.h" 12 + #include <linux/mfd/idt8a340_reg.h> 13 + #include <linux/regmap.h> 14 14 15 15 #define FW_FILENAME "idtcm.bin" 16 16 #define MAX_TOD (4) ··· 44 44 #define DEFAULT_TOD2_PTP_PLL (2) 45 45 #define DEFAULT_TOD3_PTP_PLL (3) 46 46 47 - #define POST_SM_RESET_DELAY_MS (3000) 48 47 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) 49 48 #define PHASE_PULL_IN_THRESHOLD_NS (15000) 50 49 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) ··· 63 64 * Return register address based on passed in firmware version 64 65 */ 65 66 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) 67 + enum fw_version { 68 + V_DEFAULT = 0, 69 + V487 = 1, 70 + V520 = 2, 71 + }; 66 72 67 73 /* PTP PLL Mode */ 68 74 enum ptp_pll_mode { ··· 76 72 PTP_PLL_MODE_WRITE_PHASE, 77 73 PTP_PLL_MODE_UNSUPPORTED, 78 74 PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED, 79 - }; 80 - 81 - /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 82 - enum pll_mode { 83 - PLL_MODE_MIN = 0, 84 - PLL_MODE_PLL = PLL_MODE_MIN, 85 - PLL_MODE_WRITE_PHASE = 1, 86 - PLL_MODE_WRITE_FREQUENCY = 2, 87 - PLL_MODE_GPIO_INC_DEC = 3, 88 - PLL_MODE_SYNTHESIS = 4, 89 - PLL_MODE_PHASE_MEASUREMENT = 5, 90 - PLL_MODE_DISABLED = 6, 91 - PLL_MODE_MAX = PLL_MODE_DISABLED, 92 - }; 93 - 94 - /* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */ 95 - enum manual_reference { 96 - MANU_REF_MIN = 0, 97 - MANU_REF_CLK0 = MANU_REF_MIN, 98 - MANU_REF_CLK1, 99 - MANU_REF_CLK2, 100 - MANU_REF_CLK3, 101 - MANU_REF_CLK4, 102 - MANU_REF_CLK5, 103 - MANU_REF_CLK6, 104 - MANU_REF_CLK7, 105 - MANU_REF_CLK8, 106 - MANU_REF_CLK9, 107 - MANU_REF_CLK10, 108 - MANU_REF_CLK11, 109 - MANU_REF_CLK12, 110 - MANU_REF_CLK13, 111 - MANU_REF_CLK14, 112 - MANU_REF_CLK15, 113 - MANU_REF_WRITE_PHASE, 114 - MANU_REF_WRITE_FREQUENCY, 115 - MANU_REF_XO_DPLL, 116 - MANU_REF_MAX = MANU_REF_XO_DPLL, 117 - }; 118 - 119 - enum hw_tod_write_trig_sel { 120 - HW_TOD_WR_TRIG_SEL_MIN = 0, 121 - HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN, 122 - HW_TOD_WR_TRIG_SEL_RESERVED = 1, 123 - HW_TOD_WR_TRIG_SEL_TOD_PPS = 2, 124 - HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3, 125 - HW_TOD_WR_TRIG_SEL_PWM_PPS = 4, 126 - HW_TOD_WR_TRIG_SEL_GPIO = 5, 127 - HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6, 128 - WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC, 129 - }; 130 - 131 - /* 4.8.7 only */ 132 - enum scsr_tod_write_trig_sel { 133 - SCSR_TOD_WR_TRIG_SEL_DISABLE = 0, 134 - SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1, 135 - SCSR_TOD_WR_TRIG_SEL_REFCLK = 2, 136 - SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3, 137 - SCSR_TOD_WR_TRIG_SEL_TODPPS = 4, 138 - SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5, 139 - SCSR_TOD_WR_TRIG_SEL_GPIO = 6, 140 - SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO, 141 - }; 142 - 143 - /* 4.8.7 only */ 144 - enum scsr_tod_write_type_sel { 145 - SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0, 146 - SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1, 147 - SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, 148 - SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, 149 - }; 150 - 151 - /* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */ 152 - enum dpll_state { 153 - DPLL_STATE_MIN = 0, 154 - DPLL_STATE_FREERUN = DPLL_STATE_MIN, 155 - DPLL_STATE_LOCKACQ = 1, 156 - DPLL_STATE_LOCKREC = 2, 157 - DPLL_STATE_LOCKED = 3, 158 - DPLL_STATE_HOLDOVER = 4, 159 - DPLL_STATE_OPEN_LOOP = 5, 160 - DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, 161 - }; 162 - 163 - enum fw_version { 164 - V_DEFAULT = 0, 165 - V487 = 1, 166 - V520 = 2, 167 75 }; 168 76 169 77 struct idtcm; ··· 101 185 s32 offset_ns, u32 max_ffo_ppb); 102 186 s32 current_freq_scaled_ppm; 103 187 bool phase_pull_in; 188 + u32 dco_delay; 189 + /* last input trigger for extts */ 190 + u8 refn; 104 191 u8 pll; 105 192 u16 output_mask; 106 193 }; 107 194 108 195 struct idtcm { 109 196 struct idtcm_channel channel[MAX_TOD]; 110 - struct i2c_client *client; 111 - u8 page_offset; 197 + struct device *dev; 112 198 u8 tod_mask; 113 199 char version[16]; 114 200 enum fw_version fw_ver; 115 - 201 + /* Polls for external time stamps */ 202 + u8 extts_mask; 203 + struct delayed_work extts_work; 204 + /* Remember the ptp channel to report extts */ 205 + struct idtcm_channel *event_channel[MAX_TOD]; 206 + /* Mutex to protect operations from being interrupted */ 207 + struct mutex *lock; 208 + struct device *mfd; 209 + struct regmap *regmap; 116 210 /* Overhead calculation for adjtime */ 117 211 u8 calculate_overhead_flag; 118 212 s64 tod_write_overhead_ns; 119 213 ktime_t start_time; 120 - 121 - /* Protects I2C read/modify/write registers from concurrent access */ 122 - struct mutex reg_lock; 123 214 }; 124 215 125 216 struct idtcm_fwrc {
+30 -1
include/linux/mfd/idt8a340_reg.h
··· 506 506 #define STATE_MODE_SHIFT (0) 507 507 #define STATE_MODE_MASK (0x7) 508 508 509 + /* Bit definitions for the DPLL_MANU_REF_CFG register */ 510 + #define MANUAL_REFERENCE_SHIFT (0) 511 + #define MANUAL_REFERENCE_MASK (0x1f) 512 + 509 513 /* Bit definitions for the GPIO_CFG_GBL register */ 510 514 #define SUPPLY_MODE_SHIFT (0) 511 515 #define SUPPLY_MODE_MASK (0x3) ··· 658 654 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ 659 655 enum pll_mode { 660 656 PLL_MODE_MIN = 0, 661 - PLL_MODE_NORMAL = PLL_MODE_MIN, 657 + PLL_MODE_PLL = PLL_MODE_MIN, 662 658 PLL_MODE_WRITE_PHASE = 1, 663 659 PLL_MODE_WRITE_FREQUENCY = 2, 664 660 PLL_MODE_GPIO_INC_DEC = 3, ··· 666 662 PLL_MODE_PHASE_MEASUREMENT = 5, 667 663 PLL_MODE_DISABLED = 6, 668 664 PLL_MODE_MAX = PLL_MODE_DISABLED, 665 + }; 666 + 667 + /* Values of DPLL_CTRL_n.DPLL_MANU_REF_CFG.MANUAL_REFERENCE */ 668 + enum manual_reference { 669 + MANU_REF_MIN = 0, 670 + MANU_REF_CLK0 = MANU_REF_MIN, 671 + MANU_REF_CLK1, 672 + MANU_REF_CLK2, 673 + MANU_REF_CLK3, 674 + MANU_REF_CLK4, 675 + MANU_REF_CLK5, 676 + MANU_REF_CLK6, 677 + MANU_REF_CLK7, 678 + MANU_REF_CLK8, 679 + MANU_REF_CLK9, 680 + MANU_REF_CLK10, 681 + MANU_REF_CLK11, 682 + MANU_REF_CLK12, 683 + MANU_REF_CLK13, 684 + MANU_REF_CLK14, 685 + MANU_REF_CLK15, 686 + MANU_REF_WRITE_PHASE, 687 + MANU_REF_WRITE_FREQUENCY, 688 + MANU_REF_XO_DPLL, 689 + MANU_REF_MAX = MANU_REF_XO_DPLL, 669 690 }; 670 691 671 692 enum hw_tod_write_trig_sel {