tjh.dev
+2
Documentation/arm64/silicon-errata.rst
+2
Documentation/arm64/silicon-errata.rst
···
110
110
+----------------+-----------------+-----------------+-----------------------------+
111
111
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
112
112
+----------------+-----------------+-----------------+-----------------------------+
113
+
| Cavium | ThunderX GICv3 | #38539 | N/A |
114
+
+----------------+-----------------+-----------------+-----------------------------+
113
115
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
114
116
+----------------+-----------------+-----------------+-----------------------------+
115
117
| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
+29
-1
drivers/irqchip/irq-gic-v3.c
+29
-1
drivers/irqchip/irq-gic-v3.c
···
34
34
#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
35
35
36
36
#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
37
+
#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
37
38
38
39
struct redist_region {
39
40
void __iomem *redist_base;
···
1465
1464
return true;
1466
1465
}
1467
1466
1467
+
static bool gic_enable_quirk_cavium_38539(void *data)
1468
+
{
1469
+
struct gic_chip_data *d = data;
1470
+
1471
+
d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1472
+
1473
+
return true;
1474
+
}
1475
+
1468
1476
static bool gic_enable_quirk_hip06_07(void *data)
1469
1477
{
1470
1478
struct gic_chip_data *d = data;
···
1511
1501
.iidr = 0x00000000,
1512
1502
.mask = 0xffffffff,
1513
1503
.init = gic_enable_quirk_hip06_07,
1504
+
},
1505
+
{
1506
+
/*
1507
+
* Reserved register accesses generate a Synchronous
1508
+
* External Abort. This erratum applies to:
1509
+
* - ThunderX: CN88xx
1510
+
* - OCTEON TX: CN83xx, CN81xx
1511
+
* - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1512
+
*/
1513
+
.desc = "GICv3: Cavium erratum 38539",
1514
+
.iidr = 0xa000034c,
1515
+
.mask = 0xe8f00fff,
1516
+
.init = gic_enable_quirk_cavium_38539,
1514
1517
},
1515
1518
{
1516
1519
}
···
1600
1577
pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1601
1578
pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1602
1579
1603
-
gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1580
+
/*
1581
+
* ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1582
+
* architecture spec (which says that reserved registers are RES0).
1583
+
*/
1584
+
if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1585
+
gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1604
1586
1605
1587
gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1606
1588
&gic_data);