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dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding

Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>

authored by

CK Hu and committed by
Philipp Zabel
923dd88d cb1b5dff

+298
+203
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
··· 1 + Mediatek display subsystem 2 + ========================== 3 + 4 + The Mediatek display subsystem consists of various DISP function blocks in the 5 + MMSYS register space. The connections between them can be configured by output 6 + and input selectors in the MMSYS_CONFIG register space. Pixel clock and start 7 + of frame signal are distributed to the other function blocks by a DISP_MUTEX 8 + function block. 9 + 10 + All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. 11 + For a description of the MMSYS_CONFIG binding, see 12 + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. 13 + 14 + DISP function blocks 15 + ==================== 16 + 17 + A display stream starts at a source function block that reads pixel data from 18 + memory and ends with a sink function block that drives pixels on a display 19 + interface, or writes pixels back to memory. All DISP function blocks have 20 + their own register space, interrupt, and clock gate. The blocks that can 21 + access memory additionally have to list the IOMMU and local arbiter they are 22 + connected to. 23 + 24 + For a description of the display interface sink function blocks, see 25 + Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and 26 + Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. 27 + 28 + Required properties (all function blocks): 29 + - compatible: "mediatek,<chip>-disp-<function>", one of 30 + "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 + "mediatek,<chip>-disp-rdma" - read DMA / line buffer 32 + "mediatek,<chip>-disp-wdma" - write DMA 33 + "mediatek,<chip>-disp-color" - color processor 34 + "mediatek,<chip>-disp-aal" - adaptive ambient light controller 35 + "mediatek,<chip>-disp-gamma" - gamma correction 36 + "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources 37 + "mediatek,<chip>-disp-split" - split stream to two encoders 38 + "mediatek,<chip>-disp-ufoe" - data compression engine 39 + "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt 40 + "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt 41 + "mediatek,<chip>-disp-mutex" - display mutex 42 + "mediatek,<chip>-disp-od" - overdrive 43 + - reg: Physical base address and length of the function block register space 44 + - interrupts: The interrupt signal from the function block (required, except for 45 + merge and split function blocks). 46 + - clocks: device clocks 47 + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 48 + For most function blocks this is just a single clock input. Only the DSI and 49 + DPI controller nodes have multiple clock inputs. These are documented in 50 + mediatek,dsi.txt and mediatek,dpi.txt, respectively. 51 + 52 + Required properties (DMA function blocks): 53 + - compatible: Should be one of 54 + "mediatek,<chip>-disp-ovl" 55 + "mediatek,<chip>-disp-rdma" 56 + "mediatek,<chip>-disp-wdma" 57 + - larb: Should contain a phandle pointing to the local arbiter device as defined 58 + in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt 59 + - iommus: Should point to the respective IOMMU block with master port as 60 + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt 61 + for details. 62 + 63 + Examples: 64 + 65 + mmsys: clock-controller@14000000 { 66 + compatible = "mediatek,mt8173-mmsys", "syscon"; 67 + reg = <0 0x14000000 0 0x1000>; 68 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 69 + #clock-cells = <1>; 70 + }; 71 + 72 + ovl0: ovl@1400c000 { 73 + compatible = "mediatek,mt8173-disp-ovl"; 74 + reg = <0 0x1400c000 0 0x1000>; 75 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 76 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 77 + clocks = <&mmsys CLK_MM_DISP_OVL0>; 78 + iommus = <&iommu M4U_PORT_DISP_OVL0>; 79 + mediatek,larb = <&larb0>; 80 + }; 81 + 82 + ovl1: ovl@1400d000 { 83 + compatible = "mediatek,mt8173-disp-ovl"; 84 + reg = <0 0x1400d000 0 0x1000>; 85 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 86 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 87 + clocks = <&mmsys CLK_MM_DISP_OVL1>; 88 + iommus = <&iommu M4U_PORT_DISP_OVL1>; 89 + mediatek,larb = <&larb4>; 90 + }; 91 + 92 + rdma0: rdma@1400e000 { 93 + compatible = "mediatek,mt8173-disp-rdma"; 94 + reg = <0 0x1400e000 0 0x1000>; 95 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 96 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97 + clocks = <&mmsys CLK_MM_DISP_RDMA0>; 98 + iommus = <&iommu M4U_PORT_DISP_RDMA0>; 99 + mediatek,larb = <&larb0>; 100 + }; 101 + 102 + rdma1: rdma@1400f000 { 103 + compatible = "mediatek,mt8173-disp-rdma"; 104 + reg = <0 0x1400f000 0 0x1000>; 105 + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 106 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 107 + clocks = <&mmsys CLK_MM_DISP_RDMA1>; 108 + iommus = <&iommu M4U_PORT_DISP_RDMA1>; 109 + mediatek,larb = <&larb4>; 110 + }; 111 + 112 + rdma2: rdma@14010000 { 113 + compatible = "mediatek,mt8173-disp-rdma"; 114 + reg = <0 0x14010000 0 0x1000>; 115 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 116 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 117 + clocks = <&mmsys CLK_MM_DISP_RDMA2>; 118 + iommus = <&iommu M4U_PORT_DISP_RDMA2>; 119 + mediatek,larb = <&larb4>; 120 + }; 121 + 122 + wdma0: wdma@14011000 { 123 + compatible = "mediatek,mt8173-disp-wdma"; 124 + reg = <0 0x14011000 0 0x1000>; 125 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 126 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 127 + clocks = <&mmsys CLK_MM_DISP_WDMA0>; 128 + iommus = <&iommu M4U_PORT_DISP_WDMA0>; 129 + mediatek,larb = <&larb0>; 130 + }; 131 + 132 + wdma1: wdma@14012000 { 133 + compatible = "mediatek,mt8173-disp-wdma"; 134 + reg = <0 0x14012000 0 0x1000>; 135 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 136 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 137 + clocks = <&mmsys CLK_MM_DISP_WDMA1>; 138 + iommus = <&iommu M4U_PORT_DISP_WDMA1>; 139 + mediatek,larb = <&larb4>; 140 + }; 141 + 142 + color0: color@14013000 { 143 + compatible = "mediatek,mt8173-disp-color"; 144 + reg = <0 0x14013000 0 0x1000>; 145 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 146 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 147 + clocks = <&mmsys CLK_MM_DISP_COLOR0>; 148 + }; 149 + 150 + color1: color@14014000 { 151 + compatible = "mediatek,mt8173-disp-color"; 152 + reg = <0 0x14014000 0 0x1000>; 153 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 154 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 155 + clocks = <&mmsys CLK_MM_DISP_COLOR1>; 156 + }; 157 + 158 + aal@14015000 { 159 + compatible = "mediatek,mt8173-disp-aal"; 160 + reg = <0 0x14015000 0 0x1000>; 161 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 162 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 163 + clocks = <&mmsys CLK_MM_DISP_AAL>; 164 + }; 165 + 166 + gamma@14016000 { 167 + compatible = "mediatek,mt8173-disp-gamma"; 168 + reg = <0 0x14016000 0 0x1000>; 169 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 170 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 171 + clocks = <&mmsys CLK_MM_DISP_GAMMA>; 172 + }; 173 + 174 + ufoe@1401a000 { 175 + compatible = "mediatek,mt8173-disp-ufoe"; 176 + reg = <0 0x1401a000 0 0x1000>; 177 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 178 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 179 + clocks = <&mmsys CLK_MM_DISP_UFOE>; 180 + }; 181 + 182 + dsi0: dsi@1401b000 { 183 + /* See mediatek,dsi.txt for details */ 184 + }; 185 + 186 + dpi0: dpi@1401d000 { 187 + /* See mediatek,dpi.txt for details */ 188 + }; 189 + 190 + mutex: mutex@14020000 { 191 + compatible = "mediatek,mt8173-disp-mutex"; 192 + reg = <0 0x14020000 0 0x1000>; 193 + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 194 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 195 + clocks = <&mmsys CLK_MM_MUTEX_32K>; 196 + }; 197 + 198 + od@14023000 { 199 + compatible = "mediatek,mt8173-disp-od"; 200 + reg = <0 0x14023000 0 0x1000>; 201 + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 202 + clocks = <&mmsys CLK_MM_DISP_OD>; 203 + };
+35
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
··· 1 + Mediatek DPI Device 2 + =================== 3 + 4 + The Mediatek DPI function block is a sink of the display subsystem and 5 + provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel 6 + output bus. 7 + 8 + Required properties: 9 + - compatible: "mediatek,<chip>-dpi" 10 + - reg: Physical base address and length of the controller's registers 11 + - interrupts: The interrupt signal from the function block. 12 + - clocks: device clocks 13 + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 14 + - clock-names: must contain "pixel", "engine", and "pll" 15 + - port: Output port node with endpoint definitions as described in 16 + Documentation/devicetree/bindings/graph.txt. This port should be connected 17 + to the input port of an attached HDMI or LVDS encoder chip. 18 + 19 + Example: 20 + 21 + dpi0: dpi@1401d000 { 22 + compatible = "mediatek,mt8173-dpi"; 23 + reg = <0 0x1401d000 0 0x1000>; 24 + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 25 + clocks = <&mmsys CLK_MM_DPI_PIXEL>, 26 + <&mmsys CLK_MM_DPI_ENGINE>, 27 + <&apmixedsys CLK_APMIXED_TVDPLL>; 28 + clock-names = "pixel", "engine", "pll"; 29 + 30 + port { 31 + dpi0_out: endpoint { 32 + remote-endpoint = <&hdmi0_in>; 33 + }; 34 + }; 35 + };
+60
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
··· 1 + Mediatek DSI Device 2 + =================== 3 + 4 + The Mediatek DSI function block is a sink of the display subsystem and can 5 + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 6 + channel output. 7 + 8 + Required properties: 9 + - compatible: "mediatek,<chip>-dsi" 10 + - reg: Physical base address and length of the controller's registers 11 + - interrupts: The interrupt signal from the function block. 12 + - clocks: device clocks 13 + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 14 + - clock-names: must contain "engine", "digital", and "hs" 15 + - phys: phandle link to the MIPI D-PHY controller. 16 + - phy-names: must contain "dphy" 17 + - port: Output port node with endpoint definitions as described in 18 + Documentation/devicetree/bindings/graph.txt. This port should be connected 19 + to the input port of an attached DSI panel or DSI-to-eDP encoder chip. 20 + 21 + MIPI TX Configuration Module 22 + ============================ 23 + 24 + The MIPI TX configuration module controls the MIPI D-PHY. 25 + 26 + Required properties: 27 + - compatible: "mediatek,<chip>-mipi-tx" 28 + - reg: Physical base address and length of the controller's registers 29 + - clocks: PLL reference clock 30 + - clock-output-names: name of the output clock line to the DSI encoder 31 + - #clock-cells: must be <0>; 32 + - #phy-cells: must be <0>. 33 + 34 + Example: 35 + 36 + mipi_tx0: mipi-dphy@10215000 { 37 + compatible = "mediatek,mt8173-mipi-tx"; 38 + reg = <0 0x10215000 0 0x1000>; 39 + clocks = <&clk26m>; 40 + clock-output-names = "mipi_tx0_pll"; 41 + #clock-cells = <0>; 42 + #phy-cells = <0>; 43 + }; 44 + 45 + dsi0: dsi@1401b000 { 46 + compatible = "mediatek,mt8173-dsi"; 47 + reg = <0 0x1401b000 0 0x1000>; 48 + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 49 + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, 50 + <&mipi_tx0>; 51 + clock-names = "engine", "digital", "hs"; 52 + phys = <&mipi_tx0>; 53 + phy-names = "dphy"; 54 + 55 + port { 56 + dsi0_out: endpoint { 57 + remote-endpoint = <&panel_in>; 58 + }; 59 + }; 60 + };