tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"The dmaengine subsystem updates for this cycle consist of a new driver
(Microchip) along with couple of yaml binding conversions, core api
updates and bunch of driver updates etc.
New HW support:
- Microchip sama7d65 dma controller
- Yaml conversion of atmel dma binding and Freescale Elo DMA
Controller binding
Core:
- Remove device_prep_dma_imm_data() API as users are removed
- Reduce scope of some less frequently used DMA request channel APIs
with aim to cleanup these in future
Updates:
- Drop Fenghua Yu from idxd maintainers, as he changed jobs
- AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs
removal"
* tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (29 commits)
dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality
dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number
dmaengine: ae4dma: Remove deprecated PCI IDs
dmaengine: Remove device_prep_dma_imm_data from struct dma_device
dmaengine: ti: edma: support sw triggered chans in of_edma_xlate()
dmaengine: ti: k3-udma: Enable second resource range for BCDMA and PKTDMA
dmaengine: fsl-edma: free irq correctly in remove path
dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister
dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
dmaengine: dmatest: Fix dmatest waiting less when interrupted
dt-bindings: dma: Convert fsl,elo*-dma to YAML
dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
dmaengine: Fix typo in comment
dmaengine: ti: k3-udma-glue: Drop skip_fdq argument from k3_udma_glue_reset_rx_chn
dmaengine: bcm2835-dma: fix warning when CONFIG_PM=n
dt-bindings: dma: fsl,edma: Add i.MX94 support
dt-bindings: dma: atmel: add microchip,sama7d65-dma
dmaengine: img-mdc: remove incorrect of_match_ptr annotation
dmaengine: idxd: Delete unnecessary NULL check
dmaengine: pxa: Enable compile test
...
+682
-319
+68
Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml
+68
Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Atmel Direct Memory Access Controller (DMA)
8
+
9
+
maintainers:
10
+
- Ludovic Desroches <ludovic.desroches@microchip.com>
11
+
12
+
description:
13
+
The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
14
+
peripheral to a destination peripheral over one or more AMBA buses. One channel
15
+
is required for each source/destination pair. In the most basic configuration,
16
+
the DMAC has one master interface and one channel. The master interface reads
17
+
the data from a source and writes it to a destination. Two AMBA transfers are
18
+
required for each DMAC data transfer. This is also known as a dual-access transfer.
19
+
The DMAC is programmed via the APB interface.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- atmel,at91sam9g45-dma
25
+
- atmel,at91sam9rl-dma
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
"#dma-cells":
34
+
description:
35
+
Must be <2>, used to represent the number of integer cells in the dma
36
+
property of client devices. The two cells in order are
37
+
1. The first cell represents the channel number.
38
+
2. The second cell is 0 for RX and 1 for TX transfers.
39
+
const: 2
40
+
41
+
clocks:
42
+
maxItems: 1
43
+
44
+
clock-names:
45
+
const: dma_clk
46
+
47
+
required:
48
+
- compatible
49
+
- reg
50
+
- interrupts
51
+
- "#dma-cells"
52
+
- clocks
53
+
- clock-names
54
+
55
+
additionalProperties: false
56
+
57
+
examples:
58
+
- |
59
+
dma-controller@ffffec00 {
60
+
compatible = "atmel,at91sam9g45-dma";
61
+
reg = <0xffffec00 0x200>;
62
+
interrupts = <21>;
63
+
#dma-cells = <2>;
64
+
clocks = <&pmc 2 20>;
65
+
clock-names = "dma_clk";
66
+
};
67
+
68
+
...
+3
Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml
+3
Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml
-42
Documentation/devicetree/bindings/dma/atmel-dma.txt
-42
Documentation/devicetree/bindings/dma/atmel-dma.txt
···
1
-
* Atmel Direct Memory Access Controller (DMA)
2
-
3
-
Required properties:
4
-
- compatible: Should be "atmel,<chip>-dma".
5
-
- reg: Should contain DMA registers location and length.
6
-
- interrupts: Should contain DMA interrupt.
7
-
- #dma-cells: Must be <2>, used to represent the number of integer cells in
8
-
the dmas property of client devices.
9
-
10
-
Example:
11
-
12
-
dma0: dma@ffffec00 {
13
-
compatible = "atmel,at91sam9g45-dma";
14
-
reg = <0xffffec00 0x200>;
15
-
interrupts = <21>;
16
-
#dma-cells = <2>;
17
-
};
18
-
19
-
DMA clients connected to the Atmel DMA controller must use the format
20
-
described in the dma.txt file, using a three-cell specifier for each channel:
21
-
a phandle plus two integer cells.
22
-
The three cells in order are:
23
-
24
-
1. A phandle pointing to the DMA controller.
25
-
2. The memory interface (16 most significant bits), the peripheral interface
26
-
(16 less significant bits).
27
-
3. Parameters for the at91 DMA configuration register which are device
28
-
dependent:
29
-
- bit 7-0: peripheral identifier for the hardware handshaking interface. The
30
-
identifier can be different for tx and rx.
31
-
- bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
32
-
33
-
Example:
34
-
35
-
i2c0@i2c@f8010000 {
36
-
compatible = "atmel,at91sam9x5-i2c";
37
-
reg = <0xf8010000 0x100>;
38
-
interrupts = <9 4 6>;
39
-
dmas = <&dma0 1 7>,
40
-
<&dma0 1 8>;
41
-
dma-names = "tx", "rx";
42
-
};
+8
Documentation/devicetree/bindings/dma/fsl,edma.yaml
+8
Documentation/devicetree/bindings/dma/fsl,edma.yaml
···
28
28
- fsl,imx95-edma5
29
29
- nxp,s32g2-edma
30
30
- items:
31
+
- enum:
32
+
- fsl,imx94-edma3
33
+
- const: fsl,imx93-edma3
34
+
- items:
35
+
- enum:
36
+
- fsl,imx94-edma5
37
+
- const: fsl,imx95-edma5
38
+
- items:
31
39
- const: fsl,ls1028a-edma
32
40
- const: fsl,vf610-edma
33
41
- items:
+137
Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
+137
Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale Elo DMA Controller
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
description:
13
+
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
14
+
series chips such as mpc8315, mpc8349, mpc8379 etc.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- enum:
20
+
- fsl,mpc8313-dma
21
+
- fsl,mpc8315-dma
22
+
- fsl,mpc8323-dma
23
+
- fsl,mpc8347-dma
24
+
- fsl,mpc8349-dma
25
+
- fsl,mpc8360-dma
26
+
- fsl,mpc8377-dma
27
+
- fsl,mpc8378-dma
28
+
- fsl,mpc8379-dma
29
+
- const: fsl,elo-dma
30
+
31
+
reg:
32
+
items:
33
+
- description:
34
+
DMA General Status Register, i.e. DGSR which contains status for
35
+
all the 4 DMA channels.
36
+
37
+
cell-index:
38
+
$ref: /schemas/types.yaml#/definitions/uint32
39
+
description: Controller index. 0 for controller @ 0x8100.
40
+
41
+
ranges: true
42
+
43
+
"#address-cells":
44
+
const: 1
45
+
46
+
"#size-cells":
47
+
const: 1
48
+
49
+
interrupts:
50
+
maxItems: 1
51
+
description: Controller interrupt.
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
57
+
patternProperties:
58
+
"^dma-channel@[0-9a-f]+$":
59
+
type: object
60
+
additionalProperties: false
61
+
62
+
properties:
63
+
compatible:
64
+
oneOf:
65
+
# native DMA channel
66
+
- items:
67
+
- enum:
68
+
- fsl,mpc8315-dma-channel
69
+
- fsl,mpc8323-dma-channel
70
+
- fsl,mpc8347-dma-channel
71
+
- fsl,mpc8349-dma-channel
72
+
- fsl,mpc8360-dma-channel
73
+
- fsl,mpc8377-dma-channel
74
+
- fsl,mpc8378-dma-channel
75
+
- fsl,mpc8379-dma-channel
76
+
- const: fsl,elo-dma-channel
77
+
78
+
# audio DMA channel, see fsl,ssi.yaml
79
+
- const: fsl,ssi-dma-channel
80
+
81
+
reg:
82
+
maxItems: 1
83
+
84
+
cell-index:
85
+
description: DMA channel index starts at 0.
86
+
87
+
interrupts:
88
+
maxItems: 1
89
+
description:
90
+
Per-channel interrupt. Only necessary if no controller interrupt has
91
+
been provided.
92
+
93
+
additionalProperties: false
94
+
95
+
examples:
96
+
- |
97
+
#include <dt-bindings/interrupt-controller/irq.h>
98
+
99
+
dma@82a8 {
100
+
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
101
+
reg = <0x82a8 4>;
102
+
#address-cells = <1>;
103
+
#size-cells = <1>;
104
+
ranges = <0 0x8100 0x1a4>;
105
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
106
+
cell-index = <0>;
107
+
108
+
dma-channel@0 {
109
+
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
110
+
reg = <0 0x80>;
111
+
cell-index = <0>;
112
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
113
+
};
114
+
115
+
dma-channel@80 {
116
+
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
117
+
reg = <0x80 0x80>;
118
+
cell-index = <1>;
119
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
120
+
};
121
+
122
+
dma-channel@100 {
123
+
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
124
+
reg = <0x100 0x80>;
125
+
cell-index = <2>;
126
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
127
+
};
128
+
129
+
dma-channel@180 {
130
+
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
131
+
reg = <0x180 0x80>;
132
+
cell-index = <3>;
133
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
134
+
};
135
+
};
136
+
137
+
...
+125
Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
+125
Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale Elo3 DMA Controller
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
description:
13
+
DMA controller which has same function as EloPlus except that Elo3 has 8
14
+
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
15
+
series chips, such as t1040, t4240, b4860.
16
+
17
+
properties:
18
+
compatible:
19
+
const: fsl,elo3-dma
20
+
21
+
reg:
22
+
items:
23
+
- description:
24
+
DMA General Status Registers starting from DGSR0, for channel 1~4
25
+
- description:
26
+
DMA General Status Registers starting from DGSR1, for channel 5~8
27
+
28
+
ranges: true
29
+
30
+
"#address-cells":
31
+
const: 1
32
+
33
+
"#size-cells":
34
+
const: 1
35
+
36
+
interrupts:
37
+
maxItems: 1
38
+
39
+
patternProperties:
40
+
"^dma-channel@[0-9a-f]+$":
41
+
type: object
42
+
additionalProperties: false
43
+
44
+
properties:
45
+
compatible:
46
+
enum:
47
+
# native DMA channel
48
+
- fsl,eloplus-dma-channel
49
+
50
+
# audio DMA channel, see fsl,ssi.yaml
51
+
- fsl,ssi-dma-channel
52
+
53
+
reg:
54
+
maxItems: 1
55
+
56
+
interrupts:
57
+
maxItems: 1
58
+
description:
59
+
Per-channel interrupt. Only necessary if no controller interrupt has
60
+
been provided.
61
+
62
+
additionalProperties: false
63
+
64
+
examples:
65
+
- |
66
+
#include <dt-bindings/interrupt-controller/irq.h>
67
+
68
+
dma@100300 {
69
+
compatible = "fsl,elo3-dma";
70
+
reg = <0x100300 0x4>,
71
+
<0x100600 0x4>;
72
+
#address-cells = <1>;
73
+
#size-cells = <1>;
74
+
ranges = <0x0 0x100100 0x500>;
75
+
76
+
dma-channel@0 {
77
+
compatible = "fsl,eloplus-dma-channel";
78
+
reg = <0x0 0x80>;
79
+
interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
80
+
};
81
+
82
+
dma-channel@80 {
83
+
compatible = "fsl,eloplus-dma-channel";
84
+
reg = <0x80 0x80>;
85
+
interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
86
+
};
87
+
88
+
dma-channel@100 {
89
+
compatible = "fsl,eloplus-dma-channel";
90
+
reg = <0x100 0x80>;
91
+
interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
92
+
};
93
+
94
+
dma-channel@180 {
95
+
compatible = "fsl,eloplus-dma-channel";
96
+
reg = <0x180 0x80>;
97
+
interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
98
+
};
99
+
100
+
dma-channel@300 {
101
+
compatible = "fsl,eloplus-dma-channel";
102
+
reg = <0x300 0x80>;
103
+
interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
104
+
};
105
+
106
+
dma-channel@380 {
107
+
compatible = "fsl,eloplus-dma-channel";
108
+
reg = <0x380 0x80>;
109
+
interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
110
+
};
111
+
112
+
dma-channel@400 {
113
+
compatible = "fsl,eloplus-dma-channel";
114
+
reg = <0x400 0x80>;
115
+
interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
116
+
};
117
+
118
+
dma-channel@480 {
119
+
compatible = "fsl,eloplus-dma-channel";
120
+
reg = <0x480 0x80>;
121
+
interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
122
+
};
123
+
};
124
+
125
+
...
+132
Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
+132
Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale EloPlus DMA Controller
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
description:
13
+
This is a 4-channel DMA controller with extended addresses and chaining,
14
+
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
15
+
mpc8540, mpc8641 p4080, bsc9131 etc.
16
+
17
+
properties:
18
+
compatible:
19
+
oneOf:
20
+
- items:
21
+
- enum:
22
+
- fsl,mpc8540-dma
23
+
- fsl,mpc8541-dma
24
+
- fsl,mpc8548-dma
25
+
- fsl,mpc8555-dma
26
+
- fsl,mpc8560-dma
27
+
- fsl,mpc8572-dma
28
+
- fsl,mpc8641-dma
29
+
- const: fsl,eloplus-dma
30
+
- const: fsl,eloplus-dma
31
+
32
+
reg:
33
+
items:
34
+
- description:
35
+
DMA General Status Register, i.e. DGSR which contains
36
+
status for all the 4 DMA channels
37
+
38
+
cell-index:
39
+
$ref: /schemas/types.yaml#/definitions/uint32
40
+
description:
41
+
controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
42
+
43
+
ranges: true
44
+
45
+
"#address-cells":
46
+
const: 1
47
+
48
+
"#size-cells":
49
+
const: 1
50
+
51
+
interrupts:
52
+
maxItems: 1
53
+
description: Controller interrupt.
54
+
55
+
patternProperties:
56
+
"^dma-channel@[0-9a-f]+$":
57
+
type: object
58
+
additionalProperties: false
59
+
60
+
properties:
61
+
compatible:
62
+
oneOf:
63
+
# native DMA channel
64
+
- items:
65
+
- enum:
66
+
- fsl,mpc8540-dma-channel
67
+
- fsl,mpc8541-dma-channel
68
+
- fsl,mpc8548-dma-channel
69
+
- fsl,mpc8555-dma-channel
70
+
- fsl,mpc8560-dma-channel
71
+
- fsl,mpc8572-dma-channel
72
+
- const: fsl,eloplus-dma-channel
73
+
74
+
# audio DMA channel, see fsl,ssi.yaml
75
+
- const: fsl,ssi-dma-channel
76
+
77
+
reg:
78
+
maxItems: 1
79
+
80
+
cell-index:
81
+
description: DMA channel index starts at 0.
82
+
83
+
interrupts:
84
+
maxItems: 1
85
+
description:
86
+
Per-channel interrupt. Only necessary if no controller interrupt has
87
+
been provided.
88
+
89
+
additionalProperties: false
90
+
91
+
examples:
92
+
- |
93
+
#include <dt-bindings/interrupt-controller/irq.h>
94
+
95
+
dma@21300 {
96
+
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
97
+
reg = <0x21300 4>;
98
+
#address-cells = <1>;
99
+
#size-cells = <1>;
100
+
ranges = <0 0x21100 0x200>;
101
+
cell-index = <0>;
102
+
103
+
dma-channel@0 {
104
+
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
105
+
reg = <0 0x80>;
106
+
cell-index = <0>;
107
+
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
108
+
};
109
+
110
+
dma-channel@80 {
111
+
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
112
+
reg = <0x80 0x80>;
113
+
cell-index = <1>;
114
+
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
115
+
};
116
+
117
+
dma-channel@100 {
118
+
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
119
+
reg = <0x100 0x80>;
120
+
cell-index = <2>;
121
+
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
122
+
};
123
+
124
+
dma-channel@180 {
125
+
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
126
+
reg = <0x180 0x80>;
127
+
cell-index = <3>;
128
+
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
129
+
};
130
+
};
131
+
132
+
...
+6
Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml
+6
Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml
···
31
31
- fsl,imx6q-dma-apbh
32
32
- fsl,imx6sx-dma-apbh
33
33
- fsl,imx7d-dma-apbh
34
+
- fsl,imx8dxl-dma-apbh
35
+
- fsl,imx8mm-dma-apbh
36
+
- fsl,imx8mn-dma-apbh
37
+
- fsl,imx8mp-dma-apbh
38
+
- fsl,imx8mq-dma-apbh
39
+
- fsl,imx8qm-dma-apbh
34
40
- fsl,imx8qxp-dma-apbh
35
41
- const: fsl,imx28-dma-apbh
36
42
- enum:
+2
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+2
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
-204
Documentation/devicetree/bindings/powerpc/fsl/dma.txt
-204
Documentation/devicetree/bindings/powerpc/fsl/dma.txt
···
1
-
* Freescale DMA Controllers
2
-
3
-
** Freescale Elo DMA Controller
4
-
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
5
-
series chips such as mpc8315, mpc8349, mpc8379 etc.
6
-
7
-
Required properties:
8
-
9
-
- compatible : must include "fsl,elo-dma"
10
-
- reg : DMA General Status Register, i.e. DGSR which contains
11
-
status for all the 4 DMA channels
12
-
- ranges : describes the mapping between the address space of the
13
-
DMA channels and the address space of the DMA controller
14
-
- cell-index : controller index. 0 for controller @ 0x8100
15
-
- interrupts : interrupt specifier for DMA IRQ
16
-
17
-
- DMA channel nodes:
18
-
- compatible : must include "fsl,elo-dma-channel"
19
-
However, see note below.
20
-
- reg : DMA channel specific registers
21
-
- cell-index : DMA channel index starts at 0.
22
-
23
-
Optional properties:
24
-
- interrupts : interrupt specifier for DMA channel IRQ
25
-
(on 83xx this is expected to be identical to
26
-
the interrupts property of the parent node)
27
-
28
-
Example:
29
-
dma@82a8 {
30
-
#address-cells = <1>;
31
-
#size-cells = <1>;
32
-
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
33
-
reg = <0x82a8 4>;
34
-
ranges = <0 0x8100 0x1a4>;
35
-
interrupt-parent = <&ipic>;
36
-
interrupts = <71 8>;
37
-
cell-index = <0>;
38
-
dma-channel@0 {
39
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
40
-
cell-index = <0>;
41
-
reg = <0 0x80>;
42
-
interrupt-parent = <&ipic>;
43
-
interrupts = <71 8>;
44
-
};
45
-
dma-channel@80 {
46
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
47
-
cell-index = <1>;
48
-
reg = <0x80 0x80>;
49
-
interrupt-parent = <&ipic>;
50
-
interrupts = <71 8>;
51
-
};
52
-
dma-channel@100 {
53
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
54
-
cell-index = <2>;
55
-
reg = <0x100 0x80>;
56
-
interrupt-parent = <&ipic>;
57
-
interrupts = <71 8>;
58
-
};
59
-
dma-channel@180 {
60
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
61
-
cell-index = <3>;
62
-
reg = <0x180 0x80>;
63
-
interrupt-parent = <&ipic>;
64
-
interrupts = <71 8>;
65
-
};
66
-
};
67
-
68
-
** Freescale EloPlus DMA Controller
69
-
This is a 4-channel DMA controller with extended addresses and chaining,
70
-
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
71
-
mpc8540, mpc8641 p4080, bsc9131 etc.
72
-
73
-
Required properties:
74
-
75
-
- compatible : must include "fsl,eloplus-dma"
76
-
- reg : DMA General Status Register, i.e. DGSR which contains
77
-
status for all the 4 DMA channels
78
-
- cell-index : controller index. 0 for controller @ 0x21000,
79
-
1 for controller @ 0xc000
80
-
- ranges : describes the mapping between the address space of the
81
-
DMA channels and the address space of the DMA controller
82
-
83
-
- DMA channel nodes:
84
-
- compatible : must include "fsl,eloplus-dma-channel"
85
-
However, see note below.
86
-
- cell-index : DMA channel index starts at 0.
87
-
- reg : DMA channel specific registers
88
-
- interrupts : interrupt specifier for DMA channel IRQ
89
-
90
-
Example:
91
-
dma@21300 {
92
-
#address-cells = <1>;
93
-
#size-cells = <1>;
94
-
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
95
-
reg = <0x21300 4>;
96
-
ranges = <0 0x21100 0x200>;
97
-
cell-index = <0>;
98
-
dma-channel@0 {
99
-
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
100
-
reg = <0 0x80>;
101
-
cell-index = <0>;
102
-
interrupt-parent = <&mpic>;
103
-
interrupts = <20 2>;
104
-
};
105
-
dma-channel@80 {
106
-
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
107
-
reg = <0x80 0x80>;
108
-
cell-index = <1>;
109
-
interrupt-parent = <&mpic>;
110
-
interrupts = <21 2>;
111
-
};
112
-
dma-channel@100 {
113
-
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
114
-
reg = <0x100 0x80>;
115
-
cell-index = <2>;
116
-
interrupt-parent = <&mpic>;
117
-
interrupts = <22 2>;
118
-
};
119
-
dma-channel@180 {
120
-
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
121
-
reg = <0x180 0x80>;
122
-
cell-index = <3>;
123
-
interrupt-parent = <&mpic>;
124
-
interrupts = <23 2>;
125
-
};
126
-
};
127
-
128
-
** Freescale Elo3 DMA Controller
129
-
DMA controller which has same function as EloPlus except that Elo3 has 8
130
-
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
131
-
series chips, such as t1040, t4240, b4860.
132
-
133
-
Required properties:
134
-
135
-
- compatible : must include "fsl,elo3-dma"
136
-
- reg : contains two entries for DMA General Status Registers,
137
-
i.e. DGSR0 which includes status for channel 1~4, and
138
-
DGSR1 for channel 5~8
139
-
- ranges : describes the mapping between the address space of the
140
-
DMA channels and the address space of the DMA controller
141
-
142
-
- DMA channel nodes:
143
-
- compatible : must include "fsl,eloplus-dma-channel"
144
-
- reg : DMA channel specific registers
145
-
- interrupts : interrupt specifier for DMA channel IRQ
146
-
147
-
Example:
148
-
dma@100300 {
149
-
#address-cells = <1>;
150
-
#size-cells = <1>;
151
-
compatible = "fsl,elo3-dma";
152
-
reg = <0x100300 0x4>,
153
-
<0x100600 0x4>;
154
-
ranges = <0x0 0x100100 0x500>;
155
-
dma-channel@0 {
156
-
compatible = "fsl,eloplus-dma-channel";
157
-
reg = <0x0 0x80>;
158
-
interrupts = <28 2 0 0>;
159
-
};
160
-
dma-channel@80 {
161
-
compatible = "fsl,eloplus-dma-channel";
162
-
reg = <0x80 0x80>;
163
-
interrupts = <29 2 0 0>;
164
-
};
165
-
dma-channel@100 {
166
-
compatible = "fsl,eloplus-dma-channel";
167
-
reg = <0x100 0x80>;
168
-
interrupts = <30 2 0 0>;
169
-
};
170
-
dma-channel@180 {
171
-
compatible = "fsl,eloplus-dma-channel";
172
-
reg = <0x180 0x80>;
173
-
interrupts = <31 2 0 0>;
174
-
};
175
-
dma-channel@300 {
176
-
compatible = "fsl,eloplus-dma-channel";
177
-
reg = <0x300 0x80>;
178
-
interrupts = <76 2 0 0>;
179
-
};
180
-
dma-channel@380 {
181
-
compatible = "fsl,eloplus-dma-channel";
182
-
reg = <0x380 0x80>;
183
-
interrupts = <77 2 0 0>;
184
-
};
185
-
dma-channel@400 {
186
-
compatible = "fsl,eloplus-dma-channel";
187
-
reg = <0x400 0x80>;
188
-
interrupts = <78 2 0 0>;
189
-
};
190
-
dma-channel@480 {
191
-
compatible = "fsl,eloplus-dma-channel";
192
-
reg = <0x480 0x80>;
193
-
interrupts = <79 2 0 0>;
194
-
};
195
-
};
196
-
197
-
Note on DMA channel compatible properties: The compatible property must say
198
-
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
199
-
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
200
-
DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
201
-
channel that should be used for another driver should not use
202
-
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
203
-
example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
204
-
for more information.
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
11968
11968
F: drivers/idle/intel_idle.c
11969
11969
11970
11970
INTEL IDXD DRIVER
11971
-
M: Fenghua Yu <fenghua.yu@intel.com>
11971
+
M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
11972
11972
R: Dave Jiang <dave.jiang@intel.com>
11973
11973
L: dmaengine@vger.kernel.org
11974
11974
S: Supported
···
15648
15648
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
15649
15649
L: dmaengine@vger.kernel.org
15650
15650
S: Supported
15651
-
F: Documentation/devicetree/bindings/dma/atmel-dma.txt
15651
+
F: Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml
15652
15652
F: drivers/dma/at_hdmac.c
15653
15653
F: drivers/dma/at_xdmac.c
15654
15654
F: include/dt-bindings/dma/at91.h
+1
-1
drivers/dma/Kconfig
+1
-1
drivers/dma/Kconfig
+2
-4
drivers/dma/amd/ae4dma/ae4dma-pci.c
+2
-4
drivers/dma/amd/ae4dma/ae4dma-pci.c
···
46
46
47
47
} else {
48
48
ae4_msix->msix_count = ret;
49
-
for (i = 0; i < MAX_AE4_HW_QUEUES; i++)
50
-
ae4->ae4_irq[i] = ae4_msix->msix_entry[i].vector;
49
+
for (i = 0; i < ae4_msix->msix_count; i++)
50
+
ae4->ae4_irq[i] = pci_irq_vector(pdev, i);
51
51
}
52
52
53
53
return ret;
···
137
137
}
138
138
139
139
static const struct pci_device_id ae4_pci_table[] = {
140
-
{ PCI_VDEVICE(AMD, 0x14C8), },
141
-
{ PCI_VDEVICE(AMD, 0x14DC), },
142
140
{ PCI_VDEVICE(AMD, 0x149B), },
143
141
/* Last entry must be zero */
144
142
{ 0, }
+2
drivers/dma/amd/ae4dma/ae4dma.h
+2
drivers/dma/amd/ae4dma/ae4dma.h
+87
-3
drivers/dma/amd/ptdma/ptdma-dmaengine.c
+87
-3
drivers/dma/amd/ptdma/ptdma-dmaengine.c
···
198
198
{
199
199
struct dma_async_tx_descriptor *tx_desc;
200
200
struct virt_dma_desc *vd;
201
+
struct pt_device *pt;
201
202
unsigned long flags;
202
203
204
+
pt = chan->pt;
203
205
/* Loop over descriptors until one is found with commands */
204
206
do {
205
207
if (desc) {
···
219
217
220
218
spin_lock_irqsave(&chan->vc.lock, flags);
221
219
222
-
if (desc) {
220
+
if (pt->ver != AE4_DMA_VERSION && desc) {
223
221
if (desc->status != DMA_COMPLETE) {
224
222
if (desc->status != DMA_ERROR)
225
223
desc->status = DMA_COMPLETE;
···
237
235
238
236
spin_unlock_irqrestore(&chan->vc.lock, flags);
239
237
240
-
if (tx_desc) {
238
+
if (pt->ver != AE4_DMA_VERSION && tx_desc) {
241
239
dmaengine_desc_get_callback_invoke(tx_desc, NULL);
242
240
dma_run_dependencies(tx_desc);
243
241
vchan_vdesc_fini(vd);
···
247
245
return NULL;
248
246
}
249
247
248
+
static inline bool ae4_core_queue_full(struct pt_cmd_queue *cmd_q)
249
+
{
250
+
u32 front_wi = readl(cmd_q->reg_control + AE4_WR_IDX_OFF);
251
+
u32 rear_ri = readl(cmd_q->reg_control + AE4_RD_IDX_OFF);
252
+
253
+
if (((MAX_CMD_QLEN + front_wi - rear_ri) % MAX_CMD_QLEN) >= (MAX_CMD_QLEN - 1))
254
+
return true;
255
+
256
+
return false;
257
+
}
258
+
250
259
static void pt_cmd_callback(void *data, int err)
251
260
{
252
261
struct pt_dma_desc *desc = data;
262
+
struct ae4_cmd_queue *ae4cmd_q;
253
263
struct dma_chan *dma_chan;
254
264
struct pt_dma_chan *chan;
265
+
struct ae4_device *ae4;
266
+
struct pt_device *pt;
255
267
int ret;
256
268
257
269
if (err == -EINPROGRESS)
···
273
257
274
258
dma_chan = desc->vd.tx.chan;
275
259
chan = to_pt_chan(dma_chan);
260
+
pt = chan->pt;
276
261
277
262
if (err)
278
263
desc->status = DMA_ERROR;
279
264
280
265
while (true) {
266
+
if (pt->ver == AE4_DMA_VERSION) {
267
+
ae4 = container_of(pt, struct ae4_device, pt);
268
+
ae4cmd_q = &ae4->ae4cmd_q[chan->id];
269
+
270
+
if (ae4cmd_q->q_cmd_count >= (CMD_Q_LEN - 1) ||
271
+
ae4_core_queue_full(&ae4cmd_q->cmd_q)) {
272
+
wake_up(&ae4cmd_q->q_w);
273
+
274
+
if (wait_for_completion_timeout(&ae4cmd_q->cmp,
275
+
msecs_to_jiffies(AE4_TIME_OUT))
276
+
== 0) {
277
+
dev_err(pt->dev, "TIMEOUT %d:\n", ae4cmd_q->id);
278
+
break;
279
+
}
280
+
281
+
reinit_completion(&ae4cmd_q->cmp);
282
+
continue;
283
+
}
284
+
}
285
+
281
286
/* Check for DMA descriptor completion */
282
287
desc = pt_handle_active_desc(chan, desc);
283
288
···
333
296
return desc;
334
297
}
335
298
299
+
static void pt_cmd_callback_work(void *data, int err)
300
+
{
301
+
struct dma_async_tx_descriptor *tx_desc;
302
+
struct pt_dma_desc *desc = data;
303
+
struct dma_chan *dma_chan;
304
+
struct virt_dma_desc *vd;
305
+
struct pt_dma_chan *chan;
306
+
unsigned long flags;
307
+
308
+
dma_chan = desc->vd.tx.chan;
309
+
chan = to_pt_chan(dma_chan);
310
+
311
+
if (err == -EINPROGRESS)
312
+
return;
313
+
314
+
tx_desc = &desc->vd.tx;
315
+
vd = &desc->vd;
316
+
317
+
if (err)
318
+
desc->status = DMA_ERROR;
319
+
320
+
spin_lock_irqsave(&chan->vc.lock, flags);
321
+
if (desc) {
322
+
if (desc->status != DMA_COMPLETE) {
323
+
if (desc->status != DMA_ERROR)
324
+
desc->status = DMA_COMPLETE;
325
+
326
+
dma_cookie_complete(tx_desc);
327
+
dma_descriptor_unmap(tx_desc);
328
+
} else {
329
+
tx_desc = NULL;
330
+
}
331
+
}
332
+
spin_unlock_irqrestore(&chan->vc.lock, flags);
333
+
334
+
if (tx_desc) {
335
+
dmaengine_desc_get_callback_invoke(tx_desc, NULL);
336
+
dma_run_dependencies(tx_desc);
337
+
list_del(&desc->vd.node);
338
+
vchan_vdesc_fini(vd);
339
+
}
340
+
}
341
+
336
342
static struct pt_dma_desc *pt_create_desc(struct dma_chan *dma_chan,
337
343
dma_addr_t dst,
338
344
dma_addr_t src,
···
407
327
desc->len = len;
408
328
409
329
if (pt->ver == AE4_DMA_VERSION) {
330
+
pt_cmd->pt_cmd_callback = pt_cmd_callback_work;
410
331
ae4 = container_of(pt, struct ae4_device, pt);
411
332
ae4cmd_q = &ae4->ae4cmd_q[chan->id];
412
333
mutex_lock(&ae4cmd_q->cmd_lock);
···
448
367
{
449
368
struct pt_dma_chan *chan = to_pt_chan(dma_chan);
450
369
struct pt_dma_desc *desc;
370
+
struct pt_device *pt;
451
371
unsigned long flags;
452
372
bool engine_is_idle = true;
373
+
374
+
pt = chan->pt;
453
375
454
376
spin_lock_irqsave(&chan->vc.lock, flags);
455
377
456
378
desc = pt_next_dma_desc(chan);
457
-
if (desc)
379
+
if (desc && pt->ver != AE4_DMA_VERSION)
458
380
engine_is_idle = false;
459
381
460
382
vchan_issue_pending(&chan->vc);
+1
-1
drivers/dma/bcm2835-dma.c
+1
-1
drivers/dma/bcm2835-dma.c
+8
-8
drivers/dma/dmaengine.c
+8
-8
drivers/dma/dmaengine.c
···
40
40
#include <linux/dmaengine.h>
41
41
#include <linux/hardirq.h>
42
42
#include <linux/spinlock.h>
43
+
#include <linux/of.h>
44
+
#include <linux/property.h>
43
45
#include <linux/percpu.h>
44
46
#include <linux/rcupdate.h>
45
47
#include <linux/mutex.h>
···
814
812
*/
815
813
struct dma_chan *dma_request_chan(struct device *dev, const char *name)
816
814
{
815
+
struct fwnode_handle *fwnode = dev_fwnode(dev);
817
816
struct dma_device *d, *_d;
818
817
struct dma_chan *chan = NULL;
819
818
820
-
/* If device-tree is present get slave info from here */
821
-
if (dev->of_node)
822
-
chan = of_dma_request_slave_channel(dev->of_node, name);
823
-
824
-
/* If device was enumerated by ACPI get slave info from here */
825
-
if (has_acpi_companion(dev) && !chan)
819
+
if (is_of_node(fwnode))
820
+
chan = of_dma_request_slave_channel(to_of_node(fwnode), name);
821
+
else if (is_acpi_device_node(fwnode))
826
822
chan = acpi_dma_request_slave_chan_by_name(dev, name);
827
823
828
824
if (PTR_ERR(chan) == -EPROBE_DEFER)
···
854
854
855
855
found:
856
856
#ifdef CONFIG_DEBUG_FS
857
-
chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev),
858
-
name);
857
+
chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev), name);
858
+
/* No functional issue if it fails, users are supposed to test before use */
859
859
#endif
860
860
861
861
chan->name = kasprintf(GFP_KERNEL, "dma:%s", name);
+3
-3
drivers/dma/dmatest.c
+3
-3
drivers/dma/dmatest.c
···
841
841
} else {
842
842
dma_async_issue_pending(chan);
843
843
844
-
wait_event_freezable_timeout(thread->done_wait,
845
-
done->done,
846
-
msecs_to_jiffies(params->timeout));
844
+
wait_event_timeout(thread->done_wait,
845
+
done->done,
846
+
msecs_to_jiffies(params->timeout));
847
847
848
848
status = dma_async_is_tx_complete(chan, cookie, NULL,
849
849
NULL);
+4
-2
drivers/dma/dw-edma/dw-edma-core.c
+4
-2
drivers/dma/dw-edma/dw-edma-core.c
···
15
15
#include <linux/irq.h>
16
16
#include <linux/dma/edma.h>
17
17
#include <linux/dma-mapping.h>
18
+
#include <linux/string_choices.h>
18
19
19
20
#include "dw-edma-core.h"
20
21
#include "dw-edma-v0-core.h"
···
747
746
chan->ll_max -= 1;
748
747
749
748
dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n",
750
-
chan->dir == EDMA_DIR_WRITE ? "write" : "read",
749
+
str_write_read(chan->dir == EDMA_DIR_WRITE),
751
750
chan->id, chan->ll_max);
752
751
753
752
if (dw->nr_irqs == 1)
···
768
767
memcpy(&chan->msi, &irq->msi, sizeof(chan->msi));
769
768
770
769
dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n",
771
-
chan->dir == EDMA_DIR_WRITE ? "write" : "read", chan->id,
770
+
str_write_read(chan->dir == EDMA_DIR_WRITE),
771
+
chan->id,
772
772
chan->msi.address_hi, chan->msi.address_lo,
773
773
chan->msi.data);
774
774
+2
-6
drivers/dma/dw/pci.c
+2
-6
drivers/dma/dw/pci.c
···
76
76
dev_warn(&pdev->dev, "can't remove device properly: %d\n", ret);
77
77
}
78
78
79
-
#ifdef CONFIG_PM_SLEEP
80
-
81
79
static int dw_pci_suspend_late(struct device *dev)
82
80
{
83
81
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
···
92
94
return do_dw_dma_enable(chip);
93
95
};
94
96
95
-
#endif /* CONFIG_PM_SLEEP */
96
-
97
97
static const struct dev_pm_ops dw_pci_dev_pm_ops = {
98
-
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_pci_suspend_late, dw_pci_resume_early)
98
+
LATE_SYSTEM_SLEEP_PM_OPS(dw_pci_suspend_late, dw_pci_resume_early)
99
99
};
100
100
101
101
static const struct pci_device_id dw_pci_id_table[] = {
···
132
136
.probe = dw_pci_probe,
133
137
.remove = dw_pci_remove,
134
138
.driver = {
135
-
.pm = &dw_pci_dev_pm_ops,
139
+
.pm = pm_sleep_ptr(&dw_pci_dev_pm_ops),
136
140
},
137
141
};
138
142
+2
-6
drivers/dma/dw/platform.c
+2
-6
drivers/dma/dw/platform.c
···
157
157
MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
158
158
#endif
159
159
160
-
#ifdef CONFIG_PM_SLEEP
161
-
162
160
static int dw_suspend_late(struct device *dev)
163
161
{
164
162
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
···
181
183
return do_dw_dma_enable(chip);
182
184
}
183
185
184
-
#endif /* CONFIG_PM_SLEEP */
185
-
186
186
static const struct dev_pm_ops dw_dev_pm_ops = {
187
-
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
187
+
LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
188
188
};
189
189
190
190
static struct platform_driver dw_driver = {
···
191
195
.shutdown = dw_shutdown,
192
196
.driver = {
193
197
.name = DRV_NAME,
194
-
.pm = &dw_dev_pm_ops,
198
+
.pm = pm_sleep_ptr(&dw_dev_pm_ops),
195
199
.of_match_table = of_match_ptr(dw_dma_of_id_table),
196
200
.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
197
201
},
+12
-6
drivers/dma/fsl-edma-main.c
+12
-6
drivers/dma/fsl-edma-main.c
···
164
164
fsl_chan = &fsl_edma->chans[i];
165
165
166
166
if (fsl_chan->srcid && srcid == fsl_chan->srcid) {
167
-
dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!");
167
+
dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!\n");
168
168
return true;
169
169
}
170
170
}
···
401
401
402
402
/* The last IRQ is for eDMA err */
403
403
if (i == count - 1) {
404
+
fsl_edma->errirq = irq;
404
405
ret = devm_request_irq(&pdev->dev, irq,
405
406
fsl_edma_err_handler,
406
407
0, "eDMA2-ERR", fsl_edma);
···
421
420
struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
422
421
{
423
422
if (fsl_edma->txirq == fsl_edma->errirq) {
424
-
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
423
+
if (fsl_edma->txirq >= 0)
424
+
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
425
425
} else {
426
-
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
427
-
devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
426
+
if (fsl_edma->txirq >= 0)
427
+
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
428
+
if (fsl_edma->errirq >= 0)
429
+
devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
428
430
}
429
431
}
430
432
···
624
620
if (!fsl_edma)
625
621
return -ENOMEM;
626
622
623
+
fsl_edma->errirq = -EINVAL;
624
+
fsl_edma->txirq = -EINVAL;
627
625
fsl_edma->drvdata = drvdata;
628
626
fsl_edma->n_chans = chans;
629
627
mutex_init(&fsl_edma->fsl_edma_mutex);
···
808
802
struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
809
803
810
804
fsl_edma_irq_exit(pdev, fsl_edma);
811
-
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
812
805
of_dma_controller_free(np);
813
806
dma_async_device_unregister(&fsl_edma->dma_dev);
807
+
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
814
808
fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
815
809
}
816
810
···
828
822
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
829
823
/* Make sure chan is idle or will force disable. */
830
824
if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
831
-
dev_warn(dev, "WARN: There is non-idle channel.");
825
+
dev_warn(dev, "WARN: There is non-idle channel.\n");
832
826
fsl_edma_disable_request(fsl_chan);
833
827
fsl_edma_chan_mux(fsl_chan, 0, false);
834
828
}
+1
-2
drivers/dma/idxd/init.c
+1
-2
drivers/dma/idxd/init.c
+1
-1
drivers/dma/img-mdc-dma.c
+1
-1
drivers/dma/img-mdc-dma.c
+2
-1
drivers/dma/imx-dma.c
+2
-1
drivers/dma/imx-dma.c
···
17
17
#include <linux/device.h>
18
18
#include <linux/dma-mapping.h>
19
19
#include <linux/slab.h>
20
+
#include <linux/string_choices.h>
20
21
#include <linux/platform_device.h>
21
22
#include <linux/clk.h>
22
23
#include <linux/dmaengine.h>
···
943
942
" src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
944
943
imxdmac->channel, (unsigned long long)xt->src_start,
945
944
(unsigned long long) xt->dst_start,
946
-
xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
945
+
str_true_false(xt->src_sgl), str_true_false(xt->dst_sgl),
947
946
xt->numf, xt->frame_size);
948
947
949
948
if (list_empty(&imxdmac->ld_free) ||
+2
-3
drivers/dma/imx-sdma.c
+2
-3
drivers/dma/imx-sdma.c
···
1459
1459
* dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1460
1460
* Please note in any other slave case, you have to setup chan->private
1461
1461
* with 'struct imx_dma_data' in your own filter function if you want to
1462
-
* request dma channel by dma_request_channel() rather than
1463
-
* dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1464
-
* to warn you to correct your filter function.
1462
+
* request DMA channel by dma_request_channel(), otherwise, 'MEMCPY in
1463
+
* case?' will appear to warn you to correct your filter function.
1465
1464
*/
1466
1465
if (!data) {
1467
1466
dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
+2
-2
drivers/dma/pxa_dma.c
+2
-2
drivers/dma/pxa_dma.c
···
10
10
#include <linux/interrupt.h>
11
11
#include <linux/dma-mapping.h>
12
12
#include <linux/slab.h>
13
+
#include <linux/string_choices.h>
13
14
#include <linux/dmaengine.h>
14
15
#include <linux/platform_device.h>
15
16
#include <linux/device.h>
···
278
277
seq_printf(s, "\tPriority : %s\n",
279
278
str_prio[(phy->idx & 0xf) / 4]);
280
279
seq_printf(s, "\tUnaligned transfer bit: %s\n",
281
-
_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
282
-
"yes" : "no");
280
+
str_yes_no(_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx)));
283
281
seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
284
282
dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
285
283
PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
+1
-1
drivers/dma/sh/shdma-base.c
+1
-1
drivers/dma/sh/shdma-base.c
···
725
725
slave_addr = ops->slave_addr(schan);
726
726
727
727
/*
728
-
* Allocate the sg list dynamically as it would consumer too much stack
728
+
* Allocate the sg list dynamically as it would consume too much stack
729
729
* space.
730
730
*/
731
731
sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_KERNEL);
+2
-1
drivers/dma/sun6i-dma.c
+2
-1
drivers/dma/sun6i-dma.c
···
19
19
#include <linux/platform_device.h>
20
20
#include <linux/reset.h>
21
21
#include <linux/slab.h>
22
+
#include <linux/string_choices.h>
22
23
#include <linux/types.h>
23
24
24
25
#include "virt-dma.h"
···
554
553
continue;
555
554
556
555
dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
557
-
i ? "high" : "low", status);
556
+
str_high_low(i), status);
558
557
559
558
writel(status, sdev->base + DMA_IRQ_STAT(i));
560
559
+8
-3
drivers/dma/ti/edma.c
+8
-3
drivers/dma/ti/edma.c
···
16
16
#include <linux/platform_device.h>
17
17
#include <linux/slab.h>
18
18
#include <linux/spinlock.h>
19
+
#include <linux/string_choices.h>
19
20
#include <linux/of.h>
20
21
#include <linux/of_dma.h>
21
22
#include <linux/of_irq.h>
···
2048
2047
dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
2049
2048
dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
2050
2049
dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
2051
-
dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
2050
+
dev_dbg(dev, "chmap_exist: %s\n", str_yes_no(ecc->chmap_exist));
2052
2051
2053
2052
/* Nothing need to be done if queue priority is provided */
2054
2053
if (pdata->queue_priority_mapping)
···
2259
2258
2260
2259
return NULL;
2261
2260
out:
2262
-
/* The channel is going to be used as HW synchronized */
2263
-
echan->hw_triggered = true;
2261
+
/*
2262
+
* The channel is going to be HW synchronized, unless it was
2263
+
* reserved as a memcpy channel
2264
+
*/
2265
+
echan->hw_triggered =
2266
+
!edma_is_memcpy_channel(i, ecc->info->memcpy_channels);
2264
2267
return dma_get_slave_channel(chan);
2265
2268
}
2266
2269
#else
+11
-4
drivers/dma/ti/k3-udma-glue.c
+11
-4
drivers/dma/ti/k3-udma-glue.c
···
84
84
struct k3_udma_glue_rx_flow *flows;
85
85
u32 flow_num;
86
86
u32 flows_ready;
87
+
bool single_fdq; /* one FDQ for all flows */
87
88
};
88
89
89
90
static void k3_udma_chan_dev_release(struct device *dev)
···
971
970
972
971
ep_cfg = rx_chn->common.ep_config;
973
972
974
-
if (xudma_is_pktdma(rx_chn->common.udmax))
973
+
if (xudma_is_pktdma(rx_chn->common.udmax)) {
975
974
rx_chn->udma_rchan_id = ep_cfg->mapped_channel_id;
976
-
else
975
+
rx_chn->single_fdq = false;
976
+
} else {
977
977
rx_chn->udma_rchan_id = -1;
978
+
rx_chn->single_fdq = true;
979
+
}
978
980
979
981
/* request and cfg UDMAP RX channel */
980
982
rx_chn->udma_rchanx = xudma_rchan_get(rx_chn->common.udmax,
···
1107
1103
rx_chn->common.chan_dev.dma_coherent = true;
1108
1104
dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev,
1109
1105
DMA_BIT_MASK(48));
1106
+
rx_chn->single_fdq = false;
1107
+
} else {
1108
+
rx_chn->single_fdq = true;
1110
1109
}
1111
1110
1112
1111
ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg);
···
1460
1453
1461
1454
void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
1462
1455
u32 flow_num, void *data,
1463
-
void (*cleanup)(void *data, dma_addr_t desc_dma), bool skip_fdq)
1456
+
void (*cleanup)(void *data, dma_addr_t desc_dma))
1464
1457
{
1465
1458
struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
1466
1459
struct device *dev = rx_chn->common.dev;
···
1472
1465
dev_dbg(dev, "RX reset flow %u occ_rx %u\n", flow_num, occ_rx);
1473
1466
1474
1467
/* Skip RX FDQ in case one FDQ is used for the set of flows */
1475
-
if (skip_fdq)
1468
+
if (rx_chn->single_fdq && flow_num)
1476
1469
goto do_reset;
1477
1470
1478
1471
/*
+36
drivers/dma/ti/k3-udma.c
+36
drivers/dma/ti/k3-udma.c
···
4886
4886
irq_res.desc[i].start = rm_res->desc[i].start +
4887
4887
oes->bcdma_bchan_ring;
4888
4888
irq_res.desc[i].num = rm_res->desc[i].num;
4889
+
4890
+
if (rm_res->desc[i].num_sec) {
4891
+
irq_res.desc[i].start_sec = rm_res->desc[i].start_sec +
4892
+
oes->bcdma_bchan_ring;
4893
+
irq_res.desc[i].num_sec = rm_res->desc[i].num_sec;
4894
+
}
4889
4895
}
4890
4896
}
4891
4897
} else {
···
4915
4909
irq_res.desc[i + 1].start = rm_res->desc[j].start +
4916
4910
oes->bcdma_tchan_ring;
4917
4911
irq_res.desc[i + 1].num = rm_res->desc[j].num;
4912
+
4913
+
if (rm_res->desc[j].num_sec) {
4914
+
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
4915
+
oes->bcdma_tchan_data;
4916
+
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
4917
+
irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec +
4918
+
oes->bcdma_tchan_ring;
4919
+
irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec;
4920
+
}
4918
4921
}
4919
4922
}
4920
4923
}
···
4944
4929
irq_res.desc[i + 1].start = rm_res->desc[j].start +
4945
4930
oes->bcdma_rchan_ring;
4946
4931
irq_res.desc[i + 1].num = rm_res->desc[j].num;
4932
+
4933
+
if (rm_res->desc[j].num_sec) {
4934
+
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
4935
+
oes->bcdma_rchan_data;
4936
+
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
4937
+
irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec +
4938
+
oes->bcdma_rchan_ring;
4939
+
irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec;
4940
+
}
4947
4941
}
4948
4942
}
4949
4943
}
···
5087
5063
irq_res.desc[i].start = rm_res->desc[i].start +
5088
5064
oes->pktdma_tchan_flow;
5089
5065
irq_res.desc[i].num = rm_res->desc[i].num;
5066
+
5067
+
if (rm_res->desc[i].num_sec) {
5068
+
irq_res.desc[i].start_sec = rm_res->desc[i].start_sec +
5069
+
oes->pktdma_tchan_flow;
5070
+
irq_res.desc[i].num_sec = rm_res->desc[i].num_sec;
5071
+
}
5090
5072
}
5091
5073
}
5092
5074
rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
···
5104
5074
irq_res.desc[i].start = rm_res->desc[j].start +
5105
5075
oes->pktdma_rchan_flow;
5106
5076
irq_res.desc[i].num = rm_res->desc[j].num;
5077
+
5078
+
if (rm_res->desc[j].num_sec) {
5079
+
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
5080
+
oes->pktdma_rchan_flow;
5081
+
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
5082
+
}
5107
5083
}
5108
5084
}
5109
5085
ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);
+2
-1
drivers/dma/xilinx/xilinx_dma.c
+2
-1
drivers/dma/xilinx/xilinx_dma.c
···
46
46
#include <linux/of_irq.h>
47
47
#include <linux/platform_device.h>
48
48
#include <linux/slab.h>
49
+
#include <linux/string_choices.h>
49
50
#include <linux/clk.h>
50
51
#include <linux/io-64-nonatomic-lo-hi.h>
51
52
···
2941
2940
XILINX_DMA_DMASR_SG_MASK)
2942
2941
chan->has_sg = true;
2943
2942
dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2944
-
chan->has_sg ? "enabled" : "disabled");
2943
+
str_enabled_disabled(chan->has_sg));
2945
2944
}
2946
2945
2947
2946
/* Initialize the tasklet */
+2
-2
drivers/net/ethernet/ti/am65-cpsw-nuss.c
+2
-2
drivers/net/ethernet/ti/am65-cpsw-nuss.c
···
516
516
napi_disable(&flow->napi_rx);
517
517
hrtimer_cancel(&flow->rx_hrtimer);
518
518
k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn,
519
-
am65_cpsw_nuss_rx_cleanup, !!id);
519
+
am65_cpsw_nuss_rx_cleanup);
520
520
521
521
for (port = 0; port < common->port_num; port++) {
522
522
if (!common->ports[port].ndev)
···
3332
3332
for (i = 0; i < common->rx_ch_num_flows; i++)
3333
3333
k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i,
3334
3334
rx_chan,
3335
-
am65_cpsw_nuss_rx_cleanup, !!i);
3335
+
am65_cpsw_nuss_rx_cleanup);
3336
3336
3337
3337
k3_udma_glue_disable_rx_chn(rx_chan->rx_chn);
3338
3338
+1
-1
drivers/net/ethernet/ti/icssg/icssg_common.c
+1
-1
drivers/net/ethernet/ti/icssg/icssg_common.c
+1
-2
include/linux/dma/k3-udma-glue.h
+1
-2
include/linux/dma/k3-udma-glue.h
···
138
138
u32 flow_num);
139
139
void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
140
140
u32 flow_num, void *data,
141
-
void (*cleanup)(void *data, dma_addr_t desc_dma),
142
-
bool skip_fdq);
141
+
void (*cleanup)(void *data, dma_addr_t desc_dma));
143
142
int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
144
143
u32 flow_idx);
145
144
int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
+3
-7
include/linux/dmaengine.h
+3
-7
include/linux/dmaengine.h
···
839
839
* The function takes a buffer of size buf_len. The callback function will
840
840
* be called after period_len bytes have been transferred.
841
841
* @device_prep_interleaved_dma: Transfer expression in a generic way.
842
-
* @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
843
842
* @device_caps: May be used to override the generic DMA slave capabilities
844
843
* with per-channel specific ones
845
844
* @device_config: Pushes a new configuration to a channel, return 0 or an error
···
940
941
unsigned long flags);
941
942
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
942
943
struct dma_chan *chan, struct dma_interleaved_template *xt,
943
-
unsigned long flags);
944
-
struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
945
-
struct dma_chan *chan, dma_addr_t dst, u64 data,
946
944
unsigned long flags);
947
945
948
946
void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
···
1635
1639
{
1636
1640
struct dma_chan *chan;
1637
1641
1638
-
chan = dma_request_slave_channel(dev, name);
1639
-
if (chan)
1642
+
chan = dma_request_chan(dev, name);
1643
+
if (!IS_ERR(chan))
1640
1644
return chan;
1641
1645
1642
1646
if (!fn || !fn_param)
1643
1647
return NULL;
1644
1648
1645
-
return __dma_request_channel(&mask, fn, fn_param, NULL);
1649
+
return dma_request_channel(mask, fn, fn_param);
1646
1650
}
1647
1651
1648
1652
static inline char *