Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: DIO Supported for virtual displays

[WHY]
Virtual displays do not use the backend of the pipe, and so have
infinite backend bandwidth.

[HOW]
Add a skip_dio_check bool to the VBA struct, which is used to override
the DIOSupport calculations.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Acked-by: Chris Park <Chris.Park@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Wesley Chalmers and committed by
Alex Deucher
91a51fbf 148816f9

+19 -10
+2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 2097 2097 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 2098 2098 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 2099 2099 pipes[pipe_cnt].dout.dp_lanes = 4; 2100 + pipes[pipe_cnt].dout.is_virtual = 0; 2100 2101 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 2101 2102 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; 2102 2103 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { ··· 2151 2150 break; 2152 2151 default: 2153 2152 /* In case there is no signal, set dp with 4 lanes to allow max config */ 2153 + pipes[pipe_cnt].dout.is_virtual = 1; 2154 2154 pipes[pipe_cnt].dout.output_type = dm_dp; 2155 2155 pipes[pipe_cnt].dout.dp_lanes = 4; 2156 2156 }
+4 -3
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
··· 4168 4168 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 4169 4169 locals->DIOSupport[i] = true; 4170 4170 for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { 4171 - if (locals->OutputBppPerState[i][k] == BPP_INVALID 4172 - || (mode_lib->vba.OutputFormat[k] == dm_420 4171 + if (!mode_lib->vba.skip_dio_check[k] 4172 + && (locals->OutputBppPerState[i][k] == BPP_INVALID 4173 + || (mode_lib->vba.OutputFormat[k] == dm_420 4173 4174 && mode_lib->vba.Interlace[k] == true 4174 - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { 4175 + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { 4175 4176 locals->DIOSupport[i] = false; 4176 4177 } 4177 4178 }
+4 -3
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
··· 4289 4289 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 4290 4290 locals->DIOSupport[i] = true; 4291 4291 for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { 4292 - if (locals->OutputBppPerState[i][k] == BPP_INVALID 4293 - || (mode_lib->vba.OutputFormat[k] == dm_420 4292 + if (!mode_lib->vba.skip_dio_check[k] 4293 + && (locals->OutputBppPerState[i][k] == BPP_INVALID 4294 + || (mode_lib->vba.OutputFormat[k] == dm_420 4294 4295 && mode_lib->vba.Interlace[k] == true 4295 - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { 4296 + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { 4296 4297 locals->DIOSupport[i] = false; 4297 4298 } 4298 4299 }
+4 -3
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
··· 4257 4257 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { 4258 4258 locals->DIOSupport[i] = true; 4259 4259 for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { 4260 - if (locals->OutputBppPerState[i][k] == BPP_INVALID 4261 - || (mode_lib->vba.OutputFormat[k] == dm_420 4260 + if (!mode_lib->vba.skip_dio_check[k] 4261 + && (locals->OutputBppPerState[i][k] == BPP_INVALID 4262 + || (mode_lib->vba.OutputFormat[k] == dm_420 4262 4263 && mode_lib->vba.Interlace[k] == true 4263 - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { 4264 + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { 4264 4265 locals->DIOSupport[i] = false; 4265 4266 } 4266 4267 }
+1 -1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
··· 4263 4263 for (i = 0; i < v->soc.num_states; i++) { 4264 4264 v->DIOSupport[i] = true; 4265 4265 for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { 4266 - if (v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi) 4266 + if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi) 4267 4267 && (v->OutputBppPerState[i][k] == 0 4268 4268 || (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) { 4269 4269 v->DIOSupport[i] = false;
+1
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
··· 297 297 int num_active_wb; 298 298 int output_bpc; 299 299 int output_type; 300 + int is_virtual; 300 301 int output_format; 301 302 int dsc_slices; 302 303 int max_audio_sample_rate;
+2
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
··· 451 451 dout->output_bpp; 452 452 mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] = 453 453 (enum output_encoder_class) (dout->output_type); 454 + mode_lib->vba.skip_dio_check[mode_lib->vba.NumberOfActivePlanes] = 455 + dout->is_virtual; 454 456 455 457 if (!dout->dsc_enable) 456 458 mode_lib->vba.ForcedOutputLinkBPP[mode_lib->vba.NumberOfActivePlanes] = dout->output_bpp;
+1
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
··· 340 340 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 341 341 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 342 342 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 343 + bool skip_dio_check[DC__NUM_DPP__MAX]; 343 344 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 344 345 bool SynchronizedVBlank; 345 346 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];