tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: mmcc-sdm660: Use ARRAY_SIZE for num_parents

Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marijn Suijten and committed by
Stephen Boyd 916e9ece 7340264e

+36 -36
+36 -36
drivers/clk/qcom/mmcc-sdm660.c
··· 483 483 .clkr.hw.init = &(struct clk_init_data){ 484 484 .name = "ahb_clk_src", 485 485 .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div, 486 - .num_parents = 4, 486 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div), 487 487 .ops = &clk_rcg2_ops, 488 488 }, 489 489 }; ··· 496 496 .clkr.hw.init = &(struct clk_init_data){ 497 497 .name = "byte0_clk_src", 498 498 .parent_data = mmcc_xo_dsibyte, 499 - .num_parents = 3, 499 + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 500 500 .ops = &clk_byte2_ops, 501 501 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 502 502 }, ··· 510 510 .clkr.hw.init = &(struct clk_init_data){ 511 511 .name = "byte1_clk_src", 512 512 .parent_data = mmcc_xo_dsibyte, 513 - .num_parents = 3, 513 + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 514 514 .ops = &clk_byte2_ops, 515 515 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 516 516 }, ··· 538 538 .clkr.hw.init = &(struct clk_init_data){ 539 539 .name = "camss_gp0_clk_src", 540 540 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 541 - .num_parents = 7, 541 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 542 542 .ops = &clk_rcg2_ops, 543 543 }, 544 544 }; ··· 552 552 .clkr.hw.init = &(struct clk_init_data){ 553 553 .name = "camss_gp1_clk_src", 554 554 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 555 - .num_parents = 7, 555 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 556 556 .ops = &clk_rcg2_ops, 557 557 }, 558 558 }; ··· 573 573 .clkr.hw.init = &(struct clk_init_data){ 574 574 .name = "cci_clk_src", 575 575 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 576 - .num_parents = 7, 576 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 577 577 .ops = &clk_rcg2_ops, 578 578 }, 579 579 }; ··· 597 597 .clkr.hw.init = &(struct clk_init_data){ 598 598 .name = "cpp_clk_src", 599 599 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6, 600 - .num_parents = 7, 600 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6), 601 601 .ops = &clk_rcg2_ops, 602 602 }, 603 603 }; ··· 620 620 .clkr.hw.init = &(struct clk_init_data){ 621 621 .name = "csi0_clk_src", 622 622 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 623 - .num_parents = 7, 623 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 624 624 .ops = &clk_rcg2_ops, 625 625 }, 626 626 }; ··· 641 641 .clkr.hw.init = &(struct clk_init_data){ 642 642 .name = "csi0phytimer_clk_src", 643 643 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 644 - .num_parents = 7, 644 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 645 645 .ops = &clk_rcg2_ops, 646 646 }, 647 647 }; ··· 655 655 .clkr.hw.init = &(struct clk_init_data){ 656 656 .name = "csi1_clk_src", 657 657 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 658 - .num_parents = 7, 658 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 659 659 .ops = &clk_rcg2_ops, 660 660 }, 661 661 }; ··· 669 669 .clkr.hw.init = &(struct clk_init_data){ 670 670 .name = "csi1phytimer_clk_src", 671 671 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 672 - .num_parents = 7, 672 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 673 673 .ops = &clk_rcg2_ops, 674 674 }, 675 675 }; ··· 683 683 .clkr.hw.init = &(struct clk_init_data){ 684 684 .name = "csi2_clk_src", 685 685 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 686 - .num_parents = 7, 686 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 687 687 .ops = &clk_rcg2_ops, 688 688 }, 689 689 }; ··· 697 697 .clkr.hw.init = &(struct clk_init_data){ 698 698 .name = "csi2phytimer_clk_src", 699 699 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 700 - .num_parents = 7, 700 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 701 701 .ops = &clk_rcg2_ops, 702 702 }, 703 703 }; ··· 711 711 .clkr.hw.init = &(struct clk_init_data){ 712 712 .name = "csi3_clk_src", 713 713 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 714 - .num_parents = 7, 714 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 715 715 .ops = &clk_rcg2_ops, 716 716 }, 717 717 }; ··· 733 733 .clkr.hw.init = &(struct clk_init_data){ 734 734 .name = "csiphy_clk_src", 735 735 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 736 - .num_parents = 7, 736 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 737 737 .ops = &clk_rcg2_ops, 738 738 }, 739 739 }; ··· 752 752 .clkr.hw.init = &(struct clk_init_data){ 753 753 .name = "dp_aux_clk_src", 754 754 .parent_data = mmcc_xo_gpll0_gpll0_div, 755 - .num_parents = 3, 755 + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 756 756 .ops = &clk_rcg2_ops, 757 757 }, 758 758 }; ··· 773 773 .clkr.hw.init = &(struct clk_init_data){ 774 774 .name = "dp_crypto_clk_src", 775 775 .parent_data = mmcc_xo_dplink_dpvco, 776 - .num_parents = 3, 776 + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 777 777 .ops = &clk_rcg2_ops, 778 778 }, 779 779 }; ··· 793 793 .clkr.hw.init = &(struct clk_init_data){ 794 794 .name = "dp_gtc_clk_src", 795 795 .parent_data = mmcc_xo_gpll0_gpll0_div, 796 - .num_parents = 3, 796 + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 797 797 .ops = &clk_rcg2_ops, 798 798 }, 799 799 }; ··· 814 814 .clkr.hw.init = &(struct clk_init_data){ 815 815 .name = "dp_link_clk_src", 816 816 .parent_data = mmcc_xo_dplink_dpvco, 817 - .num_parents = 3, 817 + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 818 818 .ops = &clk_rcg2_ops, 819 819 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 820 820 }, ··· 828 828 .clkr.hw.init = &(struct clk_init_data){ 829 829 .name = "dp_pixel_clk_src", 830 830 .parent_data = mmcc_xo_dplink_dpvco, 831 - .num_parents = 3, 831 + .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 832 832 .ops = &clk_dp_ops, 833 833 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 834 834 }, ··· 842 842 .clkr.hw.init = &(struct clk_init_data){ 843 843 .name = "esc0_clk_src", 844 844 .parent_data = mmcc_xo_dsibyte, 845 - .num_parents = 3, 845 + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 846 846 .ops = &clk_rcg2_ops, 847 847 }, 848 848 }; ··· 855 855 .clkr.hw.init = &(struct clk_init_data){ 856 856 .name = "esc1_clk_src", 857 857 .parent_data = mmcc_xo_dsibyte, 858 - .num_parents = 3, 858 + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 859 859 .ops = &clk_rcg2_ops, 860 860 }, 861 861 }; ··· 878 878 .clkr.hw.init = &(struct clk_init_data){ 879 879 .name = "jpeg0_clk_src", 880 880 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 881 - .num_parents = 7, 881 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 882 882 .ops = &clk_rcg2_ops, 883 883 }, 884 884 }; ··· 906 906 .clkr.hw.init = &(struct clk_init_data){ 907 907 .name = "mclk0_clk_src", 908 908 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 909 - .num_parents = 7, 909 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 910 910 .ops = &clk_rcg2_ops, 911 911 }, 912 912 }; ··· 920 920 .clkr.hw.init = &(struct clk_init_data){ 921 921 .name = "mclk1_clk_src", 922 922 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 923 - .num_parents = 7, 923 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 924 924 .ops = &clk_rcg2_ops, 925 925 }, 926 926 }; ··· 934 934 .clkr.hw.init = &(struct clk_init_data){ 935 935 .name = "mclk2_clk_src", 936 936 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 937 - .num_parents = 7, 937 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 938 938 .ops = &clk_rcg2_ops, 939 939 }, 940 940 }; ··· 948 948 .clkr.hw.init = &(struct clk_init_data){ 949 949 .name = "mclk3_clk_src", 950 950 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 951 - .num_parents = 7, 951 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 952 952 .ops = &clk_rcg2_ops, 953 953 }, 954 954 }; ··· 974 974 .clkr.hw.init = &(struct clk_init_data){ 975 975 .name = "mdp_clk_src", 976 976 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, 977 - .num_parents = 6, 977 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), 978 978 .ops = &clk_rcg2_ops, 979 979 }, 980 980 }; ··· 987 987 .clkr.hw.init = &(struct clk_init_data){ 988 988 .name = "pclk0_clk_src", 989 989 .parent_data = mmcc_xo_dsi0pll_dsi1pll, 990 - .num_parents = 3, 990 + .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), 991 991 .ops = &clk_pixel_ops, 992 992 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 993 993 }, ··· 1001 1001 .clkr.hw.init = &(struct clk_init_data){ 1002 1002 .name = "pclk1_clk_src", 1003 1003 .parent_data = mmcc_xo_dsi0pll_dsi1pll, 1004 - .num_parents = 3, 1004 + .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), 1005 1005 .ops = &clk_pixel_ops, 1006 1006 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1007 1007 }, ··· 1025 1025 .clkr.hw.init = &(struct clk_init_data){ 1026 1026 .name = "rot_clk_src", 1027 1027 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, 1028 - .num_parents = 6, 1028 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), 1029 1029 .ops = &clk_rcg2_ops, 1030 1030 }, 1031 1031 }; ··· 1051 1051 .clkr.hw.init = &(struct clk_init_data){ 1052 1052 .name = "vfe0_clk_src", 1053 1053 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, 1054 - .num_parents = 7, 1054 + .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), 1055 1055 .ops = &clk_rcg2_ops, 1056 1056 }, 1057 1057 }; ··· 1065 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 1066 .name = "vfe1_clk_src", 1067 1067 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, 1068 - .num_parents = 7, 1068 + .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), 1069 1069 .ops = &clk_rcg2_ops, 1070 1070 }, 1071 1071 }; ··· 1089 1089 .clkr.hw.init = &(struct clk_init_data){ 1090 1090 .name = "video_core_clk_src", 1091 1091 .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7, 1092 - .num_parents = 7, 1092 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7), 1093 1093 .ops = &clk_rcg2_ops, 1094 1094 .flags = CLK_IS_CRITICAL, 1095 1095 }, ··· 1104 1104 .clkr.hw.init = &(struct clk_init_data){ 1105 1105 .name = "vsync_clk_src", 1106 1106 .parent_data = mmcc_xo_gpll0_gpll0_div, 1107 - .num_parents = 3, 1107 + .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 1108 1108 .ops = &clk_rcg2_ops, 1109 1109 }, 1110 1110 }; ··· 2055 2055 .clkr.hw.init = &(struct clk_init_data){ 2056 2056 .name = "axi_clk_src", 2057 2057 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 2058 - .num_parents = 7, 2058 + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 2059 2059 .ops = &clk_rcg2_ops, 2060 2060 }, 2061 2061 };