ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Kirill A. Shutemov and committed by

Russell King 16 years ago 910a17e5 59fcf48f

+6 -1

2 changed files

expand all

arch

arm

include

asm

cache.h

Kconfig

+1 -1

arch/arm/include/asm/cache.h

··· 4 4 #ifndef __ASMARM_CACHE_H 5 5 #define __ASMARM_CACHE_H 6 6 7 - #define L1_CACHE_SHIFT 5 7 + #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT 8 8 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 9 9 10 10 /*

arch/arm/mm/Kconfig

··· 771 771 select OUTER_CACHE 772 772 help 773 773 This option enables the L2 cache on XScale3. 774 + 775 + config ARM_L1_CACHE_SHIFT 776 + int 777 + default 6 if ARCH_OMAP3 778 + default 5