Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mtd: nand: ecc-hamming: Rename the exported functions

Prefix by ecc_sw_hamming_ the functions which should be internal only
but are exported for "raw" operations.

Prefix by nand_ecc_sw_hamming_ the other functions which will be used
in the context of the declaration of an Hamming proper ECC engine
object.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-16-miquel.raynal@bootlin.com

+115 -99
+35 -32
drivers/mtd/nand/ecc-sw-hamming.c
··· 75 75 * addressbits is a lookup table to filter out the bits from the xor-ed 76 76 * ECC data that identify the faulty location. 77 77 * this is only used for repairing parity 78 - * see the comments in nand_correct_data for more details 78 + * see the comments in nand_ecc_sw_hamming_correct for more details 79 79 */ 80 80 static const char addressbits[256] = { 81 81 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, ··· 112 112 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f 113 113 }; 114 114 115 - void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize, 116 - unsigned char *code, bool sm_order) 115 + int ecc_sw_hamming_calculate(const unsigned char *buf, unsigned int step_size, 116 + unsigned char *code, bool sm_order) 117 117 { 118 118 const u32 *bp = (uint32_t *)buf; 119 - const u32 eccsize_mult = eccsize >> 8; 119 + const u32 eccsize_mult = step_size >> 8; 120 120 /* current value in buffer */ 121 121 u32 cur; 122 122 /* rp0..rp17 are the various accumulated parities (per byte) */ ··· 347 347 (invparity[par & 0x55] << 2) | 348 348 (invparity[rp17] << 1) | 349 349 (invparity[rp16] << 0); 350 - } 351 - EXPORT_SYMBOL(__nand_calculate_ecc); 352 - 353 - /** 354 - * nand_calculate_ecc - Calculate 3-byte ECC for 256/512-byte block 355 - * @chip: NAND chip object 356 - * @buf: Input buffer with raw data 357 - * @code: Output buffer with ECC 358 - */ 359 - int nand_calculate_ecc(struct nand_chip *chip, const unsigned char *buf, 360 - unsigned char *code) 361 - { 362 - bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; 363 - 364 - __nand_calculate_ecc(buf, chip->ecc.size, code, sm_order); 365 350 366 351 return 0; 367 352 } 368 - EXPORT_SYMBOL(nand_calculate_ecc); 353 + EXPORT_SYMBOL(ecc_sw_hamming_calculate); 369 354 370 - int __nand_correct_data(unsigned char *buf, 371 - unsigned char *read_ecc, unsigned char *calc_ecc, 372 - unsigned int eccsize, bool sm_order) 355 + /** 356 + * nand_ecc_sw_hamming_calculate - Calculate 3-byte ECC for 256/512-byte block 357 + * @nand: NAND device 358 + * @buf: Input buffer with raw data 359 + * @code: Output buffer with ECC 360 + */ 361 + int nand_ecc_sw_hamming_calculate(struct nand_device *nand, 362 + const unsigned char *buf, unsigned char *code) 373 363 { 374 - const u32 eccsize_mult = eccsize >> 8; 364 + struct nand_chip *chip = mtd_to_nand(nanddev_to_mtd(nand)); 365 + bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; 366 + 367 + return ecc_sw_hamming_calculate(buf, chip->ecc.size, code, sm_order); 368 + } 369 + EXPORT_SYMBOL(nand_ecc_sw_hamming_calculate); 370 + 371 + int ecc_sw_hamming_correct(unsigned char *buf, unsigned char *read_ecc, 372 + unsigned char *calc_ecc, unsigned int step_size, 373 + bool sm_order) 374 + { 375 + const u32 eccsize_mult = step_size >> 8; 375 376 unsigned char b0, b1, b2, bit_addr; 376 377 unsigned int byte_addr; 377 378 ··· 438 437 pr_err("%s: uncorrectable ECC error\n", __func__); 439 438 return -EBADMSG; 440 439 } 441 - EXPORT_SYMBOL(__nand_correct_data); 440 + EXPORT_SYMBOL(ecc_sw_hamming_correct); 442 441 443 442 /** 444 - * nand_correct_data - Detect and correct bit error(s) 445 - * @chip: NAND chip object 443 + * nand_ecc_sw_hamming_correct - Detect and correct bit error(s) 444 + * @nand: NAND device 446 445 * @buf: Raw data read from the chip 447 446 * @read_ecc: ECC bytes read from the chip 448 447 * @calc_ecc: ECC calculated from the raw data 449 448 * 450 449 * Detect and correct up to 1 bit error per 256/512-byte block. 451 450 */ 452 - int nand_correct_data(struct nand_chip *chip, unsigned char *buf, 453 - unsigned char *read_ecc, unsigned char *calc_ecc) 451 + int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf, 452 + unsigned char *read_ecc, 453 + unsigned char *calc_ecc) 454 454 { 455 + struct nand_chip *chip = mtd_to_nand(nanddev_to_mtd(nand)); 455 456 bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; 456 457 457 - return __nand_correct_data(buf, read_ecc, calc_ecc, chip->ecc.size, 458 - sm_order); 458 + return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc, chip->ecc.size, 459 + sm_order); 459 460 } 460 - EXPORT_SYMBOL(nand_correct_data); 461 + EXPORT_SYMBOL(nand_ecc_sw_hamming_correct); 461 462 462 463 MODULE_LICENSE("GPL"); 463 464 MODULE_AUTHOR("Frans Meulenbroeks <fransmeulenbroeks@gmail.com>");
+1 -2
drivers/mtd/nand/raw/cs553x_nand.c
··· 19 19 #include <linux/delay.h> 20 20 #include <linux/mtd/mtd.h> 21 21 #include <linux/mtd/rawnand.h> 22 - #include <linux/mtd/nand-ecc-sw-hamming.h> 23 22 #include <linux/mtd/partitions.h> 24 23 #include <linux/iopoll.h> 25 24 ··· 251 252 chip->ecc.bytes = 3; 252 253 chip->ecc.hwctl = cs_enable_hwecc; 253 254 chip->ecc.calculate = cs_calculate_ecc; 254 - chip->ecc.correct = nand_correct_data; 255 + chip->ecc.correct = rawnand_sw_hamming_correct; 255 256 chip->ecc.strength = 1; 256 257 257 258 return 0;
+1 -1
drivers/mtd/nand/raw/fsmc_nand.c
··· 918 918 case NAND_ECC_ENGINE_TYPE_ON_HOST: 919 919 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 920 920 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 921 - nand->ecc.correct = nand_correct_data; 921 + nand->ecc.correct = rawnand_sw_hamming_correct; 922 922 nand->ecc.hwctl = fsmc_enable_hwecc; 923 923 nand->ecc.bytes = 3; 924 924 nand->ecc.strength = 1;
+1 -1
drivers/mtd/nand/raw/lpc32xx_slc.c
··· 803 803 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; 804 804 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; 805 805 chip->ecc.calculate = lpc32xx_nand_ecc_calculate; 806 - chip->ecc.correct = nand_correct_data; 806 + chip->ecc.correct = rawnand_sw_hamming_correct; 807 807 chip->ecc.hwctl = lpc32xx_nand_ecc_enable; 808 808 809 809 /*
+23 -2
drivers/mtd/nand/raw/nand_base.c
··· 5139 5139 kfree(chip->parameters.onfi); 5140 5140 } 5141 5141 5142 + int rawnand_sw_hamming_calculate(struct nand_chip *chip, 5143 + const unsigned char *buf, 5144 + unsigned char *code) 5145 + { 5146 + struct nand_device *base = &chip->base; 5147 + 5148 + return nand_ecc_sw_hamming_calculate(base, buf, code); 5149 + } 5150 + EXPORT_SYMBOL(rawnand_sw_hamming_calculate); 5151 + 5152 + int rawnand_sw_hamming_correct(struct nand_chip *chip, 5153 + unsigned char *buf, 5154 + unsigned char *read_ecc, 5155 + unsigned char *calc_ecc) 5156 + { 5157 + struct nand_device *base = &chip->base; 5158 + 5159 + return nand_ecc_sw_hamming_correct(base, buf, read_ecc, calc_ecc); 5160 + } 5161 + EXPORT_SYMBOL(rawnand_sw_hamming_correct); 5162 + 5142 5163 int rawnand_sw_bch_init(struct nand_chip *chip) 5143 5164 { 5144 5165 struct nand_device *base = &chip->base; ··· 5284 5263 5285 5264 switch (ecc->algo) { 5286 5265 case NAND_ECC_ALGO_HAMMING: 5287 - ecc->calculate = nand_calculate_ecc; 5288 - ecc->correct = nand_correct_data; 5266 + ecc->calculate = rawnand_sw_hamming_calculate; 5267 + ecc->correct = rawnand_sw_hamming_correct; 5289 5268 ecc->read_page = nand_read_page_swecc; 5290 5269 ecc->read_subpage = nand_read_subpage; 5291 5270 ecc->write_page = nand_write_page_swecc;
+1 -2
drivers/mtd/nand/raw/ndfc.c
··· 18 18 */ 19 19 #include <linux/module.h> 20 20 #include <linux/mtd/rawnand.h> 21 - #include <linux/mtd/nand-ecc-sw-hamming.h> 22 21 #include <linux/mtd/partitions.h> 23 22 #include <linux/mtd/ndfc.h> 24 23 #include <linux/slab.h> ··· 145 146 chip->controller = &ndfc->ndfc_control; 146 147 chip->legacy.read_buf = ndfc_read_buf; 147 148 chip->legacy.write_buf = ndfc_write_buf; 148 - chip->ecc.correct = nand_correct_data; 149 + chip->ecc.correct = rawnand_sw_hamming_correct; 149 150 chip->ecc.hwctl = ndfc_enable_hwecc; 150 151 chip->ecc.calculate = ndfc_calculate_ecc; 151 152 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+1 -1
drivers/mtd/nand/raw/sharpsl.c
··· 107 107 chip->ecc.strength = 1; 108 108 chip->ecc.hwctl = sharpsl_nand_enable_hwecc; 109 109 chip->ecc.calculate = sharpsl_nand_calculate_ecc; 110 - chip->ecc.correct = nand_correct_data; 110 + chip->ecc.correct = rawnand_sw_hamming_correct; 111 111 112 112 return 0; 113 113 }
+3 -3
drivers/mtd/nand/raw/tmio_nand.c
··· 293 293 int r0, r1; 294 294 295 295 /* assume ecc.size = 512 and ecc.bytes = 6 */ 296 - r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256, false); 296 + r0 = rawnand_sw_hamming_correct(chip, buf, read_ecc, calc_ecc); 297 297 if (r0 < 0) 298 298 return r0; 299 - r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256, 300 - false); 299 + r1 = rawnand_sw_hamming_correct(chip, buf + 256, read_ecc + 3, 300 + calc_ecc + 3); 301 301 if (r1 < 0) 302 302 return r1; 303 303 return r0 + r1;
+2 -2
drivers/mtd/nand/raw/txx9ndfmc.c
··· 194 194 int stat; 195 195 196 196 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) { 197 - stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256, 198 - false); 197 + stat = rawnand_sw_hamming_correct(chip, buf, read_ecc, 198 + calc_ecc); 199 199 if (stat < 0) 200 200 return stat; 201 201 corrected += stat;
+14 -14
drivers/mtd/sm_ftl.c
··· 216 216 217 217 static int sm_correct_sector(uint8_t *buffer, struct sm_oob *oob) 218 218 { 219 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 219 220 uint8_t ecc[3]; 220 221 221 - __nand_calculate_ecc(buffer, SM_SMALL_PAGE, ecc, 222 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 223 - if (__nand_correct_data(buffer, ecc, oob->ecc1, SM_SMALL_PAGE, 224 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)) < 0) 222 + ecc_sw_hamming_calculate(buffer, SM_SMALL_PAGE, ecc, sm_order); 223 + if (ecc_sw_hamming_correct(buffer, ecc, oob->ecc1, SM_SMALL_PAGE, 224 + sm_order) < 0) 225 225 return -EIO; 226 226 227 227 buffer += SM_SMALL_PAGE; 228 228 229 - __nand_calculate_ecc(buffer, SM_SMALL_PAGE, ecc, 230 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 231 - if (__nand_correct_data(buffer, ecc, oob->ecc2, SM_SMALL_PAGE, 232 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)) < 0) 229 + ecc_sw_hamming_calculate(buffer, SM_SMALL_PAGE, ecc, sm_order); 230 + if (ecc_sw_hamming_correct(buffer, ecc, oob->ecc2, SM_SMALL_PAGE, 231 + sm_order) < 0) 233 232 return -EIO; 234 233 return 0; 235 234 } ··· 368 369 int zone, int block, int lba, 369 370 unsigned long invalid_bitmap) 370 371 { 372 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 371 373 struct sm_oob oob; 372 374 int boffset; 373 375 int retry = 0; ··· 395 395 } 396 396 397 397 if (ftl->smallpagenand) { 398 - __nand_calculate_ecc(buf + boffset, SM_SMALL_PAGE, 399 - oob.ecc1, 400 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 398 + ecc_sw_hamming_calculate(buf + boffset, 399 + SM_SMALL_PAGE, oob.ecc1, 400 + sm_order); 401 401 402 - __nand_calculate_ecc(buf + boffset + SM_SMALL_PAGE, 403 - SM_SMALL_PAGE, oob.ecc2, 404 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 402 + ecc_sw_hamming_calculate(buf + boffset + SM_SMALL_PAGE, 403 + SM_SMALL_PAGE, oob.ecc2, 404 + sm_order); 405 405 } 406 406 if (!sm_write_sector(ftl, zone, block, boffset, 407 407 buf + boffset, &oob))
+14 -15
drivers/mtd/tests/mtd_nandecctest.c
··· 119 119 static int no_bit_error_verify(void *error_data, void *error_ecc, 120 120 void *correct_data, const size_t size) 121 121 { 122 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 122 123 unsigned char calc_ecc[3]; 123 124 int ret; 124 125 125 - __nand_calculate_ecc(error_data, size, calc_ecc, 126 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 127 - ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size, 128 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 126 + ecc_sw_hamming_calculate(error_data, size, calc_ecc, sm_order); 127 + ret = ecc_sw_hamming_correct(error_data, error_ecc, calc_ecc, size, 128 + sm_order); 129 129 if (ret == 0 && !memcmp(correct_data, error_data, size)) 130 130 return 0; 131 131 ··· 149 149 static int single_bit_error_correct(void *error_data, void *error_ecc, 150 150 void *correct_data, const size_t size) 151 151 { 152 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 152 153 unsigned char calc_ecc[3]; 153 154 int ret; 154 155 155 - __nand_calculate_ecc(error_data, size, calc_ecc, 156 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 157 - ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size, 158 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 156 + ecc_sw_hamming_calculate(error_data, size, calc_ecc, sm_order); 157 + ret = ecc_sw_hamming_correct(error_data, error_ecc, calc_ecc, size, 158 + sm_order); 159 159 if (ret == 1 && !memcmp(correct_data, error_data, size)) 160 160 return 0; 161 161 ··· 186 186 static int double_bit_error_detect(void *error_data, void *error_ecc, 187 187 void *correct_data, const size_t size) 188 188 { 189 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 189 190 unsigned char calc_ecc[3]; 190 191 int ret; 191 192 192 - __nand_calculate_ecc(error_data, size, calc_ecc, 193 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 194 - ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size, 195 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 193 + ecc_sw_hamming_calculate(error_data, size, calc_ecc, sm_order); 194 + ret = ecc_sw_hamming_correct(error_data, error_ecc, calc_ecc, size, 195 + sm_order); 196 196 197 197 return (ret == -EBADMSG) ? 0 : -EINVAL; 198 198 } ··· 248 248 249 249 static int nand_ecc_test_run(const size_t size) 250 250 { 251 + bool sm_order = IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC); 251 252 int i; 252 253 int err = 0; 253 254 void *error_data; ··· 267 266 } 268 267 269 268 prandom_bytes(correct_data, size); 270 - __nand_calculate_ecc(correct_data, size, correct_ecc, 271 - IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)); 272 - 269 + ecc_sw_hamming_calculate(correct_data, size, correct_ecc, sm_order); 273 270 for (i = 0; i < ARRAY_SIZE(nand_ecc_test); i++) { 274 271 nand_ecc_test[i].prepare(error_data, error_ecc, 275 272 correct_data, correct_ecc, size);
+12 -24
include/linux/mtd/nand-ecc-sw-hamming.h
··· 10 10 #ifndef __MTD_NAND_ECC_SW_HAMMING_H__ 11 11 #define __MTD_NAND_ECC_SW_HAMMING_H__ 12 12 13 - struct nand_chip; 13 + #include <linux/mtd/nand.h> 14 14 15 - /* 16 - * Calculate 3 byte ECC code for eccsize byte block 17 - */ 18 - void __nand_calculate_ecc(const u_char *dat, unsigned int eccsize, 19 - u_char *ecc_code, bool sm_order); 20 - 21 - /* 22 - * Calculate 3 byte ECC code for 256/512 byte block 23 - */ 24 - int nand_calculate_ecc(struct nand_chip *chip, const u_char *dat, 25 - u_char *ecc_code); 26 - 27 - /* 28 - * Detect and correct a 1 bit error for eccsize byte block 29 - */ 30 - int __nand_correct_data(u_char *dat, u_char *read_ecc, u_char *calc_ecc, 31 - unsigned int eccsize, bool sm_order); 32 - 33 - /* 34 - * Detect and correct a 1 bit error for 256/512 byte block 35 - */ 36 - int nand_correct_data(struct nand_chip *chip, u_char *dat, u_char *read_ecc, 37 - u_char *calc_ecc); 15 + int ecc_sw_hamming_calculate(const unsigned char *buf, unsigned int step_size, 16 + unsigned char *code, bool sm_order); 17 + int nand_ecc_sw_hamming_calculate(struct nand_device *nand, 18 + const unsigned char *buf, 19 + unsigned char *code); 20 + int ecc_sw_hamming_correct(unsigned char *buf, unsigned char *read_ecc, 21 + unsigned char *calc_ecc, unsigned int step_size, 22 + bool sm_order); 23 + int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf, 24 + unsigned char *read_ecc, 25 + unsigned char *calc_ecc); 38 26 39 27 #endif /* __MTD_NAND_ECC_SW_HAMMING_H__ */
+7
include/linux/mtd/rawnand.h
··· 1301 1301 return 0; 1302 1302 } 1303 1303 1304 + int rawnand_sw_hamming_calculate(struct nand_chip *chip, 1305 + const unsigned char *buf, 1306 + unsigned char *code); 1307 + int rawnand_sw_hamming_correct(struct nand_chip *chip, 1308 + unsigned char *buf, 1309 + unsigned char *read_ecc, 1310 + unsigned char *calc_ecc); 1304 1311 int rawnand_sw_bch_init(struct nand_chip *chip); 1305 1312 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf, 1306 1313 unsigned char *read_ecc, unsigned char *calc_ecc);