tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (32 commits)
MIPS: Wire up accept4 syscall.
MIPS: VPE: Delete unused function get_tc_unused().
MIPS: VPE: Fix bogus indentation.
MIPS: VPE: Make various functions static.
MIPS: VPE: Free relocation chain on error.
MIPS: VPE: Fix compiler warning.
MIPS: Module: Make error messages unique.
MIPS: Octeon: Run IPI code with interrupts disabled.
MIPS: Jazz: Fix read buffer overflow
MIPS: Use DIV_ROUND_CLOSEST
MIPS: MTX-1: Request button GPIO before setting its direction
MIPS: AR7: Override CFLAGS with -Werror
MIPS: AR7: Remove unused tnetd7200_get_clock function
MIPS: AR7: Use DMA_BIT_MASK(nn) instead of deprecated DMA_nnBIT_MASK
MIPS: AR7: Fix build failures when CONFIG_SERIAL_8250 is not enabled
MIPS: Fix read buffer overflow
MIPS: AR7: Fix build warning on memory.c
MIPS: Octeon PCIe: Make hardware and software bus numbers match.
MIPS: RBTX4939: Fix IOC pin-enable register updating
MIPS: Simplify and correct interrupt handling for MSP4200
...

Linus Torvalds 90bc1a65 6ce90c43

+121 -191
unified split
+12 -2
arch/mips/alchemy/mtx-1/platform.c
··· 1 1 /* 2 2 * MTX-1 platform devices registration 3 3 * 4 - * Copyright (C) 2007, Florian Fainelli <florian@openwrt.org> 4 + * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org> 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify 7 7 * it under the terms of the GNU General Public License as published by ··· 142 142 143 143 static int __init mtx1_register_devices(void) 144 144 { 145 - gpio_direction_input(207); 145 + int rc; 146 + 147 + rc = gpio_request(mtx1_gpio_button[0].gpio, 148 + mtx1_gpio_button[0].desc); 149 + if (rc < 0) { 150 + printk(KERN_INFO "mtx1: failed to request %d\n", 151 + mtx1_gpio_button[0].gpio); 152 + goto out; 153 + } 154 + gpio_direction_input(mtx1_gpio_button[0].gpio); 155 + out: 146 156 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); 147 157 } 148 158
+1
arch/mips/ar7/Makefile
··· 8 8 platform.o \ 9 9 gpio.o \ 10 10 clock.o 11 + EXTRA_CFLAGS += -Werror
-13
arch/mips/ar7/clock.c
··· 264 264 iounmap(bootcr); 265 265 } 266 266 267 - static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock, 268 - u32 *bootcr, u32 bus_clock) 269 - { 270 - int divisor = ((readl(&clock->prediv) & 0x1f) + 1) * 271 - ((readl(&clock->postdiv) & 0x1f) + 1); 272 - 273 - if (*bootcr & BOOT_PLL_BYPASS) 274 - return base / divisor; 275 - 276 - return base * ((readl(&clock->mul) & 0xf) + 1) / divisor; 277 - } 278 - 279 - 280 267 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, 281 268 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) 282 269 {
+1 -1
arch/mips/ar7/memory.c
··· 52 52 size <<= 1; 53 53 } while (size < (64 << 20)); 54 54 55 - writel(tmpaddr, &addr); 55 + writel((u32)tmpaddr, &addr); 56 56 57 57 return size; 58 58 }
+5 -5
arch/mips/ar7/platform.c
··· 28 28 #include <linux/serial_8250.h> 29 29 #include <linux/ioport.h> 30 30 #include <linux/io.h> 31 - #include <linux/version.h> 32 31 #include <linux/vlynq.h> 33 32 #include <linux/leds.h> 34 33 #include <linux/string.h> ··· 242 243 .num_resources = 1, 243 244 }; 244 245 245 - static u64 cpmac_dma_mask = DMA_32BIT_MASK; 246 + static u64 cpmac_dma_mask = DMA_BIT_MASK(32); 246 247 static struct platform_device cpmac_low = { 247 248 .id = 0, 248 249 .name = "cpmac", 249 250 .dev = { 250 251 .dma_mask = &cpmac_dma_mask, 251 - .coherent_dma_mask = DMA_32BIT_MASK, 252 + .coherent_dma_mask = DMA_BIT_MASK(32), 252 253 .platform_data = &cpmac_low_data, 253 254 }, 254 255 .resource = cpmac_low_res, ··· 260 261 .name = "cpmac", 261 262 .dev = { 262 263 .dma_mask = &cpmac_dma_mask, 263 - .coherent_dma_mask = DMA_32BIT_MASK, 264 + .coherent_dma_mask = DMA_BIT_MASK(32), 264 265 .platform_data = &cpmac_high_data, 265 266 }, 266 267 .resource = cpmac_high_res, ··· 480 481 static int __init ar7_register_devices(void) 481 482 { 482 483 int res; 484 + #ifdef CONFIG_SERIAL_8250 483 485 static struct uart_port uart_port[2]; 484 486 485 487 memset(uart_port, 0, sizeof(struct uart_port) * 2); ··· 512 512 if (res) 513 513 return res; 514 514 } 515 - 515 + #endif /* CONFIG_SERIAL_8250 */ 516 516 res = platform_device_register(&physmap_flash); 517 517 if (res) 518 518 return res;
+1 -1
arch/mips/ar7/prom.c
··· 144 144 { 145 145 int i; 146 146 147 - for (i = 0; i < sizeof(psp_var_map); i++) 147 + for (i = 0; i < ARRAY_SIZE(psp_var_map); i++) 148 148 if (psp_var_map[i].num == num) 149 149 return psp_var_map[i].value; 150 150
-1
arch/mips/ar7/setup.c
··· 15 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 17 */ 18 - #include <linux/version.h> 19 18 #include <linux/init.h> 20 19 #include <linux/ioport.h> 21 20 #include <linux/pm.h>
+2 -2
arch/mips/cavium-octeon/smp.c
··· 194 194 void octeon_prepare_cpus(unsigned int max_cpus) 195 195 { 196 196 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); 197 - if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED, 197 + if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, 198 198 "mailbox0", mailbox_interrupt)) { 199 199 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); 200 200 } 201 - if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED, 201 + if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED, 202 202 "mailbox1", mailbox_interrupt)) { 203 203 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); 204 204 }
-2
arch/mips/dec/ecc-berr.c
··· 1 1 /* 2 - * linux/arch/mips/dec/ecc-berr.c 3 - * 4 2 * Bus error event handling code for systems equipped with ECC 5 3 * handling logic, i.e. DECstation/DECsystem 5000/200 (KN02), 6 4 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
-2
arch/mips/dec/int-handler.S
··· 1 1 /* 2 - * arch/mips/dec/int-handler.S 3 - * 4 2 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 5 3 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki 6 4 *
-2
arch/mips/dec/ioasic-irq.c
··· 1 1 /* 2 - * linux/arch/mips/dec/ioasic-irq.c 3 - * 4 2 * DEC I/O ASIC interrupts. 5 3 * 6 4 * Copyright (c) 2002, 2003 Maciej W. Rozycki
-2
arch/mips/dec/kn01-berr.c
··· 1 1 /* 2 - * linux/arch/mips/dec/kn01-berr.c 3 - * 4 2 * Bus error event handling code for DECstation/DECsystem 3100 5 3 * and 2100 (KN01) systems equipped with parity error detection 6 4 * logic.
-2
arch/mips/dec/kn02-irq.c
··· 1 1 /* 2 - * linux/arch/mips/dec/kn02-irq.c 3 - * 4 2 * DECstation 5000/200 (KN02) Control and Status Register 5 3 * interrupts. 6 4 *
-2
arch/mips/dec/kn02xa-berr.c
··· 1 1 /* 2 - * linux/arch/mips/dec/kn02xa-berr.c 3 - * 4 2 * Bus error event handling code for 5000-series systems equipped 5 3 * with parity error detection logic, i.e. DECstation/DECsystem 6 4 * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
-2
arch/mips/dec/prom/call_o32.S
··· 1 1 /* 2 - * arch/mips/dec/prom/call_o32.S 3 - * 4 2 * O32 interface for the 64 (or N32) ABI. 5 3 * 6 4 * Copyright (C) 2002 Maciej W. Rozycki
-2
arch/mips/dec/prom/console.c
··· 1 1 /* 2 - * arch/mips/dec/prom/console.c 3 - * 4 2 * DECstation PROM-based early console support. 5 3 * 6 4 * Copyright (C) 2004, 2007 Maciej W. Rozycki
-2
arch/mips/dec/time.c
··· 1 1 /* 2 - * linux/arch/mips/dec/time.c 3 - * 4 2 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 3 * Copyright (C) 2000, 2003 Maciej W. Rozycki 6 4 *
-3
arch/mips/emma/common/Makefile
··· 1 1 # 2 - # arch/mips/emma2rh/common/Makefile 3 - # Makefile for the common code of NEC EMMA2RH based board. 4 - # 5 2 # Copyright (C) NEC Electronics Corporation 2005-2006 6 3 # 7 4 # This program is free software; you can redistribute it and/or modify
-3
arch/mips/emma/common/prom.c
··· 1 1 /* 2 - * arch/mips/emma2rh/common/prom.c 3 - * This file is prom file. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/ddb5xxx/common/prom.c
-3
arch/mips/emma/markeins/Makefile
··· 1 1 # 2 - # arch/mips/emma2rh/markeins/Makefile 3 - # Makefile for the common code of NEC EMMA2RH based board. 4 - # 5 2 # Copyright (C) NEC Electronics Corporation 2005-2006 6 3 # 7 4 # This program is free software; you can redistribute it and/or modify
-3
arch/mips/emma/markeins/irq.c
··· 1 1 /* 2 - * arch/mips/emma2rh/markeins/irq.c 3 - * This file defines the irq handler for EMMA2RH. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
-3
arch/mips/emma/markeins/led.c
··· 1 1 /* 2 - * arch/mips/emma2rh/markeins/led.c 3 - * This file defines the led display for Mark-eins. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This program is free software; you can redistribute it and/or modify
-3
arch/mips/emma/markeins/platform.c
··· 1 1 /* 2 - * arch/mips/emma2rh/markeins/platofrm.c 3 - * This file sets up platform devices for EMMA2RH Mark-eins. 4 - * 5 2 * Copyright(C) MontaVista Software Inc, 2006 6 3 * 7 4 * Author: dmitry pervushin <dpervushin@ru.mvista.com>
-3
arch/mips/emma/markeins/setup.c
··· 1 1 /* 2 - * arch/mips/emma2rh/markeins/setup.c 3 - * This file is setup for EMMA2RH Mark-eins. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
-2
arch/mips/fw/lib/call_o32.S
··· 1 1 /* 2 - * arch/mips/dec/prom/call_o32.S 3 - * 4 2 * O32 interface for the 64 (or N32) ABI. 5 3 * 6 4 * Copyright (C) 2002 Maciej W. Rozycki
-3
arch/mips/include/asm/emma/emma2rh.h
··· 1 1 /* 2 - * arch/mips/include/asm/emma/emma2rh.h 3 - * This file is EMMA2RH common header. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2005-2006 6 3 * 7 4 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
-3
arch/mips/include/asm/emma/markeins.h
··· 1 1 /* 2 - * include/asm-mips/emma2rh/markeins.h 3 - * This file is EMMA2RH board depended header. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2005-2006 6 3 * 7 4 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
+1 -1
arch/mips/include/asm/gic.h
··· 20 20 #define GIC_TRIG_EDGE 1 21 21 #define GIC_TRIG_LEVEL 0 22 22 23 - #if CONFIG_SMP 23 + #ifdef CONFIG_SMP 24 24 #define GIC_NUM_INTRS (24 + NR_CPUS * 2) 25 25 #else 26 26 #define GIC_NUM_INTRS 32
+2
arch/mips/include/asm/pmc-sierra/msp71xx/war.h
··· 23 23 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ 24 24 defined(CONFIG_PMC_MSP7120_FPGA) 25 25 #define MIPS34K_MISSED_ITLB_WAR 1 26 + #else 27 + #define MIPS34K_MISSED_ITLB_WAR 0 26 28 #endif 27 29 28 30 #endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
+3 -2
arch/mips/include/asm/processor.h
··· 311 311 312 312 unsigned long get_wchan(struct task_struct *p); 313 313 314 - #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32) 315 - #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1) 314 + #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 315 + THREAD_SIZE - 32 - sizeof(struct pt_regs)) 316 + #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 316 317 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 317 318 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 318 319 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
+9 -6
arch/mips/include/asm/unistd.h
··· 354 354 #define __NR_pwritev (__NR_Linux + 331) 355 355 #define __NR_rt_tgsigqueueinfo (__NR_Linux + 332) 356 356 #define __NR_perf_counter_open (__NR_Linux + 333) 357 + #define __NR_accept4 (__NR_Linux + 334) 357 358 358 359 /* 359 360 * Offset of the last Linux o32 flavoured syscall 360 361 */ 361 - #define __NR_Linux_syscalls 333 362 + #define __NR_Linux_syscalls 334 362 363 363 364 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 364 365 365 366 #define __NR_O32_Linux 4000 366 - #define __NR_O32_Linux_syscalls 333 367 + #define __NR_O32_Linux_syscalls 334 367 368 368 369 #if _MIPS_SIM == _MIPS_SIM_ABI64 369 370 ··· 665 664 #define __NR_pwritev (__NR_Linux + 290) 666 665 #define __NR_rt_tgsigqueueinfo (__NR_Linux + 291) 667 666 #define __NR_perf_counter_open (__NR_Linux + 292) 667 + #define __NR_accept4 (__NR_Linux + 293) 668 668 669 669 /* 670 670 * Offset of the last Linux 64-bit flavoured syscall 671 671 */ 672 - #define __NR_Linux_syscalls 292 672 + #define __NR_Linux_syscalls 293 673 673 674 674 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 675 675 676 676 #define __NR_64_Linux 5000 677 - #define __NR_64_Linux_syscalls 292 677 + #define __NR_64_Linux_syscalls 293 678 678 679 679 #if _MIPS_SIM == _MIPS_SIM_NABI32 680 680 ··· 980 978 #define __NR_pwritev (__NR_Linux + 294) 981 979 #define __NR_rt_tgsigqueueinfo (__NR_Linux + 295) 982 980 #define __NR_perf_counter_open (__NR_Linux + 296) 981 + #define __NR_accept4 (__NR_Linux + 297) 983 982 984 983 /* 985 984 * Offset of the last N32 flavoured syscall 986 985 */ 987 - #define __NR_Linux_syscalls 296 986 + #define __NR_Linux_syscalls 297 988 987 989 988 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 990 989 991 990 #define __NR_N32_Linux 6000 992 - #define __NR_N32_Linux_syscalls 296 991 + #define __NR_N32_Linux_syscalls 297 993 992 994 993 #ifdef __KERNEL__ 995 994
+1 -1
arch/mips/jazz/jazzdma.c
··· 190 190 return -1; 191 191 } 192 192 193 - while (pgtbl[i].owner == laddr && i < VDMA_PGTBL_ENTRIES) { 193 + while (i < VDMA_PGTBL_ENTRIES && pgtbl[i].owner == laddr) { 194 194 pgtbl[i].owner = VDMA_PAGE_EMPTY; 195 195 i++; 196 196 }
+2 -1
arch/mips/kernel/head.S
··· 188 188 189 189 MTC0 zero, CP0_CONTEXT # clear context register 190 190 PTR_LA $28, init_thread_union 191 - PTR_LI sp, _THREAD_SIZE - 32 191 + /* Set the SP after an empty pt_regs. */ 192 + PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 192 193 PTR_ADDU sp, $28 193 194 set_saved_sp sp, t0, t1 194 195 PTR_SUBU sp, 4 * SZREG # init stack pointer
-2
arch/mips/kernel/irq_txx9.c
··· 1 1 /* 2 - * linux/arch/mips/kernel/irq_txx9.c 3 - * 4 2 * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c, 5 3 * linux/arch/mips/tx4927/common/tx4927_irq.c, 6 4 * linux/arch/mips/tx4938/common/irq.c
+7 -5
arch/mips/kernel/module.c
··· 98 98 static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) 99 99 { 100 100 if (v % 4) { 101 - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); 101 + pr_err("module %s: dangerous R_MIPS_26 REL relocation\n", 102 + me->name); 102 103 return -ENOEXEC; 103 104 } 104 105 ··· 119 118 static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v) 120 119 { 121 120 if (v % 4) { 122 - printk(KERN_ERR "module %s: dangerous relocation\n", me->name); 121 + pr_err("module %s: dangerous R_MIPS_26 RELArelocation\n", 122 + me->name); 123 123 return -ENOEXEC; 124 124 } 125 125 ··· 224 222 return 0; 225 223 226 224 out_danger: 227 - printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name); 225 + pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name); 228 226 229 227 return -ENOEXEC; 230 228 } ··· 303 301 /* This is the symbol it is referring to */ 304 302 sym = (Elf_Sym *)sechdrs[symindex].sh_addr 305 303 + ELF_MIPS_R_SYM(rel[i]); 306 - if (!sym->st_value) { 304 + if (IS_ERR_VALUE(sym->st_value)) { 307 305 /* Ignore unresolved weak symbol */ 308 306 if (ELF_ST_BIND(sym->st_info) == STB_WEAK) 309 307 continue; ··· 343 341 /* This is the symbol it is referring to */ 344 342 sym = (Elf_Sym *)sechdrs[symindex].sh_addr 345 343 + ELF_MIPS_R_SYM(rel[i]); 346 - if (!sym->st_value) { 344 + if (IS_ERR_VALUE(sym->st_value)) { 347 345 /* Ignore unresolved weak symbol */ 348 346 if (ELF_ST_BIND(sym->st_info) == STB_WEAK) 349 347 continue;
-2
arch/mips/kernel/proc.c
··· 1 1 /* 2 - * linux/arch/mips/kernel/proc.c 3 - * 4 2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle 5 3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc. 6 4 * Copyright (C) 2004 Maciej W. Rozycki
+3 -1
arch/mips/kernel/process.c
··· 115 115 { 116 116 struct thread_info *ti = task_thread_info(p); 117 117 struct pt_regs *childregs; 118 - long childksp; 118 + unsigned long childksp; 119 119 p->set_child_tid = p->clear_child_tid = NULL; 120 120 121 121 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; ··· 132 132 133 133 /* set up new TSS. */ 134 134 childregs = (struct pt_regs *) childksp - 1; 135 + /* Put the stack after the struct pt_regs. */ 136 + childksp = (unsigned long) childregs; 135 137 *childregs = *regs; 136 138 childregs->regs[7] = 0; /* Clear error flag */ 137 139
+1
arch/mips/kernel/scall32-o32.S
··· 654 654 sys sys_pwritev 6 655 655 sys sys_rt_tgsigqueueinfo 4 656 656 sys sys_perf_counter_open 5 657 + sys sys_accept4 4 657 658 .endm 658 659 659 660 /* We pre-compute the number of _instruction_ bytes needed to
+1
arch/mips/kernel/scall64-64.S
··· 491 491 PTR sys_pwritev /* 5390 */ 492 492 PTR sys_rt_tgsigqueueinfo 493 493 PTR sys_perf_counter_open 494 + PTR sys_accept4 494 495 .size sys_call_table,.-sys_call_table
+1
arch/mips/kernel/scall64-n32.S
··· 417 417 PTR sys_pwritev 418 418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */ 419 419 PTR sys_perf_counter_open 420 + PTR sys_accept4 420 421 .size sysn32_call_table,.-sysn32_call_table
+1
arch/mips/kernel/scall64-o32.S
··· 537 537 PTR compat_sys_pwritev 538 538 PTR compat_sys_rt_tgsigqueueinfo 539 539 PTR sys_perf_counter_open 540 + PTR sys_accept4 540 541 .size sys_call_table,.-sys_call_table
+8 -5
arch/mips/kernel/smtc.c
··· 465 465 smtc_configure_tlb(); 466 466 467 467 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { 468 - /* 469 - * Set the MVP bits. 470 - */ 471 - settc(tc); 472 - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); 468 + if (tcpervpe[vpe] == 0) 469 + continue; 473 470 if (vpe != 0) 474 471 printk(", "); 475 472 printk("VPE %d: TC", vpe); ··· 484 487 tc++; 485 488 } 486 489 if (vpe != 0) { 490 + /* 491 + * Allow this VPE to control others. 492 + */ 493 + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | 494 + VPECONF0_MVP); 495 + 487 496 /* 488 497 * Clear any stale software interrupts from VPE's Cause 489 498 */
-2
arch/mips/kernel/stacktrace.c
··· 1 1 /* 2 - * arch/mips/kernel/stacktrace.c 3 - * 4 2 * Stack trace management functions 5 3 * 6 4 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
+23 -26
arch/mips/kernel/vpe.c
··· 73 73 static const int minor = 1; /* fixed for now */ 74 74 75 75 #ifdef CONFIG_MIPS_APSP_KSPD 76 - static struct kspd_notifications kspd_events; 76 + static struct kspd_notifications kspd_events; 77 77 static int kspd_events_reqd = 0; 78 78 #endif 79 79 ··· 155 155 }; 156 156 157 157 static void release_progmem(void *ptr); 158 - extern void save_gp_address(unsigned int secbase, unsigned int rel); 159 158 160 159 /* get the vpe associated with this minor */ 161 - struct vpe *get_vpe(int minor) 160 + static struct vpe *get_vpe(int minor) 162 161 { 163 162 struct vpe *v; 164 163 ··· 173 174 } 174 175 175 176 /* get the vpe associated with this minor */ 176 - struct tc *get_tc(int index) 177 + static struct tc *get_tc(int index) 177 178 { 178 179 struct tc *t; 179 180 ··· 185 186 return NULL; 186 187 } 187 188 188 - struct tc *get_tc_unused(void) 189 - { 190 - struct tc *t; 191 - 192 - list_for_each_entry(t, &vpecontrol.tc_list, list) { 193 - if (t->state == TC_STATE_UNUSED) 194 - return t; 195 - } 196 - 197 - return NULL; 198 - } 199 - 200 189 /* allocate a vpe and associate it with this minor (or index) */ 201 - struct vpe *alloc_vpe(int minor) 190 + static struct vpe *alloc_vpe(int minor) 202 191 { 203 192 struct vpe *v; 204 193 ··· 203 216 } 204 217 205 218 /* allocate a tc. At startup only tc0 is running, all other can be halted. */ 206 - struct tc *alloc_tc(int index) 219 + static struct tc *alloc_tc(int index) 207 220 { 208 221 struct tc *tc; 209 222 ··· 219 232 } 220 233 221 234 /* clean up and free everything */ 222 - void release_vpe(struct vpe *v) 235 + static void release_vpe(struct vpe *v) 223 236 { 224 237 list_del(&v->list); 225 238 if (v->load_addr) ··· 227 240 kfree(v); 228 241 } 229 242 230 - void dump_mtregs(void) 243 + static void dump_mtregs(void) 231 244 { 232 245 unsigned long val; 233 246 ··· 314 327 || (s->sh_flags & masks[m][1]) 315 328 || s->sh_entsize != ~0UL) 316 329 continue; 317 - s->sh_entsize = get_offset(&mod->core_size, s); 330 + s->sh_entsize = 331 + get_offset((unsigned long *)&mod->core_size, s); 318 332 } 319 333 320 334 if (m == 0) ··· 449 461 { 450 462 unsigned long insnlo = *location; 451 463 Elf32_Addr val, vallo; 464 + struct mips_hi16 *l, *next; 452 465 453 466 /* Sign extend the addend we extract from the lo insn. */ 454 467 vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; 455 468 456 469 if (mips_hi16_list != NULL) { 457 - struct mips_hi16 *l; 458 470 459 471 l = mips_hi16_list; 460 472 while (l != NULL) { 461 - struct mips_hi16 *next; 462 473 unsigned long insn; 463 474 464 475 /* ··· 467 480 printk(KERN_DEBUG "VPE loader: " 468 481 "apply_r_mips_lo16/hi16: \t" 469 482 "inconsistent value information\n"); 470 - return -ENOEXEC; 483 + goto out_free; 471 484 } 472 485 473 486 /* ··· 505 518 *location = insnlo; 506 519 507 520 return 0; 521 + 522 + out_free: 523 + while (l != NULL) { 524 + next = l->next; 525 + kfree(l); 526 + l = next; 527 + } 528 + mips_hi16_list = NULL; 529 + 530 + return -ENOEXEC; 508 531 } 509 532 510 533 static int (*reloc_handlers[]) (struct module *me, uint32_t *location, ··· 538 541 [R_MIPS_PC16] = "MIPS_PC16" 539 542 }; 540 543 541 - int apply_relocations(Elf32_Shdr *sechdrs, 544 + static int apply_relocations(Elf32_Shdr *sechdrs, 542 545 const char *strtab, 543 546 unsigned int symindex, 544 547 unsigned int relsec, ··· 583 586 return 0; 584 587 } 585 588 586 - void save_gp_address(unsigned int secbase, unsigned int rel) 589 + static inline void save_gp_address(unsigned int secbase, unsigned int rel) 587 590 { 588 591 gp_addr = secbase + rel; 589 592 gp_offs = gp_addr - (secbase & 0xffff0000);
+6 -6
arch/mips/mipssim/sim_time.c
··· 89 89 if (cpu_has_veic) { 90 90 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 91 91 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 92 - } else { 93 - #endif 94 - { 95 - if (cpu_has_vint) 96 - set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 97 - mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 92 + 93 + return mips_cpu_timer_irq; 98 94 } 95 + #endif 96 + if (cpu_has_vint) 97 + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 98 + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 99 99 100 100 return mips_cpu_timer_irq; 101 101 }
+2 -2
arch/mips/mm/c-octeon.c
··· 289 289 } 290 290 291 291 /** 292 - * Called when the the exception is not recoverable 292 + * Called when the the exception is recoverable 293 293 */ 294 294 295 295 asmlinkage void cache_parity_error_octeon_recoverable(void) ··· 298 298 } 299 299 300 300 /** 301 - * Called when the the exception is recoverable 301 + * Called when the the exception is not recoverable 302 302 */ 303 303 304 304 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
+5 -1
arch/mips/mm/extable.c
··· 1 1 /* 2 - * linux/arch/mips/mm/extable.c 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 1997, 99, 2001 - 2004 Ralf Baechle <ralf@linux-mips.org> 3 7 */ 4 8 #include <linux/module.h> 5 9 #include <linux/spinlock.h>
+1
arch/mips/mm/fault.c
··· 171 171 * We ran out of memory, call the OOM killer, and return the userspace 172 172 * (which will retry the fault, or kill us if we got oom-killed). 173 173 */ 174 + up_read(&mm->mmap_sem); 174 175 pagefault_out_of_memory(); 175 176 return; 176 177
+1 -1
arch/mips/mti-malta/malta-int.c
··· 331 331 .flags = IRQF_DISABLED|IRQF_PERCPU, 332 332 .name = "IPI_call" 333 333 }; 334 + #endif /* CONFIG_MIPS_MT_SMP */ 334 335 335 336 static int gic_resched_int_base; 336 337 static int gic_call_int_base; ··· 347 346 { 348 347 return GIC_RESCHED_INT(cpu); 349 348 } 350 - #endif /* CONFIG_MIPS_MT_SMP */ 351 349 352 350 static struct irqaction i8259irq = { 353 351 .handler = no_action,
+1 -1
arch/mips/nxp/pnx8550/common/time.c
··· 138 138 * HZ timer interrupts per second. 139 139 */ 140 140 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); 141 - cpj = (mips_hpt_frequency + HZ / 2) / HZ; 141 + cpj = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ); 142 142 write_c0_count(0); 143 143 timer_ack(); 144 144
-3
arch/mips/pci/fixup-emma2rh.c
··· 1 1 /* 2 - * arch/mips/pci/fixup-emma2rh.c 3 - * This file defines the PCI configration. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
-2
arch/mips/pci/fixup-sb1250.c
··· 1 1 /* 2 - * arch/mips/pci/fixup-sb1250.c 3 - * 4 2 * Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved. 5 3 * Author: Maciej W. Rozycki <macro@mips.com> 6 4 *
-3
arch/mips/pci/ops-emma2rh.c
··· 1 1 /* 2 - * arch/mips/pci/ops-emma2rh.c 3 - * This file defines the PCI operation for EMMA2RH. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/pci/ops-vr41xx.c
-3
arch/mips/pci/pci-emma2rh.c
··· 1 1 /* 2 - * arch/mips/pci/pci-emma2rh.c 3 - * This file defines the PCI configration. 4 - * 5 2 * Copyright (C) NEC Electronics Corporation 2004-2006 6 3 * 7 4 * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
-2
arch/mips/pci/pci-tx4927.c
··· 1 1 /* 2 - * linux/arch/mips/pci/pci-tx4927.c 3 - * 4 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 5 3 * and RBTX49xx patch from CELF patch archive. 6 4 *
-2
arch/mips/pci/pci-tx4938.c
··· 1 1 /* 2 - * linux/arch/mips/pci/pci-tx4938.c 3 - * 4 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 5 3 * and RBTX49xx patch from CELF patch archive. 6 4 *
-2
arch/mips/pci/pci-tx4939.c
··· 1 1 /* 2 - * linux/arch/mips/pci/pci-tx4939.c 3 - * 4 2 * Based on linux/arch/mips/txx9/rbtx4939/setup.c, 5 3 * and RBTX49xx patch from CELF patch archive. 6 4 *
+17 -14
arch/mips/pci/pcie-octeon.c
··· 1040 1040 int bus_number = bus->number; 1041 1041 1042 1042 /* 1043 - * We need to force the bus number to be zero on the root 1044 - * bus. Linux numbers the 2nd root bus to start after all 1045 - * buses on root 0. 1043 + * For the top level bus make sure our hardware bus number 1044 + * matches the software one. 1046 1045 */ 1047 - if (bus->parent == NULL) 1048 - bus_number = 0; 1046 + if (bus->parent == NULL) { 1047 + union cvmx_pciercx_cfg006 pciercx_cfg006; 1048 + pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, 1049 + CVMX_PCIERCX_CFG006(pcie_port)); 1050 + if (pciercx_cfg006.s.pbnum != bus_number) { 1051 + pciercx_cfg006.s.pbnum = bus_number; 1052 + pciercx_cfg006.s.sbnum = bus_number; 1053 + pciercx_cfg006.s.subbnum = bus_number; 1054 + cvmx_pcie_cfgx_write(pcie_port, 1055 + CVMX_PCIERCX_CFG006(pcie_port), 1056 + pciercx_cfg006.u32); 1057 + } 1058 + } 1049 1059 1050 1060 /* 1051 1061 * PCIe only has a single device connected to Octeon. It is 1052 1062 * always device ID 0. Don't bother doing reads for other 1053 1063 * device IDs on the first segment. 1054 1064 */ 1055 - if ((bus_number == 0) && (devfn >> 3 != 0)) 1065 + if ((bus->parent == NULL) && (devfn >> 3 != 0)) 1056 1066 return PCIBIOS_FUNC_NOT_SUPPORTED; 1057 1067 1058 1068 /* ··· 1080 1070 * bridge only respondes to device ID 0, function 1081 1071 * 0-1 1082 1072 */ 1083 - if ((bus_number == 0) && (devfn >= 2)) 1073 + if ((bus->parent == NULL) && (devfn >= 2)) 1084 1074 return PCIBIOS_FUNC_NOT_SUPPORTED; 1085 1075 /* 1086 1076 * The PCI-X slots are device ID 2,3. Choose one of ··· 1177 1167 int size, u32 val) 1178 1168 { 1179 1169 int bus_number = bus->number; 1180 - /* 1181 - * We need to force the bus number to be zero on the root 1182 - * bus. Linux numbers the 2nd root bus to start after all 1183 - * busses on root 0. 1184 - */ 1185 - if (bus->parent == NULL) 1186 - bus_number = 0; 1187 1170 1188 1171 switch (size) { 1189 1172 case 4:
-2
arch/mips/pmc-sierra/msp71xx/gpio.c
··· 1 1 /* 2 - * @file /arch/mips/pmc-sierra/msp71xx/gpio.c 3 - * 4 2 * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two 5 3 * types of registers. The data register sets the output level when in output 6 4 * mode and when in input mode will contain the value at the input. The config
-2
arch/mips/pmc-sierra/msp71xx/gpio_extended.c
··· 1 1 /* 2 - * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c 3 - * 4 2 * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is 5 3 * a set of hardware registers that have no need for explicit locking as 6 4 * it is handled by unique method of writing individual set/clr bits.
+2 -10
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
··· 45 45 */ 46 46 static inline void ack_msp_slp_irq(unsigned int irq) 47 47 { 48 - mask_slp_irq(irq); 49 - 50 - /* 51 - * only really necessary for 18, 16-14 and sometimes 3:0 (since 52 - * these can be edge sensitive) but it doesn't hurt for the others. 53 - */ 54 - 55 48 /* check for PER interrupt range */ 56 49 if (irq < MSP_PER_INTBASE) 57 50 *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE)); ··· 55 62 static struct irq_chip msp_slp_irq_controller = { 56 63 .name = "MSP_SLP", 57 64 .ack = ack_msp_slp_irq, 58 - .mask = ack_msp_slp_irq, 59 - .mask_ack = ack_msp_slp_irq, 65 + .mask = mask_msp_slp_irq, 60 66 .unmask = unmask_msp_slp_irq, 61 67 }; 62 68 ··· 71 79 72 80 /* initialize all the IRQ descriptors */ 73 81 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) 74 - set_irq_chip_and_handler(i, &msp_slp_irq_controller 82 + set_irq_chip_and_handler(i, &msp_slp_irq_controller, 75 83 handle_level_irq); 76 84 } 77 85
-2
arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
··· 1 1 /* 2 - * arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c 3 - * 4 2 * Copyright (C) 2003 PMC-Sierra Inc. 5 3 * Author: Manish Lachwani (lachwani@pmc-sierra.com) 6 4 *
-2
arch/mips/sibyte/swarm/swarm-i2c.c
··· 1 1 /* 2 - * arch/mips/sibyte/swarm/swarm-i2c.c 3 - * 4 2 * Broadcom BCM91250A (SWARM), etc. I2C platform setup. 5 3 * 6 4 * Copyright (c) 2008 Maciej W. Rozycki
-2
arch/mips/txx9/generic/mem_tx4927.c
··· 1 1 /* 2 - * linux/arch/mips/txx9/generic/mem_tx4927.c 3 - * 4 2 * common tx4927 memory interface 5 3 * 6 4 * Author: MontaVista Software, Inc.
-2
arch/mips/txx9/generic/setup.c
··· 1 1 /* 2 - * linux/arch/mips/txx9/generic/setup.c 3 - * 4 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 5 3 * and RBTX49xx patch from CELF patch archive. 6 4 *
+1 -1
arch/mips/txx9/rbtx4939/setup.c
··· 512 512 rbtx4939_ebusc_setup(); 513 513 /* always enable ATA0 */ 514 514 txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE); 515 - rbtx4939_update_ioc_pen(); 516 515 if (txx9_master_clock == 0) 517 516 txx9_master_clock = 20000000; 518 517 tx4939_setup(); 518 + rbtx4939_update_ioc_pen(); 519 519 #ifdef HAVE_RBTX4939_IOSWAB 520 520 ioswabw = rbtx4939_ioswabw; 521 521 __mem_ioswabw = rbtx4939_mem_ioswabw;