tjh.dev
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-1
Documentation/devicetree/bindings/clock/at91-clock.txt
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-1
Documentation/devicetree/bindings/clock/at91-clock.txt
···
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- clocks : shall be the master clock phandle.
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e.g. clocks = <&mck>;
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-
- name: device tree node describing a specific system clock.
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- name: device tree node describing a specific peripheral clock.
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* #clock-cells : from common clock binding; shall be set to 0.
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* reg: peripheral id. See Atmel's datasheets to get a full
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list of peripheral ids.
+4
-4
drivers/clk/at91/clk-peripheral.c
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-4
drivers/clk/at91/clk-peripheral.c
···
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#define PERIPHERAL_RSHIFT_MASK 0x3
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#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
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-
#define PERIPHERAL_MAX_SHIFT 4
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#define PERIPHERAL_MAX_SHIFT 3
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struct clk_peripheral {
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struct clk_hw hw;
···
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return *parent_rate;
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if (periph->range.max) {
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-
for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
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+
for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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cur_rate = *parent_rate >> shift;
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if (cur_rate <= periph->range.max)
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break;
···
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best_diff = cur_rate - rate;
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best_rate = cur_rate;
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-
for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
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+
for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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cur_rate = *parent_rate >> shift;
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if (cur_rate < rate)
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cur_diff = rate - cur_rate;
···
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if (periph->range.max && rate > periph->range.max)
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return -EINVAL;
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-
for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) {
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+
for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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if (parent_rate >> shift == rate) {
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periph->auto_div = false;
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periph->div = shift;
+10
-2
drivers/clk/at91/clk-pll.c
+10
-2
drivers/clk/at91/clk-pll.c
···
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int i = 0;
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/* Check if parent_rate is a valid input rate */
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-
if (parent_rate < characteristics->input.min ||
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-
parent_rate > characteristics->input.max)
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+
if (parent_rate < characteristics->input.min)
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return -ERANGE;
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/*
···
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mindiv = (parent_rate * PLL_MUL_MIN) / rate;
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if (!mindiv)
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mindiv = 1;
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+
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if (parent_rate > characteristics->input.max) {
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tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
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if (tmpdiv > PLL_DIV_MAX)
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return -ERANGE;
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if (tmpdiv > mindiv)
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mindiv = tmpdiv;
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}
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/*
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* Calculate the maximum divider which is limited by PLL register