Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: VF Query RAS Caps from Host if supported

If VF RAS Capability support is enabled, guest is able to
retrieve the real RAS support from the host.

Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: Zhigang Luo <zhigang.luo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Victor Skvortsov and committed by
Alex Deucher
907fec2d 9928509d

+65
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
··· 3453 3453 if (!amdgpu_ras_asic_supported(adev)) 3454 3454 return; 3455 3455 3456 + if (amdgpu_sriov_vf(adev)) { 3457 + if (amdgpu_virt_get_ras_capability(adev)) 3458 + goto init_ras_enabled_flag; 3459 + } 3460 + 3456 3461 /* query ras capability from psp */ 3457 3462 if (amdgpu_psp_get_ras_capability(&adev->psp)) 3458 3463 goto init_ras_enabled_flag;
+53
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
··· 523 523 524 524 adev->unique_id = 525 525 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 526 + adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; 526 527 break; 527 528 default: 528 529 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); ··· 1144 1143 xnack_mode = false; 1145 1144 1146 1145 return xnack_mode; 1146 + } 1147 + 1148 + bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) 1149 + { 1150 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1151 + 1152 + if (!amdgpu_sriov_ras_caps_en(adev)) 1153 + return false; 1154 + 1155 + if (adev->virt.ras_en_caps.bits.block_umc) 1156 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC); 1157 + if (adev->virt.ras_en_caps.bits.block_sdma) 1158 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA); 1159 + if (adev->virt.ras_en_caps.bits.block_gfx) 1160 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX); 1161 + if (adev->virt.ras_en_caps.bits.block_mmhub) 1162 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB); 1163 + if (adev->virt.ras_en_caps.bits.block_athub) 1164 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB); 1165 + if (adev->virt.ras_en_caps.bits.block_pcie_bif) 1166 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF); 1167 + if (adev->virt.ras_en_caps.bits.block_hdp) 1168 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP); 1169 + if (adev->virt.ras_en_caps.bits.block_xgmi_wafl) 1170 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL); 1171 + if (adev->virt.ras_en_caps.bits.block_df) 1172 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF); 1173 + if (adev->virt.ras_en_caps.bits.block_smn) 1174 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN); 1175 + if (adev->virt.ras_en_caps.bits.block_sem) 1176 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM); 1177 + if (adev->virt.ras_en_caps.bits.block_mp0) 1178 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0); 1179 + if (adev->virt.ras_en_caps.bits.block_mp1) 1180 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1); 1181 + if (adev->virt.ras_en_caps.bits.block_fuse) 1182 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE); 1183 + if (adev->virt.ras_en_caps.bits.block_mca) 1184 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA); 1185 + if (adev->virt.ras_en_caps.bits.block_vcn) 1186 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN); 1187 + if (adev->virt.ras_en_caps.bits.block_jpeg) 1188 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG); 1189 + if (adev->virt.ras_en_caps.bits.block_ih) 1190 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH); 1191 + if (adev->virt.ras_en_caps.bits.block_mpio) 1192 + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO); 1193 + 1194 + if (adev->virt.ras_en_caps.bits.poison_propogation_mode) 1195 + con->poison_supported = true; /* Poison is handled by host */ 1196 + 1197 + return true; 1147 1198 }
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
··· 137 137 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 138 138 /* MES info */ 139 139 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 140 + AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 140 141 }; 141 142 142 143 enum AMDGIM_REG_ACCESS_FLAG { ··· 278 277 uint32_t autoload_ucode_id; 279 278 280 279 struct mutex rlcg_reg_lock; 280 + 281 + union amd_sriov_ras_caps ras_en_caps; 281 282 }; 282 283 283 284 struct amdgpu_video_codec_info; ··· 323 320 324 321 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 325 322 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 323 + 324 + #define amdgpu_sriov_ras_caps_en(adev) \ 325 + ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 326 326 327 327 static inline bool is_virtual_machine(void) 328 328 { ··· 390 384 u32 acc_flags, u32 hwip, 391 385 bool write, u32 *rlcg_flag); 392 386 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 387 + bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 393 388 #endif