tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: refactor code to split devcoredump code
Refractor devcoredump code into new files since its
functionality is expanded further and better to slit
and devcoredump to have its own file.
v2: Fix the build failure caught by arm compiler
of implicit function declaration with #ifdef
v3: squash in fix for implicit declaration error
Cc: Ivan Lipski <ivan.lipski@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Sunil Khatri
and committed by
Alex Deucher
9022f01b
b1edfb91
+265
-208
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
···
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81
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
82
82
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
83
83
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
84
-
amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o
84
+
amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o
85
85
86
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amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
87
87
+216
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+216
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright 2024 Advanced Micro Devices, Inc.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the "Software"),
7
+
* to deal in the Software without restriction, including without limitation
8
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
+
* and/or sell copies of the Software, and to permit persons to whom the
10
+
* Software is furnished to do so, subject to the following conditions:
11
+
*
12
+
* The above copyright notice and this permission notice shall be included in
13
+
* all copies or substantial portions of the Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21
+
* OTHER DEALINGS IN THE SOFTWARE.
22
+
*
23
+
*/
24
+
25
+
#include <generated/utsrelease.h>
26
+
#include <linux/devcoredump.h>
27
+
#include "amdgpu_dev_coredump.h"
28
+
29
+
#ifndef CONFIG_DEV_COREDUMP
30
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void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
31
+
struct amdgpu_reset_context *reset_context)
32
+
{
33
+
}
34
+
#else
35
+
36
+
const char *hw_ip_names[MAX_HWIP] = {
37
+
[GC_HWIP] = "GC",
38
+
[HDP_HWIP] = "HDP",
39
+
[SDMA0_HWIP] = "SDMA0",
40
+
[SDMA1_HWIP] = "SDMA1",
41
+
[SDMA2_HWIP] = "SDMA2",
42
+
[SDMA3_HWIP] = "SDMA3",
43
+
[SDMA4_HWIP] = "SDMA4",
44
+
[SDMA5_HWIP] = "SDMA5",
45
+
[SDMA6_HWIP] = "SDMA6",
46
+
[SDMA7_HWIP] = "SDMA7",
47
+
[LSDMA_HWIP] = "LSDMA",
48
+
[MMHUB_HWIP] = "MMHUB",
49
+
[ATHUB_HWIP] = "ATHUB",
50
+
[NBIO_HWIP] = "NBIO",
51
+
[MP0_HWIP] = "MP0",
52
+
[MP1_HWIP] = "MP1",
53
+
[UVD_HWIP] = "UVD/JPEG/VCN",
54
+
[VCN1_HWIP] = "VCN1",
55
+
[VCE_HWIP] = "VCE",
56
+
[VPE_HWIP] = "VPE",
57
+
[DF_HWIP] = "DF",
58
+
[DCE_HWIP] = "DCE",
59
+
[OSSSYS_HWIP] = "OSSSYS",
60
+
[SMUIO_HWIP] = "SMUIO",
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+
[PWR_HWIP] = "PWR",
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[NBIF_HWIP] = "NBIF",
63
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[THM_HWIP] = "THM",
64
+
[CLK_HWIP] = "CLK",
65
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[UMC_HWIP] = "UMC",
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+
[RSMU_HWIP] = "RSMU",
67
+
[XGMI_HWIP] = "XGMI",
68
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[DCI_HWIP] = "DCI",
69
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[PCIE_HWIP] = "PCIE",
70
+
};
71
+
72
+
static ssize_t
73
+
amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
74
+
void *data, size_t datalen)
75
+
{
76
+
struct drm_printer p;
77
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struct amdgpu_coredump_info *coredump = data;
78
+
struct drm_print_iterator iter;
79
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struct amdgpu_vm_fault_info *fault_info;
80
+
int i, ver;
81
+
82
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iter.data = buffer;
83
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iter.offset = 0;
84
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iter.start = offset;
85
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iter.remain = count;
86
+
87
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p = drm_coredump_printer(&iter);
88
+
89
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drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
90
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drm_printf(&p, "version: " AMDGPU_COREDUMP_VERSION "\n");
91
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drm_printf(&p, "kernel: " UTS_RELEASE "\n");
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drm_printf(&p, "module: " KBUILD_MODNAME "\n");
93
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drm_printf(&p, "time: %lld.%09ld\n", coredump->reset_time.tv_sec,
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coredump->reset_time.tv_nsec);
95
+
96
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if (coredump->reset_task_info.pid)
97
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drm_printf(&p, "process_name: %s PID: %d\n",
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coredump->reset_task_info.process_name,
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coredump->reset_task_info.pid);
100
+
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/* GPU IP's information of the SOC */
102
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drm_printf(&p, "\nIP Information\n");
103
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drm_printf(&p, "SOC Family: %d\n", coredump->adev->family);
104
+
drm_printf(&p, "SOC Revision id: %d\n", coredump->adev->rev_id);
105
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drm_printf(&p, "SOC External Revision id: %d\n", coredump->adev->external_rev_id);
106
+
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for (int i = 1; i < MAX_HWIP; i++) {
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for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
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ver = coredump->adev->ip_versions[i][j];
110
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if (ver)
111
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drm_printf(&p, "HWIP: %s[%d][%d]: v%d.%d.%d.%d.%d\n",
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hw_ip_names[i], i, j,
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IP_VERSION_MAJ(ver),
114
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IP_VERSION_MIN(ver),
115
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IP_VERSION_REV(ver),
116
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IP_VERSION_VARIANT(ver),
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IP_VERSION_SUBREV(ver));
118
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}
119
+
}
120
+
121
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if (coredump->ring) {
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drm_printf(&p, "\nRing timed out details\n");
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drm_printf(&p, "IP Type: %d Ring Name: %s\n",
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coredump->ring->funcs->type,
125
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coredump->ring->name);
126
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}
127
+
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/* Add page fault information */
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fault_info = &coredump->adev->vm_manager.fault_info;
130
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drm_printf(&p, "\n[%s] Page fault observed\n",
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fault_info->vmhub ? "mmhub" : "gfxhub");
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drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
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drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
134
+
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/* Add ring buffer information */
136
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drm_printf(&p, "Ring buffer information\n");
137
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for (int i = 0; i < coredump->adev->num_rings; i++) {
138
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int j = 0;
139
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struct amdgpu_ring *ring = coredump->adev->rings[i];
140
+
141
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drm_printf(&p, "ring name: %s\n", ring->name);
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drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n",
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amdgpu_ring_get_rptr(ring),
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amdgpu_ring_get_wptr(ring),
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ring->buf_mask);
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drm_printf(&p, "Ring size in dwords: %d\n",
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ring->ring_size / 4);
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drm_printf(&p, "Ring contents\n");
149
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drm_printf(&p, "Offset \t Value\n");
150
+
151
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while (j < ring->ring_size) {
152
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drm_printf(&p, "0x%x \t 0x%x\n", j, ring->ring[j / 4]);
153
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j += 4;
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+
}
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+
}
156
+
157
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if (coredump->reset_vram_lost)
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drm_printf(&p, "VRAM is lost due to GPU reset!\n");
159
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if (coredump->adev->reset_info.num_regs) {
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drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
161
+
162
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for (i = 0; i < coredump->adev->reset_info.num_regs; i++)
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drm_printf(&p, "0x%08x: 0x%08x\n",
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coredump->adev->reset_info.reset_dump_reg_list[i],
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coredump->adev->reset_info.reset_dump_reg_value[i]);
166
+
}
167
+
168
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return count - iter.remain;
169
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}
170
+
171
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static void amdgpu_devcoredump_free(void *data)
172
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{
173
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kfree(data);
174
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}
175
+
176
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void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
177
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struct amdgpu_reset_context *reset_context)
178
+
{
179
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struct amdgpu_coredump_info *coredump;
180
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struct drm_device *dev = adev_to_drm(adev);
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struct amdgpu_job *job = reset_context->job;
182
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struct drm_sched_job *s_job;
183
+
184
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coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT);
185
+
186
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if (!coredump) {
187
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DRM_ERROR("%s: failed to allocate memory for coredump\n", __func__);
188
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return;
189
+
}
190
+
191
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coredump->reset_vram_lost = vram_lost;
192
+
193
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if (reset_context->job && reset_context->job->vm) {
194
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struct amdgpu_task_info *ti;
195
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struct amdgpu_vm *vm = reset_context->job->vm;
196
+
197
+
ti = amdgpu_vm_get_task_info_vm(vm);
198
+
if (ti) {
199
+
coredump->reset_task_info = *ti;
200
+
amdgpu_vm_put_task_info(ti);
201
+
}
202
+
}
203
+
204
+
if (job) {
205
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s_job = &job->base;
206
+
coredump->ring = to_amdgpu_ring(s_job->sched);
207
+
}
208
+
209
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coredump->adev = adev;
210
+
211
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ktime_get_ts64(&coredump->reset_time);
212
+
213
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dev_coredumpm(dev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT,
214
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amdgpu_devcoredump_read, amdgpu_devcoredump_free);
215
+
}
216
+
#endif
+47
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h
+47
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright 2024 Advanced Micro Devices, Inc.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the "Software"),
7
+
* to deal in the Software without restriction, including without limitation
8
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
+
* and/or sell copies of the Software, and to permit persons to whom the
10
+
* Software is furnished to do so, subject to the following conditions:
11
+
*
12
+
* The above copyright notice and this permission notice shall be included in
13
+
* all copies or substantial portions of the Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21
+
* OTHER DEALINGS IN THE SOFTWARE.
22
+
*
23
+
*/
24
+
25
+
#ifndef __AMDGPU_DEV_COREDUMP_H__
26
+
#define __AMDGPU_DEV_COREDUMP_H__
27
+
28
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#include "amdgpu.h"
29
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#include "amdgpu_reset.h"
30
+
31
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#ifdef CONFIG_DEV_COREDUMP
32
+
33
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#define AMDGPU_COREDUMP_VERSION "1"
34
+
35
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struct amdgpu_coredump_info {
36
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struct amdgpu_device *adev;
37
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struct amdgpu_task_info reset_task_info;
38
+
struct timespec64 reset_time;
39
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bool reset_vram_lost;
40
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struct amdgpu_ring *ring;
41
+
};
42
+
#endif
43
+
44
+
void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
45
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struct amdgpu_reset_context *reset_context);
46
+
47
+
#endif
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-191
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
-191
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
···
21
21
*
22
22
*/
23
23
24
-
#include <linux/devcoredump.h>
25
-
#include <generated/utsrelease.h>
26
-
27
24
#include "amdgpu_reset.h"
28
25
#include "aldebaran.h"
29
26
#include "sienna_cichlid.h"
30
27
#include "smu_v13_0_10.h"
31
-
32
-
const char *hw_ip_names[MAX_HWIP] = {
33
-
[GC_HWIP] = "GC",
34
-
[HDP_HWIP] = "HDP",
35
-
[SDMA0_HWIP] = "SDMA0",
36
-
[SDMA1_HWIP] = "SDMA1",
37
-
[SDMA2_HWIP] = "SDMA2",
38
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[SDMA3_HWIP] = "SDMA3",
39
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[SDMA4_HWIP] = "SDMA4",
40
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[SDMA5_HWIP] = "SDMA5",
41
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[SDMA6_HWIP] = "SDMA6",
42
-
[SDMA7_HWIP] = "SDMA7",
43
-
[LSDMA_HWIP] = "LSDMA",
44
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[MMHUB_HWIP] = "MMHUB",
45
-
[ATHUB_HWIP] = "ATHUB",
46
-
[NBIO_HWIP] = "NBIO",
47
-
[MP0_HWIP] = "MP0",
48
-
[MP1_HWIP] = "MP1",
49
-
[UVD_HWIP] = "UVD/JPEG/VCN",
50
-
[VCN1_HWIP] = "VCN1",
51
-
[VCE_HWIP] = "VCE",
52
-
[VPE_HWIP] = "VPE",
53
-
[DF_HWIP] = "DF",
54
-
[DCE_HWIP] = "DCE",
55
-
[OSSSYS_HWIP] = "OSSSYS",
56
-
[SMUIO_HWIP] = "SMUIO",
57
-
[PWR_HWIP] = "PWR",
58
-
[NBIF_HWIP] = "NBIF",
59
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[THM_HWIP] = "THM",
60
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[CLK_HWIP] = "CLK",
61
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[UMC_HWIP] = "UMC",
62
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[RSMU_HWIP] = "RSMU",
63
-
[XGMI_HWIP] = "XGMI",
64
-
[DCI_HWIP] = "DCI",
65
-
[PCIE_HWIP] = "PCIE",
66
-
};
67
28
68
29
int amdgpu_reset_init(struct amdgpu_device *adev)
69
30
{
···
158
197
atomic_set(&reset_domain->in_gpu_reset, 0);
159
198
up_write(&reset_domain->sem);
160
199
}
161
-
162
-
#ifndef CONFIG_DEV_COREDUMP
163
-
void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
164
-
struct amdgpu_reset_context *reset_context)
165
-
{
166
-
}
167
-
#else
168
-
static ssize_t
169
-
amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
170
-
void *data, size_t datalen)
171
-
{
172
-
struct drm_printer p;
173
-
struct amdgpu_coredump_info *coredump = data;
174
-
struct drm_print_iterator iter;
175
-
struct amdgpu_vm_fault_info *fault_info;
176
-
int i, ver;
177
-
178
-
iter.data = buffer;
179
-
iter.offset = 0;
180
-
iter.start = offset;
181
-
iter.remain = count;
182
-
183
-
p = drm_coredump_printer(&iter);
184
-
185
-
drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
186
-
drm_printf(&p, "version: " AMDGPU_COREDUMP_VERSION "\n");
187
-
drm_printf(&p, "kernel: " UTS_RELEASE "\n");
188
-
drm_printf(&p, "module: " KBUILD_MODNAME "\n");
189
-
drm_printf(&p, "time: %lld.%09ld\n", coredump->reset_time.tv_sec,
190
-
coredump->reset_time.tv_nsec);
191
-
192
-
if (coredump->reset_task_info.pid)
193
-
drm_printf(&p, "process_name: %s PID: %d\n",
194
-
coredump->reset_task_info.process_name,
195
-
coredump->reset_task_info.pid);
196
-
197
-
/* GPU IP's information of the SOC */
198
-
drm_printf(&p, "\nIP Information\n");
199
-
drm_printf(&p, "SOC Family: %d\n", coredump->adev->family);
200
-
drm_printf(&p, "SOC Revision id: %d\n", coredump->adev->rev_id);
201
-
drm_printf(&p, "SOC External Revision id: %d\n", coredump->adev->external_rev_id);
202
-
203
-
for (int i = 1; i < MAX_HWIP; i++) {
204
-
for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
205
-
ver = coredump->adev->ip_versions[i][j];
206
-
if (ver)
207
-
drm_printf(&p, "HWIP: %s[%d][%d]: v%d.%d.%d.%d.%d\n",
208
-
hw_ip_names[i], i, j,
209
-
IP_VERSION_MAJ(ver),
210
-
IP_VERSION_MIN(ver),
211
-
IP_VERSION_REV(ver),
212
-
IP_VERSION_VARIANT(ver),
213
-
IP_VERSION_SUBREV(ver));
214
-
}
215
-
}
216
-
217
-
if (coredump->ring) {
218
-
drm_printf(&p, "\nRing timed out details\n");
219
-
drm_printf(&p, "IP Type: %d Ring Name: %s\n",
220
-
coredump->ring->funcs->type,
221
-
coredump->ring->name);
222
-
}
223
-
224
-
/* Add page fault information */
225
-
fault_info = &coredump->adev->vm_manager.fault_info;
226
-
drm_printf(&p, "\n[%s] Page fault observed\n",
227
-
fault_info->vmhub ? "mmhub" : "gfxhub");
228
-
drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
229
-
drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
230
-
231
-
/* Add ring buffer information */
232
-
drm_printf(&p, "Ring buffer information\n");
233
-
for (int i = 0; i < coredump->adev->num_rings; i++) {
234
-
int j = 0;
235
-
struct amdgpu_ring *ring = coredump->adev->rings[i];
236
-
237
-
drm_printf(&p, "ring name: %s\n", ring->name);
238
-
drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n",
239
-
amdgpu_ring_get_rptr(ring),
240
-
amdgpu_ring_get_wptr(ring),
241
-
ring->buf_mask);
242
-
drm_printf(&p, "Ring size in dwords: %d\n",
243
-
ring->ring_size / 4);
244
-
drm_printf(&p, "Ring contents\n");
245
-
drm_printf(&p, "Offset \t Value\n");
246
-
247
-
while (j < ring->ring_size) {
248
-
drm_printf(&p, "0x%x \t 0x%x\n", j, ring->ring[j/4]);
249
-
j += 4;
250
-
}
251
-
}
252
-
253
-
if (coredump->reset_vram_lost)
254
-
drm_printf(&p, "VRAM is lost due to GPU reset!\n");
255
-
if (coredump->adev->reset_info.num_regs) {
256
-
drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
257
-
258
-
for (i = 0; i < coredump->adev->reset_info.num_regs; i++)
259
-
drm_printf(&p, "0x%08x: 0x%08x\n",
260
-
coredump->adev->reset_info.reset_dump_reg_list[i],
261
-
coredump->adev->reset_info.reset_dump_reg_value[i]);
262
-
}
263
-
264
-
return count - iter.remain;
265
-
}
266
-
267
-
static void amdgpu_devcoredump_free(void *data)
268
-
{
269
-
kfree(data);
270
-
}
271
-
272
-
void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
273
-
struct amdgpu_reset_context *reset_context)
274
-
{
275
-
struct amdgpu_coredump_info *coredump;
276
-
struct drm_device *dev = adev_to_drm(adev);
277
-
struct amdgpu_job *job = reset_context->job;
278
-
struct drm_sched_job *s_job;
279
-
280
-
coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT);
281
-
282
-
if (!coredump) {
283
-
DRM_ERROR("%s: failed to allocate memory for coredump\n", __func__);
284
-
return;
285
-
}
286
-
287
-
coredump->reset_vram_lost = vram_lost;
288
-
289
-
if (reset_context->job && reset_context->job->vm) {
290
-
struct amdgpu_task_info *ti;
291
-
struct amdgpu_vm *vm = reset_context->job->vm;
292
-
293
-
ti = amdgpu_vm_get_task_info_vm(vm);
294
-
if (ti) {
295
-
coredump->reset_task_info = *ti;
296
-
amdgpu_vm_put_task_info(ti);
297
-
}
298
-
}
299
-
300
-
if (job) {
301
-
s_job = &job->base;
302
-
coredump->ring = to_amdgpu_ring(s_job->sched);
303
-
}
304
-
305
-
coredump->adev = adev;
306
-
307
-
ktime_get_ts64(&coredump->reset_time);
308
-
309
-
dev_coredumpm(dev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT,
310
-
amdgpu_devcoredump_read, amdgpu_devcoredump_free);
311
-
}
312
-
#endif
-16
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
-16
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
···
88
88
atomic_t reset_res;
89
89
};
90
90
91
-
#ifdef CONFIG_DEV_COREDUMP
92
-
93
-
#define AMDGPU_COREDUMP_VERSION "1"
94
-
95
-
struct amdgpu_coredump_info {
96
-
struct amdgpu_device *adev;
97
-
struct amdgpu_task_info reset_task_info;
98
-
struct timespec64 reset_time;
99
-
bool reset_vram_lost;
100
-
struct amdgpu_ring *ring;
101
-
};
102
-
#endif
103
-
104
91
int amdgpu_reset_init(struct amdgpu_device *adev);
105
92
int amdgpu_reset_fini(struct amdgpu_device *adev);
106
93
···
127
140
void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
128
141
129
142
void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
130
-
131
-
void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,
132
-
struct amdgpu_reset_context *reset_context);
133
143
134
144
#define for_each_handler(i, handler, reset_ctl) \
135
145
for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \