tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN

No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 8fe44c08 519424d7

+45 -319
-7
drivers/gpu/drm/amd/display/Kconfig
··· 31 31 by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 32 32 Hainan is not supported by AMD DC and it has no physical DCE6. 33 33 34 - config DRM_AMD_DC_DCN3_1 35 - bool "DCN 3.1 family" 36 - depends on DRM_AMD_DC_DCN 37 - help 38 - Choose this option if you want to have 39 - DCN3.1 family support for display engine 40 - 41 34 config DEBUG_KERNEL_DC 42 35 bool "Enable kgdb break in DC" 43 36 depends on DRM_AMD_DC
+1 -21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 110 110 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 111 111 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 112 112 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 113 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 114 113 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 115 114 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 116 - #endif 117 115 118 116 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 119 117 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); ··· 1143 1145 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1144 1146 init_data.flags.disable_dmcu = true; 1145 1147 break; 1146 - #if defined(CONFIG_DRM_AMD_DC_DCN) 1147 1148 case CHIP_VANGOGH: 1148 - init_data.flags.gpu_vm_support = true; 1149 - break; 1150 - #endif 1151 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1152 1149 case CHIP_YELLOW_CARP: 1153 1150 init_data.flags.gpu_vm_support = true; 1154 1151 break; 1155 - #endif 1156 1152 default: 1157 1153 break; 1158 1154 } ··· 1403 1411 case CHIP_DIMGREY_CAVEFISH: 1404 1412 case CHIP_BEIGE_GOBY: 1405 1413 case CHIP_VANGOGH: 1406 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1407 1414 case CHIP_YELLOW_CARP: 1408 - #endif 1409 1415 return 0; 1410 1416 case CHIP_NAVI12: 1411 1417 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; ··· 1522 1532 dmub_asic = DMUB_ASIC_DCN303; 1523 1533 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 1524 1534 break; 1525 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1526 1535 case CHIP_YELLOW_CARP: 1527 1536 dmub_asic = DMUB_ASIC_DCN31; 1528 1537 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 1529 1538 break; 1530 - #endif 1531 1539 1532 1540 default: 1533 1541 /* ASIC doesn't support DMUB. */ ··· 2220 2232 = 0xffffffff; 2221 2233 } 2222 2234 } 2223 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2235 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2224 2236 /* 2225 2237 * Resource allocation happens for link encoders for newer ASIC in 2226 2238 * dc_validate_global_state, so we need to revalidate it. ··· 3774 3786 switch (adev->asic_type) { 3775 3787 case CHIP_SIENNA_CICHLID: 3776 3788 case CHIP_NAVY_FLOUNDER: 3777 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3778 3789 case CHIP_YELLOW_CARP: 3779 - #endif 3780 3790 case CHIP_RENOIR: 3781 3791 if (register_outbox_irq_handlers(dm->adev)) { 3782 3792 DRM_ERROR("DM: Failed to initialize IRQ\n"); ··· 3879 3893 case CHIP_DIMGREY_CAVEFISH: 3880 3894 case CHIP_BEIGE_GOBY: 3881 3895 case CHIP_VANGOGH: 3882 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3883 3896 case CHIP_YELLOW_CARP: 3884 - #endif 3885 3897 if (dcn10_register_irq_handlers(dm->adev)) { 3886 3898 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3887 3899 goto fail; ··· 4051 4067 adev->mode_info.num_hpd = 6; 4052 4068 adev->mode_info.num_dig = 6; 4053 4069 break; 4054 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 4055 4070 case CHIP_YELLOW_CARP: 4056 4071 adev->mode_info.num_crtc = 4; 4057 4072 adev->mode_info.num_hpd = 4; 4058 4073 adev->mode_info.num_dig = 4; 4059 4074 break; 4060 - #endif 4061 4075 case CHIP_NAVI14: 4062 4076 case CHIP_DIMGREY_CAVEFISH: 4063 4077 adev->mode_info.num_crtc = 5; ··· 4293 4311 adev->asic_type == CHIP_NAVY_FLOUNDER || 4294 4312 adev->asic_type == CHIP_DIMGREY_CAVEFISH || 4295 4313 adev->asic_type == CHIP_BEIGE_GOBY || 4296 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 4297 4314 adev->asic_type == CHIP_YELLOW_CARP || 4298 - #endif 4299 4315 adev->asic_type == CHIP_VANGOGH) 4300 4316 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 4301 4317 }
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
··· 467 467 display->dig_fe = config->dig_fe; 468 468 link->dig_be = config->dig_be; 469 469 link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; 470 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 471 470 display->stream_enc_idx = config->stream_enc_idx; 472 471 link->link_enc_idx = config->link_enc_idx; 473 472 link->phy_idx = config->phy_idx; 474 473 link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link, 475 474 aconnector->dc_sink->sink_signal) ? 1 : 0; 476 - #endif 477 475 link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; 478 476 link->dp.assr_enabled = config->assr_enabled; 479 477 link->dp.mst_enabled = config->mst_enabled; ··· 655 657 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); 656 658 657 659 hdcp_work[i].hdcp.config.psp.handle = &adev->psp; 658 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 659 660 if (dc->ctx->dce_version == DCN_VERSION_3_1) { 660 661 hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1; 661 662 hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false; 662 663 } 663 - #endif 664 664 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); 665 665 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; 666 666 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
-2
drivers/gpu/drm/amd/display/dc/Makefile
··· 34 34 DC_LIBS += dcn301 35 35 DC_LIBS += dcn302 36 36 DC_LIBS += dcn303 37 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 38 37 DC_LIBS += dcn31 39 - endif 40 38 endif 41 39 42 40 DC_LIBS += dce120
+1 -6
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
··· 576 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 577 result_device_id.enum_id = 1; 578 578 break; 579 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 580 579 581 580 case ATOM_DISPLAY_LCD2_SUPPORT: 582 581 result_device_id.device_type = DEVICE_TYPE_LCD; 583 582 result_device_id.enum_id = 2; 584 583 break; 585 - #endif 586 584 587 585 case ATOM_DISPLAY_DFP1_SUPPORT: 588 586 result_device_id.device_type = DEVICE_TYPE_DFP; ··· 2160 2162 return BP_RESULT_OK; 2161 2163 } 2162 2164 2163 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2164 2165 static enum bp_result get_integrated_info_v2_2( 2165 2166 struct bios_parser *bp, 2166 2167 struct integrated_info *info) ··· 2259 2262 2260 2263 return BP_RESULT_OK; 2261 2264 } 2262 - #endif 2265 + 2263 2266 /* 2264 2267 * construct_integrated_info 2265 2268 * ··· 2307 2310 case 1: 2308 2311 result = get_integrated_info_v2_1(bp, info); 2309 2312 break; 2310 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2311 2313 case 2: 2312 2314 result = get_integrated_info_v2_2(bp, info); 2313 2315 break; 2314 - #endif 2315 2316 default: 2316 2317 return result; 2317 2318 }
+1 -5
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
··· 72 72 case DCN_VERSION_2_1: 73 73 case DCN_VERSION_3_0: 74 74 case DCN_VERSION_3_01: 75 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 76 - case DCN_VERSION_3_1: 77 - *h = dal_cmd_tbl_helper_dce112_get_table2(); 78 - return true; 79 - #endif 80 75 case DCN_VERSION_3_02: 81 76 case DCN_VERSION_3_03: 77 + case DCN_VERSION_3_1: 82 78 *h = dal_cmd_tbl_helper_dce112_get_table2(); 83 79 return true; 84 80 #endif
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
··· 135 135 AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301)) 136 136 137 137 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301) 138 - endif 139 138 140 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 141 139 ############################################################################### 142 140 # DCN31 143 141 ###############################################################################
-7
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
··· 41 41 #include "dcn21/rn_clk_mgr.h" 42 42 #include "dcn30/dcn30_clk_mgr.h" 43 43 #include "dcn301/vg_clk_mgr.h" 44 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 45 44 #include "dcn31/dcn31_clk_mgr.h" 46 - #endif 47 45 48 46 49 47 int clk_mgr_helper_get_active_display_cnt( ··· 271 273 return &clk_mgr->base.base; 272 274 } 273 275 break; 274 - #endif 275 - 276 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 277 276 case FAMILY_YELLOW_CARP: { 278 277 struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); 279 278 ··· 320 325 vg_clk_mgr_destroy(clk_mgr); 321 326 break; 322 327 323 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 324 328 case FAMILY_YELLOW_CARP: 325 329 if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev)) 326 330 dcn31_clk_mgr_destroy(clk_mgr); 327 331 break; 328 - #endif 329 332 330 333 default: 331 334 break;
-2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
··· 386 386 // Both fclk and ref_dppclk run on the same scemi clock. 387 387 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; 388 388 389 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 390 389 /* TODO: set dtbclk in correct place */ 391 390 clk_mgr->clks.dtbclk_en = false; 392 - #endif 393 391 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 394 392 } 395 393
+3 -5
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 1524 1524 return stream_mask; 1525 1525 } 1526 1526 1527 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1527 + #if defined(CONFIG_DRM_AMD_DC_DCN) 1528 1528 void dc_z10_restore(struct dc *dc) 1529 1529 { 1530 1530 if (dc->hwss.z10_restore) ··· 1544 1544 struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; 1545 1545 1546 1546 #if defined(CONFIG_DRM_AMD_DC_DCN) 1547 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1548 1547 dc_z10_restore(dc); 1549 - #endif 1550 1548 dc_allow_idle_optimizations(dc, false); 1551 1549 #endif 1552 1550 ··· 2624 2626 int i, j; 2625 2627 struct pipe_ctx *top_pipe_to_program = NULL; 2626 2628 2627 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2629 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2628 2630 dc_z10_restore(dc); 2629 2631 #endif 2630 2632 ··· 3083 3085 case DC_ACPI_CM_POWER_STATE_D0: 3084 3086 dc_resource_state_construct(dc, dc->current_state); 3085 3087 3086 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3088 + #if defined(CONFIG_DRM_AMD_DC_DCN) 3087 3089 dc_z10_restore(dc); 3088 3090 #endif 3089 3091 if (dc->ctx->dmub_srv)
+3 -3
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 2661 2661 return false; 2662 2662 2663 2663 link->psr_settings.psr_allow_active = allow_active; 2664 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2664 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2665 2665 if (!allow_active) 2666 2666 dc_z10_restore(dc); 2667 2667 #endif ··· 2842 2842 psr_context->psr_level.u32all = 0; 2843 2843 2844 2844 /*skip power down the single pipe since it blocks the cstate*/ 2845 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2845 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2846 2846 if (link->ctx->asic_id.chip_family >= FAMILY_RV) { 2847 2847 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; 2848 2848 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10) ··· 3191 3191 /*stream_enc_inst*/ 3192 3192 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 3193 3193 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 3194 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3194 + #if defined(CONFIG_DRM_AMD_DC_DCN) 3195 3195 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 3196 3196 config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; 3197 3197 config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+2 -8
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
··· 58 58 #include "dcn301/dcn301_resource.h" 59 59 #include "dcn302/dcn302_resource.h" 60 60 #include "dcn303/dcn303_resource.h" 61 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 62 - #include "../dcn31/dcn31_resource.h" 63 - #endif 61 + #include "dcn31/dcn31_resource.h" 64 62 #endif 65 63 66 64 #define DC_LOGGER_INIT(logger) ··· 139 141 case FAMILY_VGH: 140 142 dc_version = DCN_VERSION_3_01; 141 143 break; 142 - #endif 143 144 144 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 145 145 case FAMILY_YELLOW_CARP: 146 146 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 147 147 dc_version = DCN_VERSION_3_1; ··· 229 233 case DCN_VERSION_3_03: 230 234 res_pool = dcn303_create_resource_pool(init_data, dc); 231 235 break; 232 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 233 236 case DCN_VERSION_3_1: 234 237 res_pool = dcn31_create_resource_pool(init_data, dc); 235 238 break; 236 - #endif 237 239 #endif 238 240 default: 239 241 break; ··· 2136 2142 2137 2143 if (!new_ctx) 2138 2144 return DC_ERROR_UNEXPECTED; 2139 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2145 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2140 2146 2141 2147 /* 2142 2148 * Update link encoder to stream assignment.
-4
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
··· 294 294 stream->cursor_attributes = *attributes; 295 295 296 296 #if defined(CONFIG_DRM_AMD_DC_DCN) 297 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 298 297 dc_z10_restore(dc); 299 - #endif 300 298 /* disable idle optimizations while updating cursor */ 301 299 if (dc->idle_optimizations_allowed) { 302 300 dc_allow_idle_optimizations(dc, false); ··· 356 358 dc = stream->ctx->dc; 357 359 res_ctx = &dc->current_state->res_ctx; 358 360 #if defined(CONFIG_DRM_AMD_DC_DCN) 359 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 360 361 dc_z10_restore(dc); 361 - #endif 362 362 363 363 /* disable idle optimizations if enabling cursor */ 364 364 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
+6 -8
drivers/gpu/drm/amd/display/dc/dc.h
··· 352 352 DCN_PWR_STATE_LOW_POWER = 3, 353 353 }; 354 354 355 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 355 + #if defined(CONFIG_DRM_AMD_DC_DCN) 356 356 enum dcn_z9_support_state { 357 357 DCN_Z9_SUPPORT_UNKNOWN, 358 358 DCN_Z9_SUPPORT_ALLOW, ··· 376 376 int phyclk_khz; 377 377 int dramclk_khz; 378 378 bool p_state_change_support; 379 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 379 + #if defined(CONFIG_DRM_AMD_DC_DCN) 380 380 enum dcn_z9_support_state z9_support; 381 381 bool dtbclk_en; 382 382 #endif ··· 501 501 bool disable_pplib_clock_request; 502 502 bool disable_clock_gate; 503 503 bool disable_mem_low_power; 504 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 504 + #if defined(CONFIG_DRM_AMD_DC_DCN) 505 505 bool pstate_enabled; 506 506 #endif 507 507 bool disable_dmcu; ··· 522 522 unsigned int force_odm_combine; //bit vector based on otg inst 523 523 #if defined(CONFIG_DRM_AMD_DC_DCN) 524 524 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 525 - #endif 526 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 527 525 bool disable_z9_mpc; 528 526 #endif 529 527 unsigned int force_fclk_khz; ··· 565 567 bool force_enable_edp_fec; 566 568 /* FEC/PSR1 sequence enable delay in 100us */ 567 569 uint8_t fec_enable_delay_in100us; 568 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 570 + #if defined(CONFIG_DRM_AMD_DC_DCN) 569 571 bool disable_z10; 570 572 bool enable_sw_cntl_psr; 571 573 #endif ··· 593 595 uint64_t page_table_start_addr; 594 596 uint64_t page_table_end_addr; 595 597 uint64_t page_table_base_addr; 596 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 598 + #if defined(CONFIG_DRM_AMD_DC_DCN) 597 599 bool base_addr_is_mc_addr; 598 600 #endif 599 601 } gart_config; ··· 1333 1335 #endif 1334 1336 1335 1337 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1336 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1338 + #if defined(CONFIG_DRM_AMD_DC_DCN) 1337 1339 void dc_z10_restore(struct dc *dc); 1338 1340 #endif 1339 1341
+1 -2
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
··· 185 185 dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, 186 186 stream_mask, timeout) == DMUB_STATUS_OK; 187 187 } 188 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 188 + 189 189 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) 190 190 { 191 191 struct dmub_srv *dmub; ··· 207 207 208 208 return boot_status.bits.restore_required; 209 209 } 210 - #endif 211 210 212 211 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) 213 212 {
+1 -2
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
··· 62 62 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, 63 63 unsigned int stream_mask); 64 64 65 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 66 65 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv); 67 - #endif 66 + 68 67 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry); 69 68 70 69 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
-6
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
··· 1106 1106 type PANEL_DIGON_OVRD;\ 1107 1107 type PANEL_PWRSEQ_TARGET_STATE_R; 1108 1108 1109 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1110 1109 #define HWSEQ_DCN31_REG_FIELD_LIST(type) \ 1111 1110 type DOMAIN_POWER_FORCEON;\ 1112 1111 type DOMAIN_POWER_GATE;\ 1113 1112 type DOMAIN_PGFSM_PWR_STATUS;\ 1114 1113 type HPO_HDMISTREAMCLK_G_GATE_DIS; 1115 1114 1116 - #endif 1117 1115 struct dce_hwseq_shift { 1118 1116 HWSEQ_REG_FIELD_LIST(uint8_t) 1119 1117 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 1120 1118 HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) 1121 1119 HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) 1122 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1123 1120 HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) 1124 - #endif 1125 1121 }; 1126 1122 1127 1123 struct dce_hwseq_mask { ··· 1125 1129 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 1126 1130 HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) 1127 1131 HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) 1128 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1129 1132 HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) 1130 - #endif 1131 1133 }; 1132 1134 1133 1135
+2 -2
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
··· 48 48 #include "link_encoder.h" 49 49 #include "link_hwss.h" 50 50 #include "dc_link_dp.h" 51 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 51 + #if defined(CONFIG_DRM_AMD_DC_DCN) 52 52 #include "dccg.h" 53 53 #endif 54 54 #include "clock_source.h" ··· 2090 2090 2091 2091 build_audio_output(context, pipe_ctx, &audio_output); 2092 2092 2093 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2093 + #if defined(CONFIG_DRM_AMD_DC_DCN) 2094 2094 /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ 2095 2095 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2096 2096 /* disable audio DTBCLK DTO */
+1 -8
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
··· 139 139 uint32_t DCHVM_CLK_CTRL; 140 140 uint32_t DCHVM_RIOMMU_CTRL0; 141 141 uint32_t DCHVM_RIOMMU_STAT0; 142 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 143 142 uint32_t DCHUBBUB_DET0_CTRL; 144 143 uint32_t DCHUBBUB_DET1_CTRL; 145 144 uint32_t DCHUBBUB_DET2_CTRL; ··· 154 155 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; 155 156 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; 156 157 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; 157 - #endif 158 158 }; 159 159 160 160 /* set field name */ ··· 290 292 type HOSTVM_POWERSTATUS; \ 291 293 type RIOMMU_ACTIVE; \ 292 294 type HOSTVM_PREFETCH_DONE 293 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 295 + 294 296 #define HUBBUB_RET_REG_FIELD_LIST(type) \ 295 297 type DET_DEPTH;\ 296 298 type DET0_SIZE;\ ··· 313 315 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\ 314 316 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\ 315 317 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 316 - #endif 317 318 318 319 319 320 struct dcn_hubbub_shift { 320 321 DCN_HUBBUB_REG_FIELD_LIST(uint8_t); 321 322 HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); 322 323 HUBBUB_HVM_REG_FIELD_LIST(uint8_t); 323 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 324 324 HUBBUB_RET_REG_FIELD_LIST(uint8_t); 325 - #endif 326 325 }; 327 326 328 327 struct dcn_hubbub_mask { 329 328 DCN_HUBBUB_REG_FIELD_LIST(uint32_t); 330 329 HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); 331 330 HUBBUB_HVM_REG_FIELD_LIST(uint32_t); 332 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 333 331 HUBBUB_RET_REG_FIELD_LIST(uint32_t); 334 - #endif 335 332 }; 336 333 337 334 struct dc;
-8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
··· 140 140 type PHYCSYMCLK_FORCE_EN;\ 141 141 type PHYCSYMCLK_FORCE_SRC_SEL; 142 142 143 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 144 143 #define DCCG31_REG_FIELD_LIST(type) \ 145 144 type PHYDSYMCLK_FORCE_EN;\ 146 145 type PHYDSYMCLK_FORCE_SRC_SEL;\ ··· 170 171 type DCCG_AUDIO_DTO_SEL;\ 171 172 type DCCG_AUDIO_DTO0_SOURCE_SEL;\ 172 173 type DENTIST_DISPCLK_CHG_MODE; 173 - #endif 174 174 175 175 struct dccg_shift { 176 176 DCCG_REG_FIELD_LIST(uint8_t) 177 177 DCCG3_REG_FIELD_LIST(uint8_t) 178 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 179 178 DCCG31_REG_FIELD_LIST(uint8_t) 180 - #endif 181 179 }; 182 180 183 181 struct dccg_mask { 184 182 DCCG_REG_FIELD_LIST(uint32_t) 185 183 DCCG3_REG_FIELD_LIST(uint32_t) 186 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 187 184 DCCG31_REG_FIELD_LIST(uint32_t) 188 - #endif 189 185 }; 190 186 191 187 struct dccg_registers { ··· 193 199 uint32_t PHYASYMCLK_CLOCK_CNTL; 194 200 uint32_t PHYBSYMCLK_CLOCK_CNTL; 195 201 uint32_t PHYCSYMCLK_CLOCK_CNTL; 196 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 197 202 uint32_t PHYDSYMCLK_CLOCK_CNTL; 198 203 uint32_t PHYESYMCLK_CLOCK_CNTL; 199 204 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; ··· 205 212 uint32_t SYMCLK32_SE_CNTL; 206 213 uint32_t SYMCLK32_LE_CNTL; 207 214 uint32_t DENTIST_DISPCLK_CNTL; 208 - #endif 209 215 }; 210 216 211 217 struct dcn_dccg {
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
··· 83 83 int num_vmid; 84 84 struct dcn20_vmid vmid[16]; 85 85 unsigned int detile_buf_size; 86 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 87 86 unsigned int crb_size_segs; 88 87 unsigned int compbuf_size_segments; 89 88 unsigned int pixel_chunk_size; ··· 90 91 unsigned int det1_size; 91 92 unsigned int det2_size; 92 93 unsigned int det3_size; 93 - #endif 94 94 }; 95 95 96 96 void hubbub2_construct(struct dcn20_hubbub *hubbub,
-10
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
··· 216 216 type ROW_TTU_MODE; \ 217 217 type NUM_PKRS 218 218 219 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 220 219 #define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 221 220 DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\ 222 221 type HUBP_UNBOUNDED_REQ_MODE;\ 223 222 type CURSOR_REQ_MODE;\ 224 223 type HUBP_SOFT_RESET 225 - #endif 226 224 227 225 struct dcn_hubp2_registers { 228 226 DCN30_HUBP_REG_COMMON_VARIABLE_LIST; 229 227 }; 230 228 231 229 struct dcn_hubp2_shift { 232 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 233 230 DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 234 - #else 235 - DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 236 - #endif 237 231 }; 238 232 239 233 struct dcn_hubp2_mask { 240 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 241 234 DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 242 - #else 243 - DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 244 - #endif 245 235 }; 246 236 247 237 struct dcn20_hubp {
+3 -16
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
··· 1270 1270 new_pipe->update_flags.bits.gamut_remap = 1; 1271 1271 new_pipe->update_flags.bits.scaler = 1; 1272 1272 new_pipe->update_flags.bits.viewport = 1; 1273 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1274 1273 new_pipe->update_flags.bits.det_size = 1; 1275 - #endif 1276 1274 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1277 1275 new_pipe->update_flags.bits.odm = 1; 1278 1276 new_pipe->update_flags.bits.global_sync = 1; ··· 1305 1307 new_pipe->update_flags.bits.global_sync = 1; 1306 1308 } 1307 1309 1308 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1309 1310 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1310 1311 new_pipe->update_flags.bits.det_size = 1; 1311 - #endif 1312 + 1312 1313 /* 1313 1314 * Detect opp / tg change, only set on change, not on enable 1314 1315 * Assume mpcc inst = pipe index, if not this code needs to be updated ··· 1423 1426 &pipe_ctx->ttu_regs, 1424 1427 &pipe_ctx->rq_regs, 1425 1428 &pipe_ctx->pipe_dlg_param); 1426 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1429 + 1427 1430 if (hubp->funcs->set_unbounded_requesting) 1428 1431 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1429 - #endif 1430 1432 } 1431 1433 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1432 1434 hubp->funcs->hubp_setup_interdependent( ··· 1605 1609 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1606 1610 } 1607 1611 1608 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1609 1612 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1610 1613 dc->res_pool->hubbub->funcs->program_det_size( 1611 1614 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1612 - #endif 1613 1615 1614 1616 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1615 1617 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); ··· 1699 1705 for (i = 0; i < dc->res_pool->pipe_count; i++) 1700 1706 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1701 1707 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1702 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1703 1708 struct hubbub *hubbub = dc->res_pool->hubbub; 1704 1709 1705 1710 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1706 1711 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1707 - #endif 1708 1712 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1709 1713 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1710 1714 } ··· 1820 1828 &context->bw_ctx.bw.dcn.watermarks, 1821 1829 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1822 1830 false); 1823 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1824 1831 /* decrease compbuf size */ 1825 1832 if (hubbub->funcs->program_compbuf_size) 1826 1833 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false); 1827 - #endif 1828 1834 } 1829 1835 1830 1836 void dcn20_optimize_bandwidth( ··· 1841 1851 dc->clk_mgr, 1842 1852 context, 1843 1853 true); 1844 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1845 1854 /* increase compbuf size */ 1846 1855 if (hubbub->funcs->program_compbuf_size) 1847 1856 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 1848 - #endif 1849 1857 } 1850 1858 1851 1859 bool dcn20_update_bandwidth( ··· 2549 2561 2550 2562 tg->funcs->tg_init(tg); 2551 2563 } 2552 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2564 + 2553 2565 if (dc->res_pool->hubbub->funcs->init_crb) 2554 2566 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2555 - #endif 2556 2567 } 2557 2568 #ifndef TRIM_FSFT 2558 2569 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
+4 -12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 3069 3069 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 3070 3070 } 3071 3071 3072 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3073 3072 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) 3074 3073 { 3075 3074 int i; ··· 3078 3079 } 3079 3080 return false; 3080 3081 } 3081 - #endif 3082 3082 3083 3083 void dcn20_calculate_dlg_params( 3084 3084 struct dc *dc, struct dc_state *context, ··· 3086 3088 int vlevel) 3087 3089 { 3088 3090 int i, pipe_idx; 3089 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3090 3091 int plane_count; 3091 - #endif 3092 3092 3093 3093 /* Writeback MCIF_WB arbitration parameters */ 3094 3094 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); ··· 3101 3105 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 3102 3106 != dm_dram_clock_change_unsupported; 3103 3107 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 3104 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3108 + 3105 3109 context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ? 3106 3110 DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW; 3107 3111 ··· 3115 3119 context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW; 3116 3120 3117 3121 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); 3118 - #endif 3119 3122 3120 3123 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) 3121 3124 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; ··· 3126 3131 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3127 3132 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3128 3133 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 3129 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3130 - context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 3131 - context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 3132 - #endif 3134 + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 3135 + context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 3136 + 3133 3137 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 3134 3138 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 3135 3139 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = ··· 3142 3148 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; 3143 3149 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; 3144 3150 3145 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 3146 3151 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes 3147 3152 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; 3148 - #endif 3149 3153 3150 3154 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 3151 3155 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
-2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
··· 655 655 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 656 656 dc->res_pool->hubbub->funcs->force_pstate_change_control( 657 657 dc->res_pool->hubbub, false, false); 658 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 659 658 if (dc->res_pool->hubbub->funcs->init_crb) 660 659 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 661 - #endif 662 660 663 661 } 664 662
-2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
··· 299 299 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 300 300 dc->res_pool->hubbub->funcs->force_pstate_change_control( 301 301 dc->res_pool->hubbub, false, false); 302 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 303 302 if (dc->res_pool->hubbub->funcs->init_crb) 304 303 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 305 - #endif 306 304 } 307 305 308 306 void dcn31_dsc_pg_control(
-2
drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
··· 32 32 uint8_t otg_inst; 33 33 uint8_t dig_be; 34 34 uint8_t dig_fe; 35 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 36 35 uint8_t link_enc_idx; 37 36 uint8_t stream_enc_idx; 38 37 uint8_t phy_idx; 39 - #endif 40 38 uint8_t assr_enabled; 41 39 uint8_t mst_enabled; 42 40 void *dm_stream_ctx;
-6
drivers/gpu/drm/amd/display/dc/dml/Makefile
··· 62 62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags) 63 63 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048 64 64 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) 65 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 66 65 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048 67 66 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) 68 - endif 69 67 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags) 70 68 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags) 71 69 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags) ··· 74 76 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags) 75 77 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags) 76 78 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags) 77 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 78 79 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags) 79 80 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags) 80 - endif 81 81 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags) 82 82 endif 83 83 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags) ··· 90 94 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o 91 95 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o 92 96 DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o 93 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 94 97 DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o 95 - endif 96 98 endif 97 99 98 100 AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
-2
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
··· 23 23 * 24 24 */ 25 25 26 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 27 26 #include "dc.h" 28 27 #include "dc_link.h" 29 28 #include "../display_mode_lib.h" ··· 7508 7509 return (ret_val); 7509 7510 } 7510 7511 7511 - #endif /* CONFIG_DRM_AMD_DC_DCN3_1 */
-3
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
··· 23 23 * 24 24 */ 25 25 26 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 27 - 28 26 #include "../display_mode_lib.h" 29 27 #include "../display_mode_vba.h" 30 28 #include "../dml_inline_defs.h" ··· 1722 1724 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1723 1725 } 1724 1726 1725 - #endif
+2 -7
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
··· 33 33 #include "dcn21/display_rq_dlg_calc_21.h" 34 34 #include "dcn30/display_mode_vba_30.h" 35 35 #include "dcn30/display_rq_dlg_calc_30.h" 36 - #include "dml_logger.h" 37 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 38 36 #include "dcn31/display_mode_vba_31.h" 39 37 #include "dcn31/display_rq_dlg_calc_31.h" 40 - #endif 38 + #include "dml_logger.h" 41 39 42 40 const struct dml_funcs dml20_funcs = { 43 41 .validate = dml20_ModeSupportAndSystemConfigurationFull, ··· 64 66 .rq_dlg_get_dlg_reg = dml30_rq_dlg_get_dlg_reg, 65 67 .rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg 66 68 }; 67 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 69 + 68 70 const struct dml_funcs dml31_funcs = { 69 71 .validate = dml31_ModeSupportAndSystemConfigurationFull, 70 72 .recalculate = dml31_recalculate, 71 73 .rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg, 72 74 .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg 73 75 }; 74 - #endif 75 76 76 77 void dml_init_instance(struct display_mode_lib *lib, 77 78 const struct _vcs_dpi_soc_bounding_box_st *soc_bb, ··· 93 96 case DML_PROJECT_DCN30: 94 97 lib->funcs = dml30_funcs; 95 98 break; 96 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 97 99 case DML_PROJECT_DCN31: 98 100 case DML_PROJECT_DCN31_FPGA: 99 101 lib->funcs = dml31_funcs; 100 102 break; 101 103 102 - #endif 103 104 default: 104 105 break; 105 106 }
-2
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
··· 38 38 DML_PROJECT_NAVI10v2, 39 39 DML_PROJECT_DCN21, 40 40 DML_PROJECT_DCN30, 41 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 42 41 DML_PROJECT_DCN31, 43 42 DML_PROJECT_DCN31_FPGA, 44 - #endif 45 43 }; 46 44 47 45 struct display_mode_lib;
-4
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
··· 74 74 unsigned int num_states; 75 75 double sr_exit_time_us; 76 76 double sr_enter_plus_exit_time_us; 77 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 78 77 double sr_exit_z8_time_us; 79 78 double sr_enter_plus_exit_z8_time_us; 80 - #endif 81 79 double urgent_latency_us; 82 80 double urgent_latency_pixel_data_only_us; 83 81 double urgent_latency_pixel_mixed_with_vm_data_us; ··· 211 213 unsigned int is_line_buffer_bpp_fixed; 212 214 unsigned int line_buffer_fixed_bpp; 213 215 unsigned int dcc_supported; 214 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 215 216 unsigned int config_return_buffer_size_in_kbytes; 216 217 unsigned int compressed_buffer_segment_size_in_kbytes; 217 218 unsigned int meta_fifo_size_in_kentries; 218 219 unsigned int zero_size_buffer_entries; 219 220 unsigned int compbuf_reserved_space_64b; 220 221 unsigned int compbuf_reserved_space_zs; 221 - #endif 222 222 223 223 unsigned int IsLineBufferBppFixed; 224 224 unsigned int LineBufferFixedBpp;
-12
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
··· 89 89 dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark); 90 90 dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark); 91 91 dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark); 92 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 93 92 dml_get_attr_func(wm_z8_stutter_exit, mode_lib->vba.Z8StutterExitWatermark); 94 93 dml_get_attr_func(wm_z8_stutter_enter_exit, mode_lib->vba.Z8StutterEnterPlusExitWatermark); 95 94 dml_get_attr_func(stutter_efficiency_z8, mode_lib->vba.Z8StutterEfficiency); 96 95 dml_get_attr_func(stutter_num_bursts_z8, mode_lib->vba.Z8NumberOfStutterBurstsPerFrame); 97 - #endif 98 96 dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark); 99 97 dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark); 100 98 dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency); ··· 161 163 dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix); 162 164 dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix); 163 165 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix); 164 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 165 166 dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC); 166 167 dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START); 167 - #endif 168 168 169 169 double get_total_immediate_flip_bytes( 170 170 struct display_mode_lib *mode_lib, ··· 231 235 mode_lib->vba.WritebackLatency = soc->writeback_latency_us; 232 236 mode_lib->vba.SRExitTime = soc->sr_exit_time_us; 233 237 mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us; 234 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 235 238 mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = soc->pct_ideal_sdp_bw_after_urgent; 236 239 mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 237 240 mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only; ··· 239 244 soc->max_avg_sdp_bw_use_normal_percent; 240 245 mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us; 241 246 mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us; 242 - #endif 243 247 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; 244 248 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; 245 249 mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support || ··· 313 319 mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk; 314 320 mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes; 315 321 mode_lib->vba.DETBufferSizeInKByte[0] = ip->det_buffer_size_kbytes; 316 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 317 322 mode_lib->vba.ConfigReturnBufferSizeInKByte = ip->config_return_buffer_size_in_kbytes; 318 323 mode_lib->vba.CompressedBufferSegmentSizeInkByte = ip->compressed_buffer_segment_size_in_kbytes; 319 324 mode_lib->vba.MetaFIFOSizeInKEntries = ip->meta_fifo_size_in_kentries; ··· 321 328 mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs; 322 329 mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component; 323 330 mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support; 324 - #endif 325 331 326 332 mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes; 327 333 mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes; ··· 449 457 mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c; 450 458 mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal; 451 459 mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal; 452 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 453 460 mode_lib->vba.VFrontPorch[mode_lib->vba.NumberOfActivePlanes] = dst->vfront_porch; 454 461 mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_luma; 455 462 mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_chroma; 456 - #endif 457 463 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = 458 464 src->dcc_use_global ? 459 465 ip->dcc_supported : src->dcc && ip->dcc_supported; ··· 698 708 } 699 709 } 700 710 701 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 702 711 mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting; 703 712 for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) { 704 713 if (pipes[k].pipe.src.unbounded_req_mode == 0) 705 714 mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting_disable; 706 715 } 707 - #endif 708 716 // TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified 709 717 // Do we want the dscclk to automatically be halved? Guess not since the value is specified 710 718 mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
-6
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
··· 39 39 dml_get_attr_decl(wm_writeback_urgent); 40 40 dml_get_attr_decl(wm_stutter_exit); 41 41 dml_get_attr_decl(wm_stutter_enter_exit); 42 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 43 42 dml_get_attr_decl(wm_z8_stutter_exit); 44 43 dml_get_attr_decl(wm_z8_stutter_enter_exit); 45 44 dml_get_attr_decl(stutter_efficiency_z8); 46 45 dml_get_attr_decl(stutter_num_bursts_z8); 47 - #endif 48 46 dml_get_attr_decl(wm_dram_clock_change); 49 47 dml_get_attr_decl(wm_writeback_dram_clock_change); 50 48 dml_get_attr_decl(stutter_efficiency_no_vblank); ··· 106 108 dml_get_pipe_attr_decl(vupdate_offset); 107 109 dml_get_pipe_attr_decl(vupdate_width); 108 110 dml_get_pipe_attr_decl(vready_offset); 109 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 110 111 dml_get_pipe_attr_decl(vready_at_or_after_vsync); 111 112 dml_get_pipe_attr_decl(min_dst_y_next_start); 112 - #endif 113 113 114 114 double get_total_immediate_flip_bytes( 115 115 struct display_mode_lib *mode_lib, ··· 929 933 bool ClampMinDCFCLK; 930 934 bool AllowDramClockChangeOneDisplayVactive; 931 935 932 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 933 936 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation; 934 937 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency; 935 938 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData; ··· 969 974 int Z8NumberOfStutterBurstsPerFrame; 970 975 unsigned int MaximumDSCBitsPerComponent; 971 976 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; 972 - #endif 973 977 }; 974 978 975 979 bool CalculateMinAndMaxPrefetchMode(
-2
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
··· 112 112 case DCN_VERSION_3_01: 113 113 case DCN_VERSION_3_02: 114 114 case DCN_VERSION_3_03: 115 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 116 115 case DCN_VERSION_3_1: 117 - #endif 118 116 dal_hw_factory_dcn30_init(factory); 119 117 return true; 120 118 #endif
-2
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
··· 107 107 case DCN_VERSION_3_01: 108 108 case DCN_VERSION_3_02: 109 109 case DCN_VERSION_3_03: 110 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 111 110 case DCN_VERSION_3_1: 112 - #endif 113 111 dal_hw_translate_dcn30_init(translate); 114 112 return true; 115 113 #endif
-6
drivers/gpu/drm/amd/display/dc/inc/core_types.h
··· 338 338 uint32_t scaler : 1; 339 339 uint32_t viewport : 1; 340 340 uint32_t plane_changed : 1; 341 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 342 341 uint32_t det_size : 1; 343 - #endif 344 342 } bits; 345 343 uint32_t raw; 346 344 }; ··· 366 368 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 367 369 struct _vcs_dpi_display_rq_regs_st rq_regs; 368 370 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 369 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 370 371 int det_buffer_size_kb; 371 372 bool unbounded_req; 372 - #endif 373 373 #endif 374 374 union pipe_update_flags update_flags; 375 375 struct dwbc *dwbc; ··· 418 422 struct dc_clocks clk; 419 423 struct dcn_watermark_set watermarks; 420 424 struct dcn_bw_writeback bw_writeback; 421 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 422 425 int compbuf_size_kb; 423 - #endif 424 426 }; 425 427 426 428 union bw_output {
-2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
··· 91 91 unsigned int dispclk_mhz; 92 92 unsigned int dppclk_mhz; 93 93 unsigned int phyclk_mhz; 94 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 95 94 unsigned int wck_ratio; 96 - #endif 97 95 }; 98 96 99 97 /* This table is contiguous */
-6
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
··· 29 29 #include "dc_types.h" 30 30 #include "hw_shared.h" 31 31 32 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 33 32 enum phyd32clk_clock_source { 34 33 PHYD32CLKA, 35 34 PHYD32CLKB, ··· 54 55 DISPCLK_CHANGE_MODE_IMMEDIATE, 55 56 DISPCLK_CHANGE_MODE_RAMPING, 56 57 }; 57 - #endif 58 58 59 59 struct dccg { 60 60 struct dc_context *ctx; 61 61 const struct dccg_funcs *funcs; 62 62 int pipe_dppclk_khz[MAX_PIPES]; 63 63 int ref_dppclk; 64 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 65 64 int dtbclk_khz[MAX_PIPES]; 66 65 int audio_dtbclk_khz; 67 66 int ref_dtbclk_khz; 68 - #endif 69 67 }; 70 68 71 69 struct dccg_funcs { ··· 79 83 void (*otg_drop_pixel)(struct dccg *dccg, 80 84 uint32_t otg_inst); 81 85 void (*dccg_init)(struct dccg *dccg); 82 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 83 86 84 87 void (*set_physymclk)( 85 88 struct dccg *dccg, ··· 100 105 void (*set_dispclk_change_mode)( 101 106 struct dccg *dccg, 102 107 enum dentist_dispclk_change_mode change_mode); 103 - #endif 104 108 }; 105 109 106 110 #endif //__DAL_DCCG_H__
-2
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
··· 152 152 void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); 153 153 154 154 void (*init_watermarks)(struct hubbub *hubbub); 155 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 156 155 void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); 157 156 void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); 158 157 void (*init_crb)(struct hubbub *hubbub); 159 - #endif 160 158 }; 161 159 162 160 struct hubbub {
-2
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
··· 33 33 struct dchub_init_data; 34 34 struct cstate_pstate_watermarks_st { 35 35 uint32_t cstate_exit_ns; 36 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 37 36 uint32_t cstate_exit_z8_ns; 38 37 uint32_t cstate_enter_plus_exit_z8_ns; 39 - #endif 40 38 uint32_t cstate_enter_plus_exit_ns; 41 39 uint32_t pstate_change_ns; 42 40 };
-2
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
··· 173 173 174 174 bool (*enable_crtc)(struct timing_generator *tg); 175 175 bool (*disable_crtc)(struct timing_generator *tg); 176 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 177 176 bool (*immediate_disable_crtc)(struct timing_generator *tg); 178 - #endif 179 177 bool (*is_counter_moving)(struct timing_generator *tg); 180 178 void (*get_position)(struct timing_generator *tg, 181 179 struct crtc_position *position);
-2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
··· 236 236 const struct tg_color *solid_color, 237 237 int width, int height, int offset); 238 238 239 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 240 239 void (*z10_restore)(struct dc *dc); 241 - #endif 242 240 243 241 void (*update_visual_confirm_color)(struct dc *dc, 244 242 struct pipe_ctx *pipe_ctx,
-2
drivers/gpu/drm/amd/display/dc/irq/Makefile
··· 117 117 AMD_DAL_IRQ_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/irq/dcn303/,$(IRQ_DCN3_03)) 118 118 119 119 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_03) 120 - endif 121 120 122 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 123 121 ############################################################################### 124 122 # DCN 31 125 123 ###############################################################################
-3
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
··· 23 23 * 24 24 */ 25 25 26 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 27 - 28 26 #ifndef __DAL_IRQ_SERVICE_DCN31_H__ 29 27 #define __DAL_IRQ_SERVICE_DCN31_H__ 30 28 ··· 32 34 struct irq_service_init_data *init_data); 33 35 34 36 #endif /* __DAL_IRQ_SERVICE_DCN31_H__ */ 35 - #endif /* CONFIG_DRM_AMD_DC_DCN3_1 */
-8
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
··· 73 73 /* Forward declarations */ 74 74 struct dmub_srv; 75 75 struct dmub_srv_common_regs; 76 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 77 76 struct dmub_srv_dcn31_regs; 78 - #endif 79 77 80 78 struct dmcub_trace_buf_entry; 81 79 ··· 95 97 DMUB_ASIC_DCN301, 96 98 DMUB_ASIC_DCN302, 97 99 DMUB_ASIC_DCN303, 98 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 99 100 DMUB_ASIC_DCN31, 100 - #endif 101 101 DMUB_ASIC_MAX, 102 102 }; 103 103 ··· 234 238 uint32_t psp_version; 235 239 bool load_inst_const; 236 240 bool skip_panel_power_sequence; 237 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 238 241 bool disable_z10; 239 - #endif 240 242 }; 241 243 242 244 /** ··· 394 400 395 401 /* private: internal use only */ 396 402 const struct dmub_srv_common_regs *regs; 397 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 398 403 const struct dmub_srv_dcn31_regs *regs_dcn31; 399 - #endif 400 404 401 405 struct dmub_srv_base_funcs funcs; 402 406 struct dmub_srv_hw_funcs hw_funcs;
+1 -13
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
··· 362 362 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 363 363 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 364 364 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 365 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 366 365 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 367 - #else 368 - uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */ 369 - #endif 370 366 uint32_t reserved : 25; /**< reserved */ 371 367 } bits; /**< boot bits */ 372 368 uint32_t all; /**< 32-bit access to bits */ ··· 627 631 * Command type used for OUTBOX1 notification enable 628 632 */ 629 633 DMUB_CMD__OUTBOX1_ENABLE = 71, 630 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 631 634 /** 632 635 * Command type used for all idle optimization commands. 633 636 */ ··· 639 644 * Command type used for all panel control commands. 640 645 */ 641 646 DMUB_CMD__PANEL_CNTL = 74, 642 - #endif 643 647 /** 644 648 * Command type used for EDID CEA parsing 645 649 */ ··· 848 854 uint8_t reserved2; /**< Reserved bits */ 849 855 }; 850 856 851 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 852 - 853 857 /** 854 858 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 855 859 */ ··· 892 900 struct dmub_cmd_header header; /**< header */ 893 901 struct dmub_clocks clocks; /**< clock data */ 894 902 }; 895 - #endif 903 + 896 904 /** 897 905 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 898 906 */ ··· 2103 2111 struct dmub_optc_state dmub_optc_state_req; 2104 2112 }; 2105 2113 2106 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2107 2114 /** 2108 2115 * enum dmub_cmd_panel_cntl_type - Panel control command. 2109 2116 */ ··· 2137 2146 struct dmub_cmd_header header; /**< header */ 2138 2147 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2139 2148 }; 2140 - #endif 2141 2149 2142 2150 /** 2143 2151 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. ··· 2297 2307 * Definition of a DMUB_CMD__MALL command. 2298 2308 */ 2299 2309 struct dmub_rb_cmd_mall mall; 2300 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2301 2310 /** 2302 2311 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2303 2312 */ ··· 2311 2322 * Definition of DMUB_CMD__PANEL_CNTL commands. 2312 2323 */ 2313 2324 struct dmub_rb_cmd_panel_cntl panel_cntl; 2314 - #endif 2315 2325 /** 2316 2326 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2317 2327 */
+1 -5
drivers/gpu/drm/amd/display/dmub/src/Makefile
··· 21 21 # 22 22 23 23 DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o 24 - DMUB += dmub_dcn30.o dmub_dcn301.o 25 - DMUB += dmub_dcn302.o 26 - DMUB += dmub_dcn303.o 27 - ifdef CONFIG_DRM_AMD_DC_DCN3_1 24 + DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o 28 25 DMUB += dmub_dcn31.o 29 - endif 30 26 31 27 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) 32 28
-4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
··· 31 31 #include "dmub_dcn301.h" 32 32 #include "dmub_dcn302.h" 33 33 #include "dmub_dcn303.h" 34 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 35 34 #include "dmub_dcn31.h" 36 - #endif 37 35 #include "os_types.h" 38 36 /* 39 37 * Note: the DMUB service is standalone. No additional headers should be ··· 206 208 funcs->setup_windows = dmub_dcn30_setup_windows; 207 209 } 208 210 break; 209 - #ifdef CONFIG_DRM_AMD_DC_DCN3_1 210 211 211 212 case DMUB_ASIC_DCN31: 212 213 funcs->reset = dmub_dcn31_reset; ··· 238 241 funcs->get_current_time = dmub_dcn31_get_current_time; 239 242 240 243 break; 241 - #endif 242 244 243 245 default: 244 246 return false;
-2
drivers/gpu/drm/amd/display/include/dal_asic_id.h
··· 224 224 #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) 225 225 #endif 226 226 227 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 228 227 #define FAMILY_YELLOW_CARP 146 229 228 230 229 #define YELLOW_CARP_A0 0x01 ··· 232 233 233 234 #ifndef ASICREV_IS_YELLOW_CARP 234 235 #define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN)) 235 - #endif 236 236 #endif 237 237 238 238
-2
drivers/gpu/drm/amd/display/include/dal_types.h
··· 55 55 DCN_VERSION_3_01, 56 56 DCN_VERSION_3_02, 57 57 DCN_VERSION_3_03, 58 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 59 58 DCN_VERSION_3_1, 60 - #endif 61 59 DCN_VERSION_MAX 62 60 }; 63 61
-2
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
··· 172 172 return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE"; 173 173 case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE: 174 174 return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE"; 175 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 176 175 case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE: 177 176 return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE"; 178 - #endif 179 177 default: 180 178 return "MOD_HDCP_STATUS_UNKNOWN"; 181 179 }
+4 -14
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
··· 44 44 in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE; 45 45 in->process.msg3_desc.msg_size = 0; 46 46 } 47 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 47 + 48 48 static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v2( 49 49 struct mod_hdcp *hdcp, uint8_t index) 50 - #else 51 - enum mod_hdcp_status mod_hdcp_remove_display_from_topology( 52 - struct mod_hdcp *hdcp, uint8_t index) 53 - #endif 54 50 { 55 51 struct psp_context *psp = hdcp->config.psp.handle; 56 52 struct ta_dtm_shared_memory *dtm_cmd; ··· 80 84 mutex_unlock(&psp->dtm_context.mutex); 81 85 return status; 82 86 } 83 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 87 + 84 88 static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v3( 85 89 struct mod_hdcp *hdcp, uint8_t index) 86 90 { ··· 132 136 133 137 return status; 134 138 } 135 - #endif 136 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 139 + 137 140 static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v2( 138 141 struct mod_hdcp *hdcp, struct mod_hdcp_display *display) 139 - #else 140 - enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp, 141 - struct mod_hdcp_display *display) 142 - #endif 143 142 { 144 143 struct psp_context *psp = hdcp->config.psp.handle; 145 144 struct ta_dtm_shared_memory *dtm_cmd; ··· 180 189 return status; 181 190 } 182 191 183 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 184 192 static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v3( 185 193 struct mod_hdcp *hdcp, struct mod_hdcp_display *display) 186 194 { ··· 244 254 245 255 return status; 246 256 } 247 - #endif 257 + 248 258 enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp) 249 259 { 250 260
+2 -11
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
··· 44 44 enum ta_dtm_command { 45 45 TA_DTM_COMMAND__UNUSED_1 = 1, 46 46 TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2, 47 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 48 47 TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE, 49 48 TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3 50 - #else 51 - TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE 52 - #endif 53 49 }; 54 50 55 51 /* DTM related enumerations */ ··· 87 91 uint32_t max_hdcp_supported_version; 88 92 }; 89 93 90 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 91 94 /* For security reason/HW may change value, these encoder type enum values are not HW register values */ 92 95 /* Security code will check real HW register values and these SW enum values */ 93 96 enum ta_dtm_encoder_type { ··· 112 117 uint32_t phy_id; 113 118 uint32_t link_hdcp_cap; 114 119 }; 115 - #endif 120 + 116 121 struct ta_dtm_topology_assr_enable { 117 122 uint32_t display_topology_dig_be_index; 118 123 }; ··· 126 131 union ta_dtm_cmd_input { 127 132 struct ta_dtm_topology_update_input_v2 topology_update_v2; 128 133 struct ta_dtm_topology_assr_enable topology_assr_enable; 129 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 130 134 struct ta_dtm_topology_update_input_v3 topology_update_v3; 131 - #endif 132 135 }; 133 136 134 137 union ta_dtm_cmd_output { ··· 306 313 TA_HDCP2_VERSION_UNKNOWN = 0, 307 314 TA_HDCP2_VERSION_2_0 = 20, 308 315 TA_HDCP2_VERSION_2_1 = 21, 309 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 316 + TA_HDCP2_VERSION_2_2 = 22, 310 317 TA_HDCP2_VERSION_2_3 = 23, 311 - #endif 312 - TA_HDCP2_VERSION_2_2 = 22 313 318 }; 314 319 315 320 /* input/output structures for HDCP commands */
-10
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
··· 97 97 MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST, 98 98 MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, 99 99 MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, 100 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 101 100 MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, 102 - #endif 103 101 }; 104 102 105 103 struct mod_hdcp_displayport { ··· 121 123 MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED 122 124 }; 123 125 124 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 125 126 struct mod_hdcp_psp_caps { 126 127 uint8_t dtm_v3_supported; 127 128 uint8_t opm_state_query_supported; 128 129 }; 129 130 130 - #endif 131 131 enum mod_hdcp_display_disable_option { 132 132 MOD_HDCP_DISPLAY_NOT_DISABLE = 0, 133 133 MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION, ··· 158 162 struct mod_hdcp_psp { 159 163 void *handle; 160 164 void *funcs; 161 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 162 165 struct mod_hdcp_psp_caps caps; 163 - #endif 164 166 }; 165 167 166 168 struct mod_hdcp_display_adjustment { ··· 234 240 uint8_t index; 235 241 uint8_t controller; 236 242 uint8_t dig_fe; 237 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 238 243 uint8_t stream_enc_idx; 239 - #endif 240 244 union { 241 245 uint8_t vc_id; 242 246 }; ··· 247 255 enum mod_hdcp_operation_mode mode; 248 256 uint8_t dig_be; 249 257 uint8_t ddc_line; 250 - #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 251 258 uint8_t link_enc_idx; 252 259 uint8_t phy_idx; 253 260 uint8_t hdcp_supported_informational; 254 - #endif 255 261 union { 256 262 struct mod_hdcp_displayport dp; 257 263 struct mod_hdcp_hdmi hdmi;