memory: tegra: Split Tegra194 data into separate file

+1 -1

drivers/memory/tegra/Makefile

··· 8 8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o 9 9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o 10 10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o 11 - tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o 11 + tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o 12 12 13 13 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o 14 14

+5

drivers/memory/tegra/mc.h

··· 146 146 extern const struct tegra_mc_ops tegra30_mc_ops; 147 147 #endif 148 148 149 + #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ 150 + defined(CONFIG_ARCH_TEGRA_194_SOC) 151 + extern const struct tegra_mc_ops tegra186_mc_ops; 152 + #endif 153 + 149 154 extern const char * const tegra_mc_status_names[32]; 150 155 extern const char * const tegra_mc_error_names[8]; 151 156

+1 -1348

drivers/memory/tegra/tegra186.c

··· 15 15 #include <dt-bindings/memory/tegra186-mc.h> 16 16 #endif 17 17 18 - #if defined(CONFIG_ARCH_TEGRA_194_SOC) 19 - #include <dt-bindings/memory/tegra194-mc.h> 20 - #endif 21 - 22 18 static void tegra186_mc_program_sid(struct tegra_mc *mc) 23 19 { 24 20 unsigned int i; ··· 66 70 return 0; 67 71 } 68 72 69 - static const struct tegra_mc_ops tegra186_mc_ops = { 73 + const struct tegra_mc_ops tegra186_mc_ops = { 70 74 .probe = tegra186_mc_probe, 71 75 .remove = tegra186_mc_remove, 72 76 .resume = tegra186_mc_resume, ··· 800 804 const struct tegra_mc_soc tegra186_mc_soc = { 801 805 .num_clients = ARRAY_SIZE(tegra186_mc_clients), 802 806 .clients = tegra186_mc_clients, 803 - .num_address_bits = 40, 804 - .ops = &tegra186_mc_ops, 805 - }; 806 - #endif 807 - 808 - #if defined(CONFIG_ARCH_TEGRA_194_SOC) 809 - static const struct tegra_mc_client tegra194_mc_clients[] = { 810 - { 811 - .id = TEGRA194_MEMORY_CLIENT_PTCR, 812 - .name = "ptcr", 813 - .sid = TEGRA194_SID_PASSTHROUGH, 814 - .regs = { 815 - .sid = { 816 - .override = 0x000, 817 - .security = 0x004, 818 - }, 819 - }, 820 - }, { 821 - .id = TEGRA194_MEMORY_CLIENT_MIU7R, 822 - .name = "miu7r", 823 - .sid = TEGRA194_SID_MIU, 824 - .regs = { 825 - .sid = { 826 - .override = 0x008, 827 - .security = 0x00c, 828 - }, 829 - }, 830 - }, { 831 - .id = TEGRA194_MEMORY_CLIENT_MIU7W, 832 - .name = "miu7w", 833 - .sid = TEGRA194_SID_MIU, 834 - .regs = { 835 - .sid = { 836 - .override = 0x010, 837 - .security = 0x014, 838 - }, 839 - }, 840 - }, { 841 - .id = TEGRA194_MEMORY_CLIENT_HDAR, 842 - .name = "hdar", 843 - .sid = TEGRA194_SID_HDA, 844 - .regs = { 845 - .sid = { 846 - .override = 0x0a8, 847 - .security = 0x0ac, 848 - }, 849 - }, 850 - }, { 851 - .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR, 852 - .name = "host1xdmar", 853 - .sid = TEGRA194_SID_HOST1X, 854 - .regs = { 855 - .sid = { 856 - .override = 0x0b0, 857 - .security = 0x0b4, 858 - }, 859 - }, 860 - }, { 861 - .id = TEGRA194_MEMORY_CLIENT_NVENCSRD, 862 - .name = "nvencsrd", 863 - .sid = TEGRA194_SID_NVENC, 864 - .regs = { 865 - .sid = { 866 - .override = 0x0e0, 867 - .security = 0x0e4, 868 - }, 869 - }, 870 - }, { 871 - .id = TEGRA194_MEMORY_CLIENT_SATAR, 872 - .name = "satar", 873 - .sid = TEGRA194_SID_SATA, 874 - .regs = { 875 - .sid = { 876 - .override = 0x0f8, 877 - .security = 0x0fc, 878 - }, 879 - }, 880 - }, { 881 - .id = TEGRA194_MEMORY_CLIENT_MPCORER, 882 - .name = "mpcorer", 883 - .sid = TEGRA194_SID_PASSTHROUGH, 884 - .regs = { 885 - .sid = { 886 - .override = 0x138, 887 - .security = 0x13c, 888 - }, 889 - }, 890 - }, { 891 - .id = TEGRA194_MEMORY_CLIENT_NVENCSWR, 892 - .name = "nvencswr", 893 - .sid = TEGRA194_SID_NVENC, 894 - .regs = { 895 - .sid = { 896 - .override = 0x158, 897 - .security = 0x15c, 898 - }, 899 - }, 900 - }, { 901 - .id = TEGRA194_MEMORY_CLIENT_HDAW, 902 - .name = "hdaw", 903 - .sid = TEGRA194_SID_HDA, 904 - .regs = { 905 - .sid = { 906 - .override = 0x1a8, 907 - .security = 0x1ac, 908 - }, 909 - }, 910 - }, { 911 - .id = TEGRA194_MEMORY_CLIENT_MPCOREW, 912 - .name = "mpcorew", 913 - .sid = TEGRA194_SID_PASSTHROUGH, 914 - .regs = { 915 - .sid = { 916 - .override = 0x1c8, 917 - .security = 0x1cc, 918 - }, 919 - }, 920 - }, { 921 - .id = TEGRA194_MEMORY_CLIENT_SATAW, 922 - .name = "sataw", 923 - .sid = TEGRA194_SID_SATA, 924 - .regs = { 925 - .sid = { 926 - .override = 0x1e8, 927 - .security = 0x1ec, 928 - }, 929 - }, 930 - }, { 931 - .id = TEGRA194_MEMORY_CLIENT_ISPRA, 932 - .name = "ispra", 933 - .sid = TEGRA194_SID_ISP, 934 - .regs = { 935 - .sid = { 936 - .override = 0x220, 937 - .security = 0x224, 938 - }, 939 - }, 940 - }, { 941 - .id = TEGRA194_MEMORY_CLIENT_ISPFALR, 942 - .name = "ispfalr", 943 - .sid = TEGRA194_SID_ISP_FALCON, 944 - .regs = { 945 - .sid = { 946 - .override = 0x228, 947 - .security = 0x22c, 948 - }, 949 - }, 950 - }, { 951 - .id = TEGRA194_MEMORY_CLIENT_ISPWA, 952 - .name = "ispwa", 953 - .sid = TEGRA194_SID_ISP, 954 - .regs = { 955 - .sid = { 956 - .override = 0x230, 957 - .security = 0x234, 958 - }, 959 - }, 960 - }, { 961 - .id = TEGRA194_MEMORY_CLIENT_ISPWB, 962 - .name = "ispwb", 963 - .sid = TEGRA194_SID_ISP, 964 - .regs = { 965 - .sid = { 966 - .override = 0x238, 967 - .security = 0x23c, 968 - }, 969 - }, 970 - }, { 971 - .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR, 972 - .name = "xusb_hostr", 973 - .sid = TEGRA194_SID_XUSB_HOST, 974 - .regs = { 975 - .sid = { 976 - .override = 0x250, 977 - .security = 0x254, 978 - }, 979 - }, 980 - }, { 981 - .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW, 982 - .name = "xusb_hostw", 983 - .sid = TEGRA194_SID_XUSB_HOST, 984 - .regs = { 985 - .sid = { 986 - .override = 0x258, 987 - .security = 0x25c, 988 - }, 989 - }, 990 - }, { 991 - .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR, 992 - .name = "xusb_devr", 993 - .sid = TEGRA194_SID_XUSB_DEV, 994 - .regs = { 995 - .sid = { 996 - .override = 0x260, 997 - .security = 0x264, 998 - }, 999 - }, 1000 - }, { 1001 - .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW, 1002 - .name = "xusb_devw", 1003 - .sid = TEGRA194_SID_XUSB_DEV, 1004 - .regs = { 1005 - .sid = { 1006 - .override = 0x268, 1007 - .security = 0x26c, 1008 - }, 1009 - }, 1010 - }, { 1011 - .id = TEGRA194_MEMORY_CLIENT_SDMMCRA, 1012 - .name = "sdmmcra", 1013 - .sid = TEGRA194_SID_SDMMC1, 1014 - .regs = { 1015 - .sid = { 1016 - .override = 0x300, 1017 - .security = 0x304, 1018 - }, 1019 - }, 1020 - }, { 1021 - .id = TEGRA194_MEMORY_CLIENT_SDMMCR, 1022 - .name = "sdmmcr", 1023 - .sid = TEGRA194_SID_SDMMC3, 1024 - .regs = { 1025 - .sid = { 1026 - .override = 0x310, 1027 - .security = 0x314, 1028 - }, 1029 - }, 1030 - }, { 1031 - .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB, 1032 - .name = "sdmmcrab", 1033 - .sid = TEGRA194_SID_SDMMC4, 1034 - .regs = { 1035 - .sid = { 1036 - .override = 0x318, 1037 - .security = 0x31c, 1038 - }, 1039 - }, 1040 - }, { 1041 - .id = TEGRA194_MEMORY_CLIENT_SDMMCWA, 1042 - .name = "sdmmcwa", 1043 - .sid = TEGRA194_SID_SDMMC1, 1044 - .regs = { 1045 - .sid = { 1046 - .override = 0x320, 1047 - .security = 0x324, 1048 - }, 1049 - }, 1050 - }, { 1051 - .id = TEGRA194_MEMORY_CLIENT_SDMMCW, 1052 - .name = "sdmmcw", 1053 - .sid = TEGRA194_SID_SDMMC3, 1054 - .regs = { 1055 - .sid = { 1056 - .override = 0x330, 1057 - .security = 0x334, 1058 - }, 1059 - }, 1060 - }, { 1061 - .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB, 1062 - .name = "sdmmcwab", 1063 - .sid = TEGRA194_SID_SDMMC4, 1064 - .regs = { 1065 - .sid = { 1066 - .override = 0x338, 1067 - .security = 0x33c, 1068 - }, 1069 - }, 1070 - }, { 1071 - .id = TEGRA194_MEMORY_CLIENT_VICSRD, 1072 - .name = "vicsrd", 1073 - .sid = TEGRA194_SID_VIC, 1074 - .regs = { 1075 - .sid = { 1076 - .override = 0x360, 1077 - .security = 0x364, 1078 - }, 1079 - }, 1080 - }, { 1081 - .id = TEGRA194_MEMORY_CLIENT_VICSWR, 1082 - .name = "vicswr", 1083 - .sid = TEGRA194_SID_VIC, 1084 - .regs = { 1085 - .sid = { 1086 - .override = 0x368, 1087 - .security = 0x36c, 1088 - }, 1089 - }, 1090 - }, { 1091 - .id = TEGRA194_MEMORY_CLIENT_VIW, 1092 - .name = "viw", 1093 - .sid = TEGRA194_SID_VI, 1094 - .regs = { 1095 - .sid = { 1096 - .override = 0x390, 1097 - .security = 0x394, 1098 - }, 1099 - }, 1100 - }, { 1101 - .id = TEGRA194_MEMORY_CLIENT_NVDECSRD, 1102 - .name = "nvdecsrd", 1103 - .sid = TEGRA194_SID_NVDEC, 1104 - .regs = { 1105 - .sid = { 1106 - .override = 0x3c0, 1107 - .security = 0x3c4, 1108 - }, 1109 - }, 1110 - }, { 1111 - .id = TEGRA194_MEMORY_CLIENT_NVDECSWR, 1112 - .name = "nvdecswr", 1113 - .sid = TEGRA194_SID_NVDEC, 1114 - .regs = { 1115 - .sid = { 1116 - .override = 0x3c8, 1117 - .security = 0x3cc, 1118 - }, 1119 - }, 1120 - }, { 1121 - .id = TEGRA194_MEMORY_CLIENT_APER, 1122 - .name = "aper", 1123 - .sid = TEGRA194_SID_APE, 1124 - .regs = { 1125 - .sid = { 1126 - .override = 0x3c0, 1127 - .security = 0x3c4, 1128 - }, 1129 - }, 1130 - }, { 1131 - .id = TEGRA194_MEMORY_CLIENT_APEW, 1132 - .name = "apew", 1133 - .sid = TEGRA194_SID_APE, 1134 - .regs = { 1135 - .sid = { 1136 - .override = 0x3d0, 1137 - .security = 0x3d4, 1138 - }, 1139 - }, 1140 - }, { 1141 - .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD, 1142 - .name = "nvjpgsrd", 1143 - .sid = TEGRA194_SID_NVJPG, 1144 - .regs = { 1145 - .sid = { 1146 - .override = 0x3f0, 1147 - .security = 0x3f4, 1148 - }, 1149 - }, 1150 - }, { 1151 - .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR, 1152 - .name = "nvjpgswr", 1153 - .sid = TEGRA194_SID_NVJPG, 1154 - .regs = { 1155 - .sid = { 1156 - .override = 0x3f0, 1157 - .security = 0x3f4, 1158 - }, 1159 - }, 1160 - }, { 1161 - .name = "axiapr", 1162 - .id = TEGRA194_MEMORY_CLIENT_AXIAPR, 1163 - .sid = TEGRA194_SID_PASSTHROUGH, 1164 - .regs = { 1165 - .sid = { 1166 - .override = 0x410, 1167 - .security = 0x414, 1168 - }, 1169 - }, 1170 - }, { 1171 - .id = TEGRA194_MEMORY_CLIENT_AXIAPW, 1172 - .name = "axiapw", 1173 - .sid = TEGRA194_SID_PASSTHROUGH, 1174 - .regs = { 1175 - .sid = { 1176 - .override = 0x418, 1177 - .security = 0x41c, 1178 - }, 1179 - }, 1180 - }, { 1181 - .id = TEGRA194_MEMORY_CLIENT_ETRR, 1182 - .name = "etrr", 1183 - .sid = TEGRA194_SID_ETR, 1184 - .regs = { 1185 - .sid = { 1186 - .override = 0x420, 1187 - .security = 0x424, 1188 - }, 1189 - }, 1190 - }, { 1191 - .id = TEGRA194_MEMORY_CLIENT_ETRW, 1192 - .name = "etrw", 1193 - .sid = TEGRA194_SID_ETR, 1194 - .regs = { 1195 - .sid = { 1196 - .override = 0x428, 1197 - .security = 0x42c, 1198 - }, 1199 - }, 1200 - }, { 1201 - .id = TEGRA194_MEMORY_CLIENT_AXISR, 1202 - .name = "axisr", 1203 - .sid = TEGRA194_SID_PASSTHROUGH, 1204 - .regs = { 1205 - .sid = { 1206 - .override = 0x460, 1207 - .security = 0x464, 1208 - }, 1209 - }, 1210 - }, { 1211 - .id = TEGRA194_MEMORY_CLIENT_AXISW, 1212 - .name = "axisw", 1213 - .sid = TEGRA194_SID_PASSTHROUGH, 1214 - .regs = { 1215 - .sid = { 1216 - .override = 0x468, 1217 - .security = 0x46c, 1218 - }, 1219 - }, 1220 - }, { 1221 - .id = TEGRA194_MEMORY_CLIENT_EQOSR, 1222 - .name = "eqosr", 1223 - .sid = TEGRA194_SID_EQOS, 1224 - .regs = { 1225 - .sid = { 1226 - .override = 0x470, 1227 - .security = 0x474, 1228 - }, 1229 - }, 1230 - }, { 1231 - .name = "eqosw", 1232 - .id = TEGRA194_MEMORY_CLIENT_EQOSW, 1233 - .sid = TEGRA194_SID_EQOS, 1234 - .regs = { 1235 - .sid = { 1236 - .override = 0x478, 1237 - .security = 0x47c, 1238 - }, 1239 - }, 1240 - }, { 1241 - .id = TEGRA194_MEMORY_CLIENT_UFSHCR, 1242 - .name = "ufshcr", 1243 - .sid = TEGRA194_SID_UFSHC, 1244 - .regs = { 1245 - .sid = { 1246 - .override = 0x480, 1247 - .security = 0x484, 1248 - }, 1249 - }, 1250 - }, { 1251 - .id = TEGRA194_MEMORY_CLIENT_UFSHCW, 1252 - .name = "ufshcw", 1253 - .sid = TEGRA194_SID_UFSHC, 1254 - .regs = { 1255 - .sid = { 1256 - .override = 0x488, 1257 - .security = 0x48c, 1258 - }, 1259 - }, 1260 - }, { 1261 - .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR, 1262 - .name = "nvdisplayr", 1263 - .sid = TEGRA194_SID_NVDISPLAY, 1264 - .regs = { 1265 - .sid = { 1266 - .override = 0x490, 1267 - .security = 0x494, 1268 - }, 1269 - }, 1270 - }, { 1271 - .id = TEGRA194_MEMORY_CLIENT_BPMPR, 1272 - .name = "bpmpr", 1273 - .sid = TEGRA194_SID_BPMP, 1274 - .regs = { 1275 - .sid = { 1276 - .override = 0x498, 1277 - .security = 0x49c, 1278 - }, 1279 - }, 1280 - }, { 1281 - .id = TEGRA194_MEMORY_CLIENT_BPMPW, 1282 - .name = "bpmpw", 1283 - .sid = TEGRA194_SID_BPMP, 1284 - .regs = { 1285 - .sid = { 1286 - .override = 0x4a0, 1287 - .security = 0x4a4, 1288 - }, 1289 - }, 1290 - }, { 1291 - .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR, 1292 - .name = "bpmpdmar", 1293 - .sid = TEGRA194_SID_BPMP, 1294 - .regs = { 1295 - .sid = { 1296 - .override = 0x4a8, 1297 - .security = 0x4ac, 1298 - }, 1299 - }, 1300 - }, { 1301 - .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW, 1302 - .name = "bpmpdmaw", 1303 - .sid = TEGRA194_SID_BPMP, 1304 - .regs = { 1305 - .sid = { 1306 - .override = 0x4b0, 1307 - .security = 0x4b4, 1308 - }, 1309 - }, 1310 - }, { 1311 - .id = TEGRA194_MEMORY_CLIENT_AONR, 1312 - .name = "aonr", 1313 - .sid = TEGRA194_SID_AON, 1314 - .regs = { 1315 - .sid = { 1316 - .override = 0x4b8, 1317 - .security = 0x4bc, 1318 - }, 1319 - }, 1320 - }, { 1321 - .id = TEGRA194_MEMORY_CLIENT_AONW, 1322 - .name = "aonw", 1323 - .sid = TEGRA194_SID_AON, 1324 - .regs = { 1325 - .sid = { 1326 - .override = 0x4c0, 1327 - .security = 0x4c4, 1328 - }, 1329 - }, 1330 - }, { 1331 - .id = TEGRA194_MEMORY_CLIENT_AONDMAR, 1332 - .name = "aondmar", 1333 - .sid = TEGRA194_SID_AON, 1334 - .regs = { 1335 - .sid = { 1336 - .override = 0x4c8, 1337 - .security = 0x4cc, 1338 - }, 1339 - }, 1340 - }, { 1341 - .id = TEGRA194_MEMORY_CLIENT_AONDMAW, 1342 - .name = "aondmaw", 1343 - .sid = TEGRA194_SID_AON, 1344 - .regs = { 1345 - .sid = { 1346 - .override = 0x4d0, 1347 - .security = 0x4d4, 1348 - }, 1349 - }, 1350 - }, { 1351 - .id = TEGRA194_MEMORY_CLIENT_SCER, 1352 - .name = "scer", 1353 - .sid = TEGRA194_SID_SCE, 1354 - .regs = { 1355 - .sid = { 1356 - .override = 0x4d8, 1357 - .security = 0x4dc, 1358 - }, 1359 - }, 1360 - }, { 1361 - .id = TEGRA194_MEMORY_CLIENT_SCEW, 1362 - .name = "scew", 1363 - .sid = TEGRA194_SID_SCE, 1364 - .regs = { 1365 - .sid = { 1366 - .override = 0x4e0, 1367 - .security = 0x4e4, 1368 - }, 1369 - }, 1370 - }, { 1371 - .id = TEGRA194_MEMORY_CLIENT_SCEDMAR, 1372 - .name = "scedmar", 1373 - .sid = TEGRA194_SID_SCE, 1374 - .regs = { 1375 - .sid = { 1376 - .override = 0x4e8, 1377 - .security = 0x4ec, 1378 - }, 1379 - }, 1380 - }, { 1381 - .id = TEGRA194_MEMORY_CLIENT_SCEDMAW, 1382 - .name = "scedmaw", 1383 - .sid = TEGRA194_SID_SCE, 1384 - .regs = { 1385 - .sid = { 1386 - .override = 0x4f0, 1387 - .security = 0x4f4, 1388 - }, 1389 - }, 1390 - }, { 1391 - .id = TEGRA194_MEMORY_CLIENT_APEDMAR, 1392 - .name = "apedmar", 1393 - .sid = TEGRA194_SID_APE, 1394 - .regs = { 1395 - .sid = { 1396 - .override = 0x4f8, 1397 - .security = 0x4fc, 1398 - }, 1399 - }, 1400 - }, { 1401 - .id = TEGRA194_MEMORY_CLIENT_APEDMAW, 1402 - .name = "apedmaw", 1403 - .sid = TEGRA194_SID_APE, 1404 - .regs = { 1405 - .sid = { 1406 - .override = 0x500, 1407 - .security = 0x504, 1408 - }, 1409 - }, 1410 - }, { 1411 - .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1, 1412 - .name = "nvdisplayr1", 1413 - .sid = TEGRA194_SID_NVDISPLAY, 1414 - .regs = { 1415 - .sid = { 1416 - .override = 0x508, 1417 - .security = 0x50c, 1418 - }, 1419 - }, 1420 - }, { 1421 - .id = TEGRA194_MEMORY_CLIENT_VICSRD1, 1422 - .name = "vicsrd1", 1423 - .sid = TEGRA194_SID_VIC, 1424 - .regs = { 1425 - .sid = { 1426 - .override = 0x510, 1427 - .security = 0x514, 1428 - }, 1429 - }, 1430 - }, { 1431 - .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1, 1432 - .name = "nvdecsrd1", 1433 - .sid = TEGRA194_SID_NVDEC, 1434 - .regs = { 1435 - .sid = { 1436 - .override = 0x518, 1437 - .security = 0x51c, 1438 - }, 1439 - }, 1440 - }, { 1441 - .id = TEGRA194_MEMORY_CLIENT_MIU0R, 1442 - .name = "miu0r", 1443 - .sid = TEGRA194_SID_MIU, 1444 - .regs = { 1445 - .sid = { 1446 - .override = 0x530, 1447 - .security = 0x534, 1448 - }, 1449 - }, 1450 - }, { 1451 - .name = "miu0w", 1452 - .id = TEGRA194_MEMORY_CLIENT_MIU0W, 1453 - .sid = TEGRA194_SID_MIU, 1454 - .regs = { 1455 - .sid = { 1456 - .override = 0x538, 1457 - .security = 0x53c, 1458 - }, 1459 - }, 1460 - }, { 1461 - .id = TEGRA194_MEMORY_CLIENT_MIU1R, 1462 - .name = "miu1r", 1463 - .sid = TEGRA194_SID_MIU, 1464 - .regs = { 1465 - .sid = { 1466 - .override = 0x540, 1467 - .security = 0x544, 1468 - }, 1469 - }, 1470 - }, { 1471 - .id = TEGRA194_MEMORY_CLIENT_MIU1W, 1472 - .name = "miu1w", 1473 - .sid = TEGRA194_SID_MIU, 1474 - .regs = { 1475 - .sid = { 1476 - .override = 0x548, 1477 - .security = 0x54c, 1478 - }, 1479 - }, 1480 - }, { 1481 - .id = TEGRA194_MEMORY_CLIENT_MIU2R, 1482 - .name = "miu2r", 1483 - .sid = TEGRA194_SID_MIU, 1484 - .regs = { 1485 - .sid = { 1486 - .override = 0x570, 1487 - .security = 0x574, 1488 - }, 1489 - }, 1490 - }, { 1491 - .id = TEGRA194_MEMORY_CLIENT_MIU2W, 1492 - .name = "miu2w", 1493 - .sid = TEGRA194_SID_MIU, 1494 - .regs = { 1495 - .sid = { 1496 - .override = 0x578, 1497 - .security = 0x57c, 1498 - }, 1499 - }, 1500 - }, { 1501 - .id = TEGRA194_MEMORY_CLIENT_MIU3R, 1502 - .name = "miu3r", 1503 - .sid = TEGRA194_SID_MIU, 1504 - .regs = { 1505 - .sid = { 1506 - .override = 0x580, 1507 - .security = 0x584, 1508 - }, 1509 - }, 1510 - }, { 1511 - .id = TEGRA194_MEMORY_CLIENT_MIU3W, 1512 - .name = "miu3w", 1513 - .sid = TEGRA194_SID_MIU, 1514 - .regs = { 1515 - .sid = { 1516 - .override = 0x588, 1517 - .security = 0x58c, 1518 - }, 1519 - }, 1520 - }, { 1521 - .id = TEGRA194_MEMORY_CLIENT_MIU4R, 1522 - .name = "miu4r", 1523 - .sid = TEGRA194_SID_MIU, 1524 - .regs = { 1525 - .sid = { 1526 - .override = 0x590, 1527 - .security = 0x594, 1528 - }, 1529 - }, 1530 - }, { 1531 - .id = TEGRA194_MEMORY_CLIENT_MIU4W, 1532 - .name = "miu4w", 1533 - .sid = TEGRA194_SID_MIU, 1534 - .regs = { 1535 - .sid = { 1536 - .override = 0x598, 1537 - .security = 0x59c, 1538 - }, 1539 - }, 1540 - }, { 1541 - .id = TEGRA194_MEMORY_CLIENT_DPMUR, 1542 - .name = "dpmur", 1543 - .sid = TEGRA194_SID_PASSTHROUGH, 1544 - .regs = { 1545 - .sid = { 1546 - .override = 0x598, 1547 - .security = 0x59c, 1548 - }, 1549 - }, 1550 - }, { 1551 - .id = TEGRA194_MEMORY_CLIENT_VIFALR, 1552 - .name = "vifalr", 1553 - .sid = TEGRA194_SID_VI_FALCON, 1554 - .regs = { 1555 - .sid = { 1556 - .override = 0x5e0, 1557 - .security = 0x5e4, 1558 - }, 1559 - }, 1560 - }, { 1561 - .id = TEGRA194_MEMORY_CLIENT_VIFALW, 1562 - .name = "vifalw", 1563 - .sid = TEGRA194_SID_VI_FALCON, 1564 - .regs = { 1565 - .sid = { 1566 - .override = 0x5e8, 1567 - .security = 0x5ec, 1568 - }, 1569 - }, 1570 - }, { 1571 - .id = TEGRA194_MEMORY_CLIENT_DLA0RDA, 1572 - .name = "dla0rda", 1573 - .sid = TEGRA194_SID_NVDLA0, 1574 - .regs = { 1575 - .sid = { 1576 - .override = 0x5f0, 1577 - .security = 0x5f4, 1578 - }, 1579 - }, 1580 - }, { 1581 - .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB, 1582 - .name = "dla0falrdb", 1583 - .sid = TEGRA194_SID_NVDLA0, 1584 - .regs = { 1585 - .sid = { 1586 - .override = 0x5f8, 1587 - .security = 0x5fc, 1588 - }, 1589 - }, 1590 - }, { 1591 - .id = TEGRA194_MEMORY_CLIENT_DLA0WRA, 1592 - .name = "dla0wra", 1593 - .sid = TEGRA194_SID_NVDLA0, 1594 - .regs = { 1595 - .sid = { 1596 - .override = 0x600, 1597 - .security = 0x604, 1598 - }, 1599 - }, 1600 - }, { 1601 - .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB, 1602 - .name = "dla0falwrb", 1603 - .sid = TEGRA194_SID_NVDLA0, 1604 - .regs = { 1605 - .sid = { 1606 - .override = 0x608, 1607 - .security = 0x60c, 1608 - }, 1609 - }, 1610 - }, { 1611 - .id = TEGRA194_MEMORY_CLIENT_DLA1RDA, 1612 - .name = "dla1rda", 1613 - .sid = TEGRA194_SID_NVDLA1, 1614 - .regs = { 1615 - .sid = { 1616 - .override = 0x610, 1617 - .security = 0x614, 1618 - }, 1619 - }, 1620 - }, { 1621 - .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB, 1622 - .name = "dla1falrdb", 1623 - .sid = TEGRA194_SID_NVDLA1, 1624 - .regs = { 1625 - .sid = { 1626 - .override = 0x618, 1627 - .security = 0x61c, 1628 - }, 1629 - }, 1630 - }, { 1631 - .id = TEGRA194_MEMORY_CLIENT_DLA1WRA, 1632 - .name = "dla1wra", 1633 - .sid = TEGRA194_SID_NVDLA1, 1634 - .regs = { 1635 - .sid = { 1636 - .override = 0x620, 1637 - .security = 0x624, 1638 - }, 1639 - }, 1640 - }, { 1641 - .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB, 1642 - .name = "dla1falwrb", 1643 - .sid = TEGRA194_SID_NVDLA1, 1644 - .regs = { 1645 - .sid = { 1646 - .override = 0x628, 1647 - .security = 0x62c, 1648 - }, 1649 - }, 1650 - }, { 1651 - .id = TEGRA194_MEMORY_CLIENT_PVA0RDA, 1652 - .name = "pva0rda", 1653 - .sid = TEGRA194_SID_PVA0, 1654 - .regs = { 1655 - .sid = { 1656 - .override = 0x630, 1657 - .security = 0x634, 1658 - }, 1659 - }, 1660 - }, { 1661 - .id = TEGRA194_MEMORY_CLIENT_PVA0RDB, 1662 - .name = "pva0rdb", 1663 - .sid = TEGRA194_SID_PVA0, 1664 - .regs = { 1665 - .sid = { 1666 - .override = 0x638, 1667 - .security = 0x63c, 1668 - }, 1669 - }, 1670 - }, { 1671 - .id = TEGRA194_MEMORY_CLIENT_PVA0RDC, 1672 - .name = "pva0rdc", 1673 - .sid = TEGRA194_SID_PVA0, 1674 - .regs = { 1675 - .sid = { 1676 - .override = 0x640, 1677 - .security = 0x644, 1678 - }, 1679 - }, 1680 - }, { 1681 - .id = TEGRA194_MEMORY_CLIENT_PVA0WRA, 1682 - .name = "pva0wra", 1683 - .sid = TEGRA194_SID_PVA0, 1684 - .regs = { 1685 - .sid = { 1686 - .override = 0x648, 1687 - .security = 0x64c, 1688 - }, 1689 - }, 1690 - }, { 1691 - .id = TEGRA194_MEMORY_CLIENT_PVA0WRB, 1692 - .name = "pva0wrb", 1693 - .sid = TEGRA194_SID_PVA0, 1694 - .regs = { 1695 - .sid = { 1696 - .override = 0x650, 1697 - .security = 0x654, 1698 - }, 1699 - }, 1700 - }, { 1701 - .id = TEGRA194_MEMORY_CLIENT_PVA0WRC, 1702 - .name = "pva0wrc", 1703 - .sid = TEGRA194_SID_PVA0, 1704 - .regs = { 1705 - .sid = { 1706 - .override = 0x658, 1707 - .security = 0x65c, 1708 - }, 1709 - }, 1710 - }, { 1711 - .id = TEGRA194_MEMORY_CLIENT_PVA1RDA, 1712 - .name = "pva1rda", 1713 - .sid = TEGRA194_SID_PVA1, 1714 - .regs = { 1715 - .sid = { 1716 - .override = 0x660, 1717 - .security = 0x664, 1718 - }, 1719 - }, 1720 - }, { 1721 - .id = TEGRA194_MEMORY_CLIENT_PVA1RDB, 1722 - .name = "pva1rdb", 1723 - .sid = TEGRA194_SID_PVA1, 1724 - .regs = { 1725 - .sid = { 1726 - .override = 0x668, 1727 - .security = 0x66c, 1728 - }, 1729 - }, 1730 - }, { 1731 - .id = TEGRA194_MEMORY_CLIENT_PVA1RDC, 1732 - .name = "pva1rdc", 1733 - .sid = TEGRA194_SID_PVA1, 1734 - .regs = { 1735 - .sid = { 1736 - .override = 0x670, 1737 - .security = 0x674, 1738 - }, 1739 - }, 1740 - }, { 1741 - .id = TEGRA194_MEMORY_CLIENT_PVA1WRA, 1742 - .name = "pva1wra", 1743 - .sid = TEGRA194_SID_PVA1, 1744 - .regs = { 1745 - .sid = { 1746 - .override = 0x678, 1747 - .security = 0x67c, 1748 - }, 1749 - }, 1750 - }, { 1751 - .id = TEGRA194_MEMORY_CLIENT_PVA1WRB, 1752 - .name = "pva1wrb", 1753 - .sid = TEGRA194_SID_PVA1, 1754 - .regs = { 1755 - .sid = { 1756 - .override = 0x680, 1757 - .security = 0x684, 1758 - }, 1759 - }, 1760 - }, { 1761 - .id = TEGRA194_MEMORY_CLIENT_PVA1WRC, 1762 - .name = "pva1wrc", 1763 - .sid = TEGRA194_SID_PVA1, 1764 - .regs = { 1765 - .sid = { 1766 - .override = 0x688, 1767 - .security = 0x68c, 1768 - }, 1769 - }, 1770 - }, { 1771 - .id = TEGRA194_MEMORY_CLIENT_RCER, 1772 - .name = "rcer", 1773 - .sid = TEGRA194_SID_RCE, 1774 - .regs = { 1775 - .sid = { 1776 - .override = 0x690, 1777 - .security = 0x694, 1778 - }, 1779 - }, 1780 - }, { 1781 - .id = TEGRA194_MEMORY_CLIENT_RCEW, 1782 - .name = "rcew", 1783 - .sid = TEGRA194_SID_RCE, 1784 - .regs = { 1785 - .sid = { 1786 - .override = 0x698, 1787 - .security = 0x69c, 1788 - }, 1789 - }, 1790 - }, { 1791 - .id = TEGRA194_MEMORY_CLIENT_RCEDMAR, 1792 - .name = "rcedmar", 1793 - .sid = TEGRA194_SID_RCE, 1794 - .regs = { 1795 - .sid = { 1796 - .override = 0x6a0, 1797 - .security = 0x6a4, 1798 - }, 1799 - }, 1800 - }, { 1801 - .id = TEGRA194_MEMORY_CLIENT_RCEDMAW, 1802 - .name = "rcedmaw", 1803 - .sid = TEGRA194_SID_RCE, 1804 - .regs = { 1805 - .sid = { 1806 - .override = 0x6a8, 1807 - .security = 0x6ac, 1808 - }, 1809 - }, 1810 - }, { 1811 - .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD, 1812 - .name = "nvenc1srd", 1813 - .sid = TEGRA194_SID_NVENC1, 1814 - .regs = { 1815 - .sid = { 1816 - .override = 0x6b0, 1817 - .security = 0x6b4, 1818 - }, 1819 - }, 1820 - }, { 1821 - .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR, 1822 - .name = "nvenc1swr", 1823 - .sid = TEGRA194_SID_NVENC1, 1824 - .regs = { 1825 - .sid = { 1826 - .override = 0x6b8, 1827 - .security = 0x6bc, 1828 - }, 1829 - }, 1830 - }, { 1831 - .id = TEGRA194_MEMORY_CLIENT_PCIE0R, 1832 - .name = "pcie0r", 1833 - .sid = TEGRA194_SID_PCIE0, 1834 - .regs = { 1835 - .sid = { 1836 - .override = 0x6c0, 1837 - .security = 0x6c4, 1838 - }, 1839 - }, 1840 - }, { 1841 - .id = TEGRA194_MEMORY_CLIENT_PCIE0W, 1842 - .name = "pcie0w", 1843 - .sid = TEGRA194_SID_PCIE0, 1844 - .regs = { 1845 - .sid = { 1846 - .override = 0x6c8, 1847 - .security = 0x6cc, 1848 - }, 1849 - }, 1850 - }, { 1851 - .id = TEGRA194_MEMORY_CLIENT_PCIE1R, 1852 - .name = "pcie1r", 1853 - .sid = TEGRA194_SID_PCIE1, 1854 - .regs = { 1855 - .sid = { 1856 - .override = 0x6d0, 1857 - .security = 0x6d4, 1858 - }, 1859 - }, 1860 - }, { 1861 - .id = TEGRA194_MEMORY_CLIENT_PCIE1W, 1862 - .name = "pcie1w", 1863 - .sid = TEGRA194_SID_PCIE1, 1864 - .regs = { 1865 - .sid = { 1866 - .override = 0x6d8, 1867 - .security = 0x6dc, 1868 - }, 1869 - }, 1870 - }, { 1871 - .id = TEGRA194_MEMORY_CLIENT_PCIE2AR, 1872 - .name = "pcie2ar", 1873 - .sid = TEGRA194_SID_PCIE2, 1874 - .regs = { 1875 - .sid = { 1876 - .override = 0x6e0, 1877 - .security = 0x6e4, 1878 - }, 1879 - }, 1880 - }, { 1881 - .id = TEGRA194_MEMORY_CLIENT_PCIE2AW, 1882 - .name = "pcie2aw", 1883 - .sid = TEGRA194_SID_PCIE2, 1884 - .regs = { 1885 - .sid = { 1886 - .override = 0x6e8, 1887 - .security = 0x6ec, 1888 - }, 1889 - }, 1890 - }, { 1891 - .id = TEGRA194_MEMORY_CLIENT_PCIE3R, 1892 - .name = "pcie3r", 1893 - .sid = TEGRA194_SID_PCIE3, 1894 - .regs = { 1895 - .sid = { 1896 - .override = 0x6f0, 1897 - .security = 0x6f4, 1898 - }, 1899 - }, 1900 - }, { 1901 - .id = TEGRA194_MEMORY_CLIENT_PCIE3W, 1902 - .name = "pcie3w", 1903 - .sid = TEGRA194_SID_PCIE3, 1904 - .regs = { 1905 - .sid = { 1906 - .override = 0x6f8, 1907 - .security = 0x6fc, 1908 - }, 1909 - }, 1910 - }, { 1911 - .id = TEGRA194_MEMORY_CLIENT_PCIE4R, 1912 - .name = "pcie4r", 1913 - .sid = TEGRA194_SID_PCIE4, 1914 - .regs = { 1915 - .sid = { 1916 - .override = 0x700, 1917 - .security = 0x704, 1918 - }, 1919 - }, 1920 - }, { 1921 - .id = TEGRA194_MEMORY_CLIENT_PCIE4W, 1922 - .name = "pcie4w", 1923 - .sid = TEGRA194_SID_PCIE4, 1924 - .regs = { 1925 - .sid = { 1926 - .override = 0x708, 1927 - .security = 0x70c, 1928 - }, 1929 - }, 1930 - }, { 1931 - .id = TEGRA194_MEMORY_CLIENT_PCIE5R, 1932 - .name = "pcie5r", 1933 - .sid = TEGRA194_SID_PCIE5, 1934 - .regs = { 1935 - .sid = { 1936 - .override = 0x710, 1937 - .security = 0x714, 1938 - }, 1939 - }, 1940 - }, { 1941 - .id = TEGRA194_MEMORY_CLIENT_PCIE5W, 1942 - .name = "pcie5w", 1943 - .sid = TEGRA194_SID_PCIE5, 1944 - .regs = { 1945 - .sid = { 1946 - .override = 0x718, 1947 - .security = 0x71c, 1948 - }, 1949 - }, 1950 - }, { 1951 - .id = TEGRA194_MEMORY_CLIENT_ISPFALW, 1952 - .name = "ispfalw", 1953 - .sid = TEGRA194_SID_ISP_FALCON, 1954 - .regs = { 1955 - .sid = { 1956 - .override = 0x720, 1957 - .security = 0x724, 1958 - }, 1959 - }, 1960 - }, { 1961 - .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1, 1962 - .name = "dla0rda1", 1963 - .sid = TEGRA194_SID_NVDLA0, 1964 - .regs = { 1965 - .sid = { 1966 - .override = 0x748, 1967 - .security = 0x74c, 1968 - }, 1969 - }, 1970 - }, { 1971 - .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1, 1972 - .name = "dla1rda1", 1973 - .sid = TEGRA194_SID_NVDLA1, 1974 - .regs = { 1975 - .sid = { 1976 - .override = 0x750, 1977 - .security = 0x754, 1978 - }, 1979 - }, 1980 - }, { 1981 - .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1, 1982 - .name = "pva0rda1", 1983 - .sid = TEGRA194_SID_PVA0, 1984 - .regs = { 1985 - .sid = { 1986 - .override = 0x758, 1987 - .security = 0x75c, 1988 - }, 1989 - }, 1990 - }, { 1991 - .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1, 1992 - .name = "pva0rdb1", 1993 - .sid = TEGRA194_SID_PVA0, 1994 - .regs = { 1995 - .sid = { 1996 - .override = 0x760, 1997 - .security = 0x764, 1998 - }, 1999 - }, 2000 - }, { 2001 - .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1, 2002 - .name = "pva1rda1", 2003 - .sid = TEGRA194_SID_PVA1, 2004 - .regs = { 2005 - .sid = { 2006 - .override = 0x768, 2007 - .security = 0x76c, 2008 - }, 2009 - }, 2010 - }, { 2011 - .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1, 2012 - .name = "pva1rdb1", 2013 - .sid = TEGRA194_SID_PVA1, 2014 - .regs = { 2015 - .sid = { 2016 - .override = 0x770, 2017 - .security = 0x774, 2018 - }, 2019 - }, 2020 - }, { 2021 - .id = TEGRA194_MEMORY_CLIENT_PCIE5R1, 2022 - .name = "pcie5r1", 2023 - .sid = TEGRA194_SID_PCIE5, 2024 - .regs = { 2025 - .sid = { 2026 - .override = 0x778, 2027 - .security = 0x77c, 2028 - }, 2029 - }, 2030 - }, { 2031 - .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1, 2032 - .name = "nvencsrd1", 2033 - .sid = TEGRA194_SID_NVENC, 2034 - .regs = { 2035 - .sid = { 2036 - .override = 0x780, 2037 - .security = 0x784, 2038 - }, 2039 - }, 2040 - }, { 2041 - .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1, 2042 - .name = "nvenc1srd1", 2043 - .sid = TEGRA194_SID_NVENC1, 2044 - .regs = { 2045 - .sid = { 2046 - .override = 0x788, 2047 - .security = 0x78c, 2048 - }, 2049 - }, 2050 - }, { 2051 - .id = TEGRA194_MEMORY_CLIENT_ISPRA1, 2052 - .name = "ispra1", 2053 - .sid = TEGRA194_SID_ISP, 2054 - .regs = { 2055 - .sid = { 2056 - .override = 0x790, 2057 - .security = 0x794, 2058 - }, 2059 - }, 2060 - }, { 2061 - .id = TEGRA194_MEMORY_CLIENT_PCIE0R1, 2062 - .name = "pcie0r1", 2063 - .sid = TEGRA194_SID_PCIE0, 2064 - .regs = { 2065 - .sid = { 2066 - .override = 0x798, 2067 - .security = 0x79c, 2068 - }, 2069 - }, 2070 - }, { 2071 - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD, 2072 - .name = "nvdec1srd", 2073 - .sid = TEGRA194_SID_NVDEC1, 2074 - .regs = { 2075 - .sid = { 2076 - .override = 0x7c8, 2077 - .security = 0x7cc, 2078 - }, 2079 - }, 2080 - }, { 2081 - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1, 2082 - .name = "nvdec1srd1", 2083 - .sid = TEGRA194_SID_NVDEC1, 2084 - .regs = { 2085 - .sid = { 2086 - .override = 0x7d0, 2087 - .security = 0x7d4, 2088 - }, 2089 - }, 2090 - }, { 2091 - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR, 2092 - .name = "nvdec1swr", 2093 - .sid = TEGRA194_SID_NVDEC1, 2094 - .regs = { 2095 - .sid = { 2096 - .override = 0x7d8, 2097 - .security = 0x7dc, 2098 - }, 2099 - }, 2100 - }, { 2101 - .id = TEGRA194_MEMORY_CLIENT_MIU5R, 2102 - .name = "miu5r", 2103 - .sid = TEGRA194_SID_MIU, 2104 - .regs = { 2105 - .sid = { 2106 - .override = 0x7e0, 2107 - .security = 0x7e4, 2108 - }, 2109 - }, 2110 - }, { 2111 - .id = TEGRA194_MEMORY_CLIENT_MIU5W, 2112 - .name = "miu5w", 2113 - .sid = TEGRA194_SID_MIU, 2114 - .regs = { 2115 - .sid = { 2116 - .override = 0x7e8, 2117 - .security = 0x7ec, 2118 - }, 2119 - }, 2120 - }, { 2121 - .id = TEGRA194_MEMORY_CLIENT_MIU6R, 2122 - .name = "miu6r", 2123 - .sid = TEGRA194_SID_MIU, 2124 - .regs = { 2125 - .sid = { 2126 - .override = 0x7f0, 2127 - .security = 0x7f4, 2128 - }, 2129 - }, 2130 - }, { 2131 - .id = TEGRA194_MEMORY_CLIENT_MIU6W, 2132 - .name = "miu6w", 2133 - .sid = TEGRA194_SID_MIU, 2134 - .regs = { 2135 - .sid = { 2136 - .override = 0x7f8, 2137 - .security = 0x7fc, 2138 - }, 2139 - }, 2140 - }, 2141 - }; 2142 - 2143 - const struct tegra_mc_soc tegra194_mc_soc = { 2144 - .num_clients = ARRAY_SIZE(tegra194_mc_clients), 2145 - .clients = tegra194_mc_clients, 2146 807 .num_address_bits = 40, 2147 808 .ops = &tegra186_mc_ops, 2148 809 };

+1351

drivers/memory/tegra/tegra194.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. 4 + */ 5 + 6 + #include <soc/tegra/mc.h> 7 + 8 + #include <dt-bindings/memory/tegra194-mc.h> 9 + 10 + #include "mc.h" 11 + 12 + static const struct tegra_mc_client tegra194_mc_clients[] = { 13 + { 14 + .id = TEGRA194_MEMORY_CLIENT_PTCR, 15 + .name = "ptcr", 16 + .sid = TEGRA194_SID_PASSTHROUGH, 17 + .regs = { 18 + .sid = { 19 + .override = 0x000, 20 + .security = 0x004, 21 + }, 22 + }, 23 + }, { 24 + .id = TEGRA194_MEMORY_CLIENT_MIU7R, 25 + .name = "miu7r", 26 + .sid = TEGRA194_SID_MIU, 27 + .regs = { 28 + .sid = { 29 + .override = 0x008, 30 + .security = 0x00c, 31 + }, 32 + }, 33 + }, { 34 + .id = TEGRA194_MEMORY_CLIENT_MIU7W, 35 + .name = "miu7w", 36 + .sid = TEGRA194_SID_MIU, 37 + .regs = { 38 + .sid = { 39 + .override = 0x010, 40 + .security = 0x014, 41 + }, 42 + }, 43 + }, { 44 + .id = TEGRA194_MEMORY_CLIENT_HDAR, 45 + .name = "hdar", 46 + .sid = TEGRA194_SID_HDA, 47 + .regs = { 48 + .sid = { 49 + .override = 0x0a8, 50 + .security = 0x0ac, 51 + }, 52 + }, 53 + }, { 54 + .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR, 55 + .name = "host1xdmar", 56 + .sid = TEGRA194_SID_HOST1X, 57 + .regs = { 58 + .sid = { 59 + .override = 0x0b0, 60 + .security = 0x0b4, 61 + }, 62 + }, 63 + }, { 64 + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD, 65 + .name = "nvencsrd", 66 + .sid = TEGRA194_SID_NVENC, 67 + .regs = { 68 + .sid = { 69 + .override = 0x0e0, 70 + .security = 0x0e4, 71 + }, 72 + }, 73 + }, { 74 + .id = TEGRA194_MEMORY_CLIENT_SATAR, 75 + .name = "satar", 76 + .sid = TEGRA194_SID_SATA, 77 + .regs = { 78 + .sid = { 79 + .override = 0x0f8, 80 + .security = 0x0fc, 81 + }, 82 + }, 83 + }, { 84 + .id = TEGRA194_MEMORY_CLIENT_MPCORER, 85 + .name = "mpcorer", 86 + .sid = TEGRA194_SID_PASSTHROUGH, 87 + .regs = { 88 + .sid = { 89 + .override = 0x138, 90 + .security = 0x13c, 91 + }, 92 + }, 93 + }, { 94 + .id = TEGRA194_MEMORY_CLIENT_NVENCSWR, 95 + .name = "nvencswr", 96 + .sid = TEGRA194_SID_NVENC, 97 + .regs = { 98 + .sid = { 99 + .override = 0x158, 100 + .security = 0x15c, 101 + }, 102 + }, 103 + }, { 104 + .id = TEGRA194_MEMORY_CLIENT_HDAW, 105 + .name = "hdaw", 106 + .sid = TEGRA194_SID_HDA, 107 + .regs = { 108 + .sid = { 109 + .override = 0x1a8, 110 + .security = 0x1ac, 111 + }, 112 + }, 113 + }, { 114 + .id = TEGRA194_MEMORY_CLIENT_MPCOREW, 115 + .name = "mpcorew", 116 + .sid = TEGRA194_SID_PASSTHROUGH, 117 + .regs = { 118 + .sid = { 119 + .override = 0x1c8, 120 + .security = 0x1cc, 121 + }, 122 + }, 123 + }, { 124 + .id = TEGRA194_MEMORY_CLIENT_SATAW, 125 + .name = "sataw", 126 + .sid = TEGRA194_SID_SATA, 127 + .regs = { 128 + .sid = { 129 + .override = 0x1e8, 130 + .security = 0x1ec, 131 + }, 132 + }, 133 + }, { 134 + .id = TEGRA194_MEMORY_CLIENT_ISPRA, 135 + .name = "ispra", 136 + .sid = TEGRA194_SID_ISP, 137 + .regs = { 138 + .sid = { 139 + .override = 0x220, 140 + .security = 0x224, 141 + }, 142 + }, 143 + }, { 144 + .id = TEGRA194_MEMORY_CLIENT_ISPFALR, 145 + .name = "ispfalr", 146 + .sid = TEGRA194_SID_ISP_FALCON, 147 + .regs = { 148 + .sid = { 149 + .override = 0x228, 150 + .security = 0x22c, 151 + }, 152 + }, 153 + }, { 154 + .id = TEGRA194_MEMORY_CLIENT_ISPWA, 155 + .name = "ispwa", 156 + .sid = TEGRA194_SID_ISP, 157 + .regs = { 158 + .sid = { 159 + .override = 0x230, 160 + .security = 0x234, 161 + }, 162 + }, 163 + }, { 164 + .id = TEGRA194_MEMORY_CLIENT_ISPWB, 165 + .name = "ispwb", 166 + .sid = TEGRA194_SID_ISP, 167 + .regs = { 168 + .sid = { 169 + .override = 0x238, 170 + .security = 0x23c, 171 + }, 172 + }, 173 + }, { 174 + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR, 175 + .name = "xusb_hostr", 176 + .sid = TEGRA194_SID_XUSB_HOST, 177 + .regs = { 178 + .sid = { 179 + .override = 0x250, 180 + .security = 0x254, 181 + }, 182 + }, 183 + }, { 184 + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW, 185 + .name = "xusb_hostw", 186 + .sid = TEGRA194_SID_XUSB_HOST, 187 + .regs = { 188 + .sid = { 189 + .override = 0x258, 190 + .security = 0x25c, 191 + }, 192 + }, 193 + }, { 194 + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR, 195 + .name = "xusb_devr", 196 + .sid = TEGRA194_SID_XUSB_DEV, 197 + .regs = { 198 + .sid = { 199 + .override = 0x260, 200 + .security = 0x264, 201 + }, 202 + }, 203 + }, { 204 + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW, 205 + .name = "xusb_devw", 206 + .sid = TEGRA194_SID_XUSB_DEV, 207 + .regs = { 208 + .sid = { 209 + .override = 0x268, 210 + .security = 0x26c, 211 + }, 212 + }, 213 + }, { 214 + .id = TEGRA194_MEMORY_CLIENT_SDMMCRA, 215 + .name = "sdmmcra", 216 + .sid = TEGRA194_SID_SDMMC1, 217 + .regs = { 218 + .sid = { 219 + .override = 0x300, 220 + .security = 0x304, 221 + }, 222 + }, 223 + }, { 224 + .id = TEGRA194_MEMORY_CLIENT_SDMMCR, 225 + .name = "sdmmcr", 226 + .sid = TEGRA194_SID_SDMMC3, 227 + .regs = { 228 + .sid = { 229 + .override = 0x310, 230 + .security = 0x314, 231 + }, 232 + }, 233 + }, { 234 + .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB, 235 + .name = "sdmmcrab", 236 + .sid = TEGRA194_SID_SDMMC4, 237 + .regs = { 238 + .sid = { 239 + .override = 0x318, 240 + .security = 0x31c, 241 + }, 242 + }, 243 + }, { 244 + .id = TEGRA194_MEMORY_CLIENT_SDMMCWA, 245 + .name = "sdmmcwa", 246 + .sid = TEGRA194_SID_SDMMC1, 247 + .regs = { 248 + .sid = { 249 + .override = 0x320, 250 + .security = 0x324, 251 + }, 252 + }, 253 + }, { 254 + .id = TEGRA194_MEMORY_CLIENT_SDMMCW, 255 + .name = "sdmmcw", 256 + .sid = TEGRA194_SID_SDMMC3, 257 + .regs = { 258 + .sid = { 259 + .override = 0x330, 260 + .security = 0x334, 261 + }, 262 + }, 263 + }, { 264 + .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB, 265 + .name = "sdmmcwab", 266 + .sid = TEGRA194_SID_SDMMC4, 267 + .regs = { 268 + .sid = { 269 + .override = 0x338, 270 + .security = 0x33c, 271 + }, 272 + }, 273 + }, { 274 + .id = TEGRA194_MEMORY_CLIENT_VICSRD, 275 + .name = "vicsrd", 276 + .sid = TEGRA194_SID_VIC, 277 + .regs = { 278 + .sid = { 279 + .override = 0x360, 280 + .security = 0x364, 281 + }, 282 + }, 283 + }, { 284 + .id = TEGRA194_MEMORY_CLIENT_VICSWR, 285 + .name = "vicswr", 286 + .sid = TEGRA194_SID_VIC, 287 + .regs = { 288 + .sid = { 289 + .override = 0x368, 290 + .security = 0x36c, 291 + }, 292 + }, 293 + }, { 294 + .id = TEGRA194_MEMORY_CLIENT_VIW, 295 + .name = "viw", 296 + .sid = TEGRA194_SID_VI, 297 + .regs = { 298 + .sid = { 299 + .override = 0x390, 300 + .security = 0x394, 301 + }, 302 + }, 303 + }, { 304 + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD, 305 + .name = "nvdecsrd", 306 + .sid = TEGRA194_SID_NVDEC, 307 + .regs = { 308 + .sid = { 309 + .override = 0x3c0, 310 + .security = 0x3c4, 311 + }, 312 + }, 313 + }, { 314 + .id = TEGRA194_MEMORY_CLIENT_NVDECSWR, 315 + .name = "nvdecswr", 316 + .sid = TEGRA194_SID_NVDEC, 317 + .regs = { 318 + .sid = { 319 + .override = 0x3c8, 320 + .security = 0x3cc, 321 + }, 322 + }, 323 + }, { 324 + .id = TEGRA194_MEMORY_CLIENT_APER, 325 + .name = "aper", 326 + .sid = TEGRA194_SID_APE, 327 + .regs = { 328 + .sid = { 329 + .override = 0x3c0, 330 + .security = 0x3c4, 331 + }, 332 + }, 333 + }, { 334 + .id = TEGRA194_MEMORY_CLIENT_APEW, 335 + .name = "apew", 336 + .sid = TEGRA194_SID_APE, 337 + .regs = { 338 + .sid = { 339 + .override = 0x3d0, 340 + .security = 0x3d4, 341 + }, 342 + }, 343 + }, { 344 + .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD, 345 + .name = "nvjpgsrd", 346 + .sid = TEGRA194_SID_NVJPG, 347 + .regs = { 348 + .sid = { 349 + .override = 0x3f0, 350 + .security = 0x3f4, 351 + }, 352 + }, 353 + }, { 354 + .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR, 355 + .name = "nvjpgswr", 356 + .sid = TEGRA194_SID_NVJPG, 357 + .regs = { 358 + .sid = { 359 + .override = 0x3f0, 360 + .security = 0x3f4, 361 + }, 362 + }, 363 + }, { 364 + .name = "axiapr", 365 + .id = TEGRA194_MEMORY_CLIENT_AXIAPR, 366 + .sid = TEGRA194_SID_PASSTHROUGH, 367 + .regs = { 368 + .sid = { 369 + .override = 0x410, 370 + .security = 0x414, 371 + }, 372 + }, 373 + }, { 374 + .id = TEGRA194_MEMORY_CLIENT_AXIAPW, 375 + .name = "axiapw", 376 + .sid = TEGRA194_SID_PASSTHROUGH, 377 + .regs = { 378 + .sid = { 379 + .override = 0x418, 380 + .security = 0x41c, 381 + }, 382 + }, 383 + }, { 384 + .id = TEGRA194_MEMORY_CLIENT_ETRR, 385 + .name = "etrr", 386 + .sid = TEGRA194_SID_ETR, 387 + .regs = { 388 + .sid = { 389 + .override = 0x420, 390 + .security = 0x424, 391 + }, 392 + }, 393 + }, { 394 + .id = TEGRA194_MEMORY_CLIENT_ETRW, 395 + .name = "etrw", 396 + .sid = TEGRA194_SID_ETR, 397 + .regs = { 398 + .sid = { 399 + .override = 0x428, 400 + .security = 0x42c, 401 + }, 402 + }, 403 + }, { 404 + .id = TEGRA194_MEMORY_CLIENT_AXISR, 405 + .name = "axisr", 406 + .sid = TEGRA194_SID_PASSTHROUGH, 407 + .regs = { 408 + .sid = { 409 + .override = 0x460, 410 + .security = 0x464, 411 + }, 412 + }, 413 + }, { 414 + .id = TEGRA194_MEMORY_CLIENT_AXISW, 415 + .name = "axisw", 416 + .sid = TEGRA194_SID_PASSTHROUGH, 417 + .regs = { 418 + .sid = { 419 + .override = 0x468, 420 + .security = 0x46c, 421 + }, 422 + }, 423 + }, { 424 + .id = TEGRA194_MEMORY_CLIENT_EQOSR, 425 + .name = "eqosr", 426 + .sid = TEGRA194_SID_EQOS, 427 + .regs = { 428 + .sid = { 429 + .override = 0x470, 430 + .security = 0x474, 431 + }, 432 + }, 433 + }, { 434 + .name = "eqosw", 435 + .id = TEGRA194_MEMORY_CLIENT_EQOSW, 436 + .sid = TEGRA194_SID_EQOS, 437 + .regs = { 438 + .sid = { 439 + .override = 0x478, 440 + .security = 0x47c, 441 + }, 442 + }, 443 + }, { 444 + .id = TEGRA194_MEMORY_CLIENT_UFSHCR, 445 + .name = "ufshcr", 446 + .sid = TEGRA194_SID_UFSHC, 447 + .regs = { 448 + .sid = { 449 + .override = 0x480, 450 + .security = 0x484, 451 + }, 452 + }, 453 + }, { 454 + .id = TEGRA194_MEMORY_CLIENT_UFSHCW, 455 + .name = "ufshcw", 456 + .sid = TEGRA194_SID_UFSHC, 457 + .regs = { 458 + .sid = { 459 + .override = 0x488, 460 + .security = 0x48c, 461 + }, 462 + }, 463 + }, { 464 + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR, 465 + .name = "nvdisplayr", 466 + .sid = TEGRA194_SID_NVDISPLAY, 467 + .regs = { 468 + .sid = { 469 + .override = 0x490, 470 + .security = 0x494, 471 + }, 472 + }, 473 + }, { 474 + .id = TEGRA194_MEMORY_CLIENT_BPMPR, 475 + .name = "bpmpr", 476 + .sid = TEGRA194_SID_BPMP, 477 + .regs = { 478 + .sid = { 479 + .override = 0x498, 480 + .security = 0x49c, 481 + }, 482 + }, 483 + }, { 484 + .id = TEGRA194_MEMORY_CLIENT_BPMPW, 485 + .name = "bpmpw", 486 + .sid = TEGRA194_SID_BPMP, 487 + .regs = { 488 + .sid = { 489 + .override = 0x4a0, 490 + .security = 0x4a4, 491 + }, 492 + }, 493 + }, { 494 + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR, 495 + .name = "bpmpdmar", 496 + .sid = TEGRA194_SID_BPMP, 497 + .regs = { 498 + .sid = { 499 + .override = 0x4a8, 500 + .security = 0x4ac, 501 + }, 502 + }, 503 + }, { 504 + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW, 505 + .name = "bpmpdmaw", 506 + .sid = TEGRA194_SID_BPMP, 507 + .regs = { 508 + .sid = { 509 + .override = 0x4b0, 510 + .security = 0x4b4, 511 + }, 512 + }, 513 + }, { 514 + .id = TEGRA194_MEMORY_CLIENT_AONR, 515 + .name = "aonr", 516 + .sid = TEGRA194_SID_AON, 517 + .regs = { 518 + .sid = { 519 + .override = 0x4b8, 520 + .security = 0x4bc, 521 + }, 522 + }, 523 + }, { 524 + .id = TEGRA194_MEMORY_CLIENT_AONW, 525 + .name = "aonw", 526 + .sid = TEGRA194_SID_AON, 527 + .regs = { 528 + .sid = { 529 + .override = 0x4c0, 530 + .security = 0x4c4, 531 + }, 532 + }, 533 + }, { 534 + .id = TEGRA194_MEMORY_CLIENT_AONDMAR, 535 + .name = "aondmar", 536 + .sid = TEGRA194_SID_AON, 537 + .regs = { 538 + .sid = { 539 + .override = 0x4c8, 540 + .security = 0x4cc, 541 + }, 542 + }, 543 + }, { 544 + .id = TEGRA194_MEMORY_CLIENT_AONDMAW, 545 + .name = "aondmaw", 546 + .sid = TEGRA194_SID_AON, 547 + .regs = { 548 + .sid = { 549 + .override = 0x4d0, 550 + .security = 0x4d4, 551 + }, 552 + }, 553 + }, { 554 + .id = TEGRA194_MEMORY_CLIENT_SCER, 555 + .name = "scer", 556 + .sid = TEGRA194_SID_SCE, 557 + .regs = { 558 + .sid = { 559 + .override = 0x4d8, 560 + .security = 0x4dc, 561 + }, 562 + }, 563 + }, { 564 + .id = TEGRA194_MEMORY_CLIENT_SCEW, 565 + .name = "scew", 566 + .sid = TEGRA194_SID_SCE, 567 + .regs = { 568 + .sid = { 569 + .override = 0x4e0, 570 + .security = 0x4e4, 571 + }, 572 + }, 573 + }, { 574 + .id = TEGRA194_MEMORY_CLIENT_SCEDMAR, 575 + .name = "scedmar", 576 + .sid = TEGRA194_SID_SCE, 577 + .regs = { 578 + .sid = { 579 + .override = 0x4e8, 580 + .security = 0x4ec, 581 + }, 582 + }, 583 + }, { 584 + .id = TEGRA194_MEMORY_CLIENT_SCEDMAW, 585 + .name = "scedmaw", 586 + .sid = TEGRA194_SID_SCE, 587 + .regs = { 588 + .sid = { 589 + .override = 0x4f0, 590 + .security = 0x4f4, 591 + }, 592 + }, 593 + }, { 594 + .id = TEGRA194_MEMORY_CLIENT_APEDMAR, 595 + .name = "apedmar", 596 + .sid = TEGRA194_SID_APE, 597 + .regs = { 598 + .sid = { 599 + .override = 0x4f8, 600 + .security = 0x4fc, 601 + }, 602 + }, 603 + }, { 604 + .id = TEGRA194_MEMORY_CLIENT_APEDMAW, 605 + .name = "apedmaw", 606 + .sid = TEGRA194_SID_APE, 607 + .regs = { 608 + .sid = { 609 + .override = 0x500, 610 + .security = 0x504, 611 + }, 612 + }, 613 + }, { 614 + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1, 615 + .name = "nvdisplayr1", 616 + .sid = TEGRA194_SID_NVDISPLAY, 617 + .regs = { 618 + .sid = { 619 + .override = 0x508, 620 + .security = 0x50c, 621 + }, 622 + }, 623 + }, { 624 + .id = TEGRA194_MEMORY_CLIENT_VICSRD1, 625 + .name = "vicsrd1", 626 + .sid = TEGRA194_SID_VIC, 627 + .regs = { 628 + .sid = { 629 + .override = 0x510, 630 + .security = 0x514, 631 + }, 632 + }, 633 + }, { 634 + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1, 635 + .name = "nvdecsrd1", 636 + .sid = TEGRA194_SID_NVDEC, 637 + .regs = { 638 + .sid = { 639 + .override = 0x518, 640 + .security = 0x51c, 641 + }, 642 + }, 643 + }, { 644 + .id = TEGRA194_MEMORY_CLIENT_MIU0R, 645 + .name = "miu0r", 646 + .sid = TEGRA194_SID_MIU, 647 + .regs = { 648 + .sid = { 649 + .override = 0x530, 650 + .security = 0x534, 651 + }, 652 + }, 653 + }, { 654 + .name = "miu0w", 655 + .id = TEGRA194_MEMORY_CLIENT_MIU0W, 656 + .sid = TEGRA194_SID_MIU, 657 + .regs = { 658 + .sid = { 659 + .override = 0x538, 660 + .security = 0x53c, 661 + }, 662 + }, 663 + }, { 664 + .id = TEGRA194_MEMORY_CLIENT_MIU1R, 665 + .name = "miu1r", 666 + .sid = TEGRA194_SID_MIU, 667 + .regs = { 668 + .sid = { 669 + .override = 0x540, 670 + .security = 0x544, 671 + }, 672 + }, 673 + }, { 674 + .id = TEGRA194_MEMORY_CLIENT_MIU1W, 675 + .name = "miu1w", 676 + .sid = TEGRA194_SID_MIU, 677 + .regs = { 678 + .sid = { 679 + .override = 0x548, 680 + .security = 0x54c, 681 + }, 682 + }, 683 + }, { 684 + .id = TEGRA194_MEMORY_CLIENT_MIU2R, 685 + .name = "miu2r", 686 + .sid = TEGRA194_SID_MIU, 687 + .regs = { 688 + .sid = { 689 + .override = 0x570, 690 + .security = 0x574, 691 + }, 692 + }, 693 + }, { 694 + .id = TEGRA194_MEMORY_CLIENT_MIU2W, 695 + .name = "miu2w", 696 + .sid = TEGRA194_SID_MIU, 697 + .regs = { 698 + .sid = { 699 + .override = 0x578, 700 + .security = 0x57c, 701 + }, 702 + }, 703 + }, { 704 + .id = TEGRA194_MEMORY_CLIENT_MIU3R, 705 + .name = "miu3r", 706 + .sid = TEGRA194_SID_MIU, 707 + .regs = { 708 + .sid = { 709 + .override = 0x580, 710 + .security = 0x584, 711 + }, 712 + }, 713 + }, { 714 + .id = TEGRA194_MEMORY_CLIENT_MIU3W, 715 + .name = "miu3w", 716 + .sid = TEGRA194_SID_MIU, 717 + .regs = { 718 + .sid = { 719 + .override = 0x588, 720 + .security = 0x58c, 721 + }, 722 + }, 723 + }, { 724 + .id = TEGRA194_MEMORY_CLIENT_MIU4R, 725 + .name = "miu4r", 726 + .sid = TEGRA194_SID_MIU, 727 + .regs = { 728 + .sid = { 729 + .override = 0x590, 730 + .security = 0x594, 731 + }, 732 + }, 733 + }, { 734 + .id = TEGRA194_MEMORY_CLIENT_MIU4W, 735 + .name = "miu4w", 736 + .sid = TEGRA194_SID_MIU, 737 + .regs = { 738 + .sid = { 739 + .override = 0x598, 740 + .security = 0x59c, 741 + }, 742 + }, 743 + }, { 744 + .id = TEGRA194_MEMORY_CLIENT_DPMUR, 745 + .name = "dpmur", 746 + .sid = TEGRA194_SID_PASSTHROUGH, 747 + .regs = { 748 + .sid = { 749 + .override = 0x598, 750 + .security = 0x59c, 751 + }, 752 + }, 753 + }, { 754 + .id = TEGRA194_MEMORY_CLIENT_VIFALR, 755 + .name = "vifalr", 756 + .sid = TEGRA194_SID_VI_FALCON, 757 + .regs = { 758 + .sid = { 759 + .override = 0x5e0, 760 + .security = 0x5e4, 761 + }, 762 + }, 763 + }, { 764 + .id = TEGRA194_MEMORY_CLIENT_VIFALW, 765 + .name = "vifalw", 766 + .sid = TEGRA194_SID_VI_FALCON, 767 + .regs = { 768 + .sid = { 769 + .override = 0x5e8, 770 + .security = 0x5ec, 771 + }, 772 + }, 773 + }, { 774 + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA, 775 + .name = "dla0rda", 776 + .sid = TEGRA194_SID_NVDLA0, 777 + .regs = { 778 + .sid = { 779 + .override = 0x5f0, 780 + .security = 0x5f4, 781 + }, 782 + }, 783 + }, { 784 + .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB, 785 + .name = "dla0falrdb", 786 + .sid = TEGRA194_SID_NVDLA0, 787 + .regs = { 788 + .sid = { 789 + .override = 0x5f8, 790 + .security = 0x5fc, 791 + }, 792 + }, 793 + }, { 794 + .id = TEGRA194_MEMORY_CLIENT_DLA0WRA, 795 + .name = "dla0wra", 796 + .sid = TEGRA194_SID_NVDLA0, 797 + .regs = { 798 + .sid = { 799 + .override = 0x600, 800 + .security = 0x604, 801 + }, 802 + }, 803 + }, { 804 + .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB, 805 + .name = "dla0falwrb", 806 + .sid = TEGRA194_SID_NVDLA0, 807 + .regs = { 808 + .sid = { 809 + .override = 0x608, 810 + .security = 0x60c, 811 + }, 812 + }, 813 + }, { 814 + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA, 815 + .name = "dla1rda", 816 + .sid = TEGRA194_SID_NVDLA1, 817 + .regs = { 818 + .sid = { 819 + .override = 0x610, 820 + .security = 0x614, 821 + }, 822 + }, 823 + }, { 824 + .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB, 825 + .name = "dla1falrdb", 826 + .sid = TEGRA194_SID_NVDLA1, 827 + .regs = { 828 + .sid = { 829 + .override = 0x618, 830 + .security = 0x61c, 831 + }, 832 + }, 833 + }, { 834 + .id = TEGRA194_MEMORY_CLIENT_DLA1WRA, 835 + .name = "dla1wra", 836 + .sid = TEGRA194_SID_NVDLA1, 837 + .regs = { 838 + .sid = { 839 + .override = 0x620, 840 + .security = 0x624, 841 + }, 842 + }, 843 + }, { 844 + .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB, 845 + .name = "dla1falwrb", 846 + .sid = TEGRA194_SID_NVDLA1, 847 + .regs = { 848 + .sid = { 849 + .override = 0x628, 850 + .security = 0x62c, 851 + }, 852 + }, 853 + }, { 854 + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA, 855 + .name = "pva0rda", 856 + .sid = TEGRA194_SID_PVA0, 857 + .regs = { 858 + .sid = { 859 + .override = 0x630, 860 + .security = 0x634, 861 + }, 862 + }, 863 + }, { 864 + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB, 865 + .name = "pva0rdb", 866 + .sid = TEGRA194_SID_PVA0, 867 + .regs = { 868 + .sid = { 869 + .override = 0x638, 870 + .security = 0x63c, 871 + }, 872 + }, 873 + }, { 874 + .id = TEGRA194_MEMORY_CLIENT_PVA0RDC, 875 + .name = "pva0rdc", 876 + .sid = TEGRA194_SID_PVA0, 877 + .regs = { 878 + .sid = { 879 + .override = 0x640, 880 + .security = 0x644, 881 + }, 882 + }, 883 + }, { 884 + .id = TEGRA194_MEMORY_CLIENT_PVA0WRA, 885 + .name = "pva0wra", 886 + .sid = TEGRA194_SID_PVA0, 887 + .regs = { 888 + .sid = { 889 + .override = 0x648, 890 + .security = 0x64c, 891 + }, 892 + }, 893 + }, { 894 + .id = TEGRA194_MEMORY_CLIENT_PVA0WRB, 895 + .name = "pva0wrb", 896 + .sid = TEGRA194_SID_PVA0, 897 + .regs = { 898 + .sid = { 899 + .override = 0x650, 900 + .security = 0x654, 901 + }, 902 + }, 903 + }, { 904 + .id = TEGRA194_MEMORY_CLIENT_PVA0WRC, 905 + .name = "pva0wrc", 906 + .sid = TEGRA194_SID_PVA0, 907 + .regs = { 908 + .sid = { 909 + .override = 0x658, 910 + .security = 0x65c, 911 + }, 912 + }, 913 + }, { 914 + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA, 915 + .name = "pva1rda", 916 + .sid = TEGRA194_SID_PVA1, 917 + .regs = { 918 + .sid = { 919 + .override = 0x660, 920 + .security = 0x664, 921 + }, 922 + }, 923 + }, { 924 + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB, 925 + .name = "pva1rdb", 926 + .sid = TEGRA194_SID_PVA1, 927 + .regs = { 928 + .sid = { 929 + .override = 0x668, 930 + .security = 0x66c, 931 + }, 932 + }, 933 + }, { 934 + .id = TEGRA194_MEMORY_CLIENT_PVA1RDC, 935 + .name = "pva1rdc", 936 + .sid = TEGRA194_SID_PVA1, 937 + .regs = { 938 + .sid = { 939 + .override = 0x670, 940 + .security = 0x674, 941 + }, 942 + }, 943 + }, { 944 + .id = TEGRA194_MEMORY_CLIENT_PVA1WRA, 945 + .name = "pva1wra", 946 + .sid = TEGRA194_SID_PVA1, 947 + .regs = { 948 + .sid = { 949 + .override = 0x678, 950 + .security = 0x67c, 951 + }, 952 + }, 953 + }, { 954 + .id = TEGRA194_MEMORY_CLIENT_PVA1WRB, 955 + .name = "pva1wrb", 956 + .sid = TEGRA194_SID_PVA1, 957 + .regs = { 958 + .sid = { 959 + .override = 0x680, 960 + .security = 0x684, 961 + }, 962 + }, 963 + }, { 964 + .id = TEGRA194_MEMORY_CLIENT_PVA1WRC, 965 + .name = "pva1wrc", 966 + .sid = TEGRA194_SID_PVA1, 967 + .regs = { 968 + .sid = { 969 + .override = 0x688, 970 + .security = 0x68c, 971 + }, 972 + }, 973 + }, { 974 + .id = TEGRA194_MEMORY_CLIENT_RCER, 975 + .name = "rcer", 976 + .sid = TEGRA194_SID_RCE, 977 + .regs = { 978 + .sid = { 979 + .override = 0x690, 980 + .security = 0x694, 981 + }, 982 + }, 983 + }, { 984 + .id = TEGRA194_MEMORY_CLIENT_RCEW, 985 + .name = "rcew", 986 + .sid = TEGRA194_SID_RCE, 987 + .regs = { 988 + .sid = { 989 + .override = 0x698, 990 + .security = 0x69c, 991 + }, 992 + }, 993 + }, { 994 + .id = TEGRA194_MEMORY_CLIENT_RCEDMAR, 995 + .name = "rcedmar", 996 + .sid = TEGRA194_SID_RCE, 997 + .regs = { 998 + .sid = { 999 + .override = 0x6a0, 1000 + .security = 0x6a4, 1001 + }, 1002 + }, 1003 + }, { 1004 + .id = TEGRA194_MEMORY_CLIENT_RCEDMAW, 1005 + .name = "rcedmaw", 1006 + .sid = TEGRA194_SID_RCE, 1007 + .regs = { 1008 + .sid = { 1009 + .override = 0x6a8, 1010 + .security = 0x6ac, 1011 + }, 1012 + }, 1013 + }, { 1014 + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD, 1015 + .name = "nvenc1srd", 1016 + .sid = TEGRA194_SID_NVENC1, 1017 + .regs = { 1018 + .sid = { 1019 + .override = 0x6b0, 1020 + .security = 0x6b4, 1021 + }, 1022 + }, 1023 + }, { 1024 + .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR, 1025 + .name = "nvenc1swr", 1026 + .sid = TEGRA194_SID_NVENC1, 1027 + .regs = { 1028 + .sid = { 1029 + .override = 0x6b8, 1030 + .security = 0x6bc, 1031 + }, 1032 + }, 1033 + }, { 1034 + .id = TEGRA194_MEMORY_CLIENT_PCIE0R, 1035 + .name = "pcie0r", 1036 + .sid = TEGRA194_SID_PCIE0, 1037 + .regs = { 1038 + .sid = { 1039 + .override = 0x6c0, 1040 + .security = 0x6c4, 1041 + }, 1042 + }, 1043 + }, { 1044 + .id = TEGRA194_MEMORY_CLIENT_PCIE0W, 1045 + .name = "pcie0w", 1046 + .sid = TEGRA194_SID_PCIE0, 1047 + .regs = { 1048 + .sid = { 1049 + .override = 0x6c8, 1050 + .security = 0x6cc, 1051 + }, 1052 + }, 1053 + }, { 1054 + .id = TEGRA194_MEMORY_CLIENT_PCIE1R, 1055 + .name = "pcie1r", 1056 + .sid = TEGRA194_SID_PCIE1, 1057 + .regs = { 1058 + .sid = { 1059 + .override = 0x6d0, 1060 + .security = 0x6d4, 1061 + }, 1062 + }, 1063 + }, { 1064 + .id = TEGRA194_MEMORY_CLIENT_PCIE1W, 1065 + .name = "pcie1w", 1066 + .sid = TEGRA194_SID_PCIE1, 1067 + .regs = { 1068 + .sid = { 1069 + .override = 0x6d8, 1070 + .security = 0x6dc, 1071 + }, 1072 + }, 1073 + }, { 1074 + .id = TEGRA194_MEMORY_CLIENT_PCIE2AR, 1075 + .name = "pcie2ar", 1076 + .sid = TEGRA194_SID_PCIE2, 1077 + .regs = { 1078 + .sid = { 1079 + .override = 0x6e0, 1080 + .security = 0x6e4, 1081 + }, 1082 + }, 1083 + }, { 1084 + .id = TEGRA194_MEMORY_CLIENT_PCIE2AW, 1085 + .name = "pcie2aw", 1086 + .sid = TEGRA194_SID_PCIE2, 1087 + .regs = { 1088 + .sid = { 1089 + .override = 0x6e8, 1090 + .security = 0x6ec, 1091 + }, 1092 + }, 1093 + }, { 1094 + .id = TEGRA194_MEMORY_CLIENT_PCIE3R, 1095 + .name = "pcie3r", 1096 + .sid = TEGRA194_SID_PCIE3, 1097 + .regs = { 1098 + .sid = { 1099 + .override = 0x6f0, 1100 + .security = 0x6f4, 1101 + }, 1102 + }, 1103 + }, { 1104 + .id = TEGRA194_MEMORY_CLIENT_PCIE3W, 1105 + .name = "pcie3w", 1106 + .sid = TEGRA194_SID_PCIE3, 1107 + .regs = { 1108 + .sid = { 1109 + .override = 0x6f8, 1110 + .security = 0x6fc, 1111 + }, 1112 + }, 1113 + }, { 1114 + .id = TEGRA194_MEMORY_CLIENT_PCIE4R, 1115 + .name = "pcie4r", 1116 + .sid = TEGRA194_SID_PCIE4, 1117 + .regs = { 1118 + .sid = { 1119 + .override = 0x700, 1120 + .security = 0x704, 1121 + }, 1122 + }, 1123 + }, { 1124 + .id = TEGRA194_MEMORY_CLIENT_PCIE4W, 1125 + .name = "pcie4w", 1126 + .sid = TEGRA194_SID_PCIE4, 1127 + .regs = { 1128 + .sid = { 1129 + .override = 0x708, 1130 + .security = 0x70c, 1131 + }, 1132 + }, 1133 + }, { 1134 + .id = TEGRA194_MEMORY_CLIENT_PCIE5R, 1135 + .name = "pcie5r", 1136 + .sid = TEGRA194_SID_PCIE5, 1137 + .regs = { 1138 + .sid = { 1139 + .override = 0x710, 1140 + .security = 0x714, 1141 + }, 1142 + }, 1143 + }, { 1144 + .id = TEGRA194_MEMORY_CLIENT_PCIE5W, 1145 + .name = "pcie5w", 1146 + .sid = TEGRA194_SID_PCIE5, 1147 + .regs = { 1148 + .sid = { 1149 + .override = 0x718, 1150 + .security = 0x71c, 1151 + }, 1152 + }, 1153 + }, { 1154 + .id = TEGRA194_MEMORY_CLIENT_ISPFALW, 1155 + .name = "ispfalw", 1156 + .sid = TEGRA194_SID_ISP_FALCON, 1157 + .regs = { 1158 + .sid = { 1159 + .override = 0x720, 1160 + .security = 0x724, 1161 + }, 1162 + }, 1163 + }, { 1164 + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1, 1165 + .name = "dla0rda1", 1166 + .sid = TEGRA194_SID_NVDLA0, 1167 + .regs = { 1168 + .sid = { 1169 + .override = 0x748, 1170 + .security = 0x74c, 1171 + }, 1172 + }, 1173 + }, { 1174 + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1, 1175 + .name = "dla1rda1", 1176 + .sid = TEGRA194_SID_NVDLA1, 1177 + .regs = { 1178 + .sid = { 1179 + .override = 0x750, 1180 + .security = 0x754, 1181 + }, 1182 + }, 1183 + }, { 1184 + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1, 1185 + .name = "pva0rda1", 1186 + .sid = TEGRA194_SID_PVA0, 1187 + .regs = { 1188 + .sid = { 1189 + .override = 0x758, 1190 + .security = 0x75c, 1191 + }, 1192 + }, 1193 + }, { 1194 + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1, 1195 + .name = "pva0rdb1", 1196 + .sid = TEGRA194_SID_PVA0, 1197 + .regs = { 1198 + .sid = { 1199 + .override = 0x760, 1200 + .security = 0x764, 1201 + }, 1202 + }, 1203 + }, { 1204 + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1, 1205 + .name = "pva1rda1", 1206 + .sid = TEGRA194_SID_PVA1, 1207 + .regs = { 1208 + .sid = { 1209 + .override = 0x768, 1210 + .security = 0x76c, 1211 + }, 1212 + }, 1213 + }, { 1214 + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1, 1215 + .name = "pva1rdb1", 1216 + .sid = TEGRA194_SID_PVA1, 1217 + .regs = { 1218 + .sid = { 1219 + .override = 0x770, 1220 + .security = 0x774, 1221 + }, 1222 + }, 1223 + }, { 1224 + .id = TEGRA194_MEMORY_CLIENT_PCIE5R1, 1225 + .name = "pcie5r1", 1226 + .sid = TEGRA194_SID_PCIE5, 1227 + .regs = { 1228 + .sid = { 1229 + .override = 0x778, 1230 + .security = 0x77c, 1231 + }, 1232 + }, 1233 + }, { 1234 + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1, 1235 + .name = "nvencsrd1", 1236 + .sid = TEGRA194_SID_NVENC, 1237 + .regs = { 1238 + .sid = { 1239 + .override = 0x780, 1240 + .security = 0x784, 1241 + }, 1242 + }, 1243 + }, { 1244 + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1, 1245 + .name = "nvenc1srd1", 1246 + .sid = TEGRA194_SID_NVENC1, 1247 + .regs = { 1248 + .sid = { 1249 + .override = 0x788, 1250 + .security = 0x78c, 1251 + }, 1252 + }, 1253 + }, { 1254 + .id = TEGRA194_MEMORY_CLIENT_ISPRA1, 1255 + .name = "ispra1", 1256 + .sid = TEGRA194_SID_ISP, 1257 + .regs = { 1258 + .sid = { 1259 + .override = 0x790, 1260 + .security = 0x794, 1261 + }, 1262 + }, 1263 + }, { 1264 + .id = TEGRA194_MEMORY_CLIENT_PCIE0R1, 1265 + .name = "pcie0r1", 1266 + .sid = TEGRA194_SID_PCIE0, 1267 + .regs = { 1268 + .sid = { 1269 + .override = 0x798, 1270 + .security = 0x79c, 1271 + }, 1272 + }, 1273 + }, { 1274 + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD, 1275 + .name = "nvdec1srd", 1276 + .sid = TEGRA194_SID_NVDEC1, 1277 + .regs = { 1278 + .sid = { 1279 + .override = 0x7c8, 1280 + .security = 0x7cc, 1281 + }, 1282 + }, 1283 + }, { 1284 + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1, 1285 + .name = "nvdec1srd1", 1286 + .sid = TEGRA194_SID_NVDEC1, 1287 + .regs = { 1288 + .sid = { 1289 + .override = 0x7d0, 1290 + .security = 0x7d4, 1291 + }, 1292 + }, 1293 + }, { 1294 + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR, 1295 + .name = "nvdec1swr", 1296 + .sid = TEGRA194_SID_NVDEC1, 1297 + .regs = { 1298 + .sid = { 1299 + .override = 0x7d8, 1300 + .security = 0x7dc, 1301 + }, 1302 + }, 1303 + }, { 1304 + .id = TEGRA194_MEMORY_CLIENT_MIU5R, 1305 + .name = "miu5r", 1306 + .sid = TEGRA194_SID_MIU, 1307 + .regs = { 1308 + .sid = { 1309 + .override = 0x7e0, 1310 + .security = 0x7e4, 1311 + }, 1312 + }, 1313 + }, { 1314 + .id = TEGRA194_MEMORY_CLIENT_MIU5W, 1315 + .name = "miu5w", 1316 + .sid = TEGRA194_SID_MIU, 1317 + .regs = { 1318 + .sid = { 1319 + .override = 0x7e8, 1320 + .security = 0x7ec, 1321 + }, 1322 + }, 1323 + }, { 1324 + .id = TEGRA194_MEMORY_CLIENT_MIU6R, 1325 + .name = "miu6r", 1326 + .sid = TEGRA194_SID_MIU, 1327 + .regs = { 1328 + .sid = { 1329 + .override = 0x7f0, 1330 + .security = 0x7f4, 1331 + }, 1332 + }, 1333 + }, { 1334 + .id = TEGRA194_MEMORY_CLIENT_MIU6W, 1335 + .name = "miu6w", 1336 + .sid = TEGRA194_SID_MIU, 1337 + .regs = { 1338 + .sid = { 1339 + .override = 0x7f8, 1340 + .security = 0x7fc, 1341 + }, 1342 + }, 1343 + }, 1344 + }; 1345 + 1346 + const struct tegra_mc_soc tegra194_mc_soc = { 1347 + .num_clients = ARRAY_SIZE(tegra194_mc_clients), 1348 + .clients = tegra194_mc_clients, 1349 + .num_address_bits = 40, 1350 + .ops = &tegra186_mc_ops, 1351 + };