[MIPS] SB1250: Fix bugs/warnings by creative use of volatile.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

+18 -17
+1 -2
arch/mips/mm/pg-sb1.c
··· 218 218 for (i = 0; i < DM_NUM_CHANNELS; i++) { 219 219 const u64 base_val = CPHYSADDR(&page_descr[i]) | 220 220 V_DM_DSCR_BASE_RINGSZ(1); 221 - volatile void *base_reg = 222 - IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); 221 + void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); 223 222 224 223 __raw_writeq(base_val, base_reg); 225 224 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
+1 -1
arch/mips/pci/pci-bcm1480.c
··· 216 216 /* 217 217 * See if the PCI bus has been configured by the firmware. 218 218 */ 219 - reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG)); 219 + reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); 220 220 if (!(reg & M_BCM1480_SYS_PCI_HOST)) { 221 221 bcm1480_bus_status |= PCI_DEVICE_MODE; 222 222 } else {
+1 -1
arch/mips/pci/pci-sb1250.c
··· 228 228 /* 229 229 * See if the PCI bus has been configured by the firmware. 230 230 */ 231 - reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG)); 231 + reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); 232 232 if (!(reg & M_SYS_PCI_HOST)) { 233 233 sb1250_bus_status |= PCI_DEVICE_MODE; 234 234 } else {
+3 -3
arch/mips/sibyte/bcm1480/smp.c
··· 34 34 * independent of board/firmware 35 35 */ 36 36 37 - static volatile void *mailbox_0_set_regs[] = { 37 + static void *mailbox_0_set_regs[] = { 38 38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 39 39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 40 40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 42 42 }; 43 43 44 - static volatile void *mailbox_0_clear_regs[] = { 44 + static void *mailbox_0_clear_regs[] = { 45 45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 46 46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 47 47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 49 49 }; 50 50 51 - static volatile void *mailbox_0_regs[] = { 51 + static void *mailbox_0_regs[] = { 52 52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 53 53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 54 54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
+10 -8
arch/mips/sibyte/swarm/setup.c
··· 169 169 #define LEDS_PHYS MLEDS_PHYS 170 170 #endif 171 171 172 - #define setled(index, c) \ 173 - ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c) 174 172 void setleds(char *str) 175 173 { 174 + void *reg; 176 175 int i; 176 + 177 177 for (i = 0; i < 4; i++) { 178 - if (!str[i]) { 179 - setled(i, ' '); 180 - } else { 181 - setled(i, str[i]); 182 - } 178 + reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3); 179 + 180 + if (!str[i]) 181 + writeb(' ', reg); 182 + else 183 + writeb(str[i], reg); 183 184 } 184 185 } 185 - #endif 186 + 187 + #endif /* LEDS_PHYS */
+1 -1
drivers/net/sb1250-mac.c
··· 243 243 * Controller-specific things 244 244 */ 245 245 246 - volatile void __iomem *sbm_base; /* MAC's base address */ 246 + void __iomem *sbm_base; /* MAC's base address */ 247 247 sbmac_state_t sbm_state; /* current state */ 248 248 249 249 volatile void __iomem *sbm_macenable; /* MAC Enable Register */
+1 -1
include/asm-mips/sibyte/sb1250.h
··· 67 67 68 68 #endif 69 69 70 - #define IOADDR(a) ((volatile void __iomem *)(IO_BASE + (a))) 70 + #define IOADDR(a) ((void __iomem *)(IO_BASE + (a))) 71 71 72 72 #endif