MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.

Signed-off-by: Tomaso Paoletti <[e-mail]>
Signed-off-by: David Daney <[e-mail]>
Signed-off-by: Ralf Baechle <[e-mail]>

arch/mips/include/asm/io.h

···
 #undef __IS_KSEG1
 }
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb()  		wmb()
+#else
+#define war_octeon_io_reorder_wmb()		do { } while (0)
+#endif
+
 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
 									\
 static inline void pfx##write##bwlq(type val,				\
···
 {									\
 	volatile type *__mem;						\
 	type __val;							\
+									\
+	war_octeon_io_reorder_wmb();					\
 									\
 	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
 									\
···
 {									\
 	volatile type *__addr;						\
 	type __val;							\
+									\
+	war_octeon_io_reorder_wmb();					\
 									\
 	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 									\
···
 #endif
 
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
 /* Depends on MIPS II instruction set */
 #define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
 
 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 {