Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

+13

Documentation/devicetree/bindings/arm/tegra.yaml

··· 52 52 - nvidia,cardhu-a04 53 53 - const: nvidia,cardhu 54 54 - const: nvidia,tegra30 55 + - description: ASUS Portable AiO P1801-T 56 + items: 57 + - const: asus,p1801-t 58 + - const: nvidia,tegra30 55 59 - description: ASUS Transformers Device family 56 60 items: 57 61 - enum: ··· 64 60 - asus,tf300tg 65 61 - asus,tf300tl 66 62 - asus,tf700t 63 + - const: nvidia,tegra30 64 + - description: Asus VivoTab RT 65 + items: 66 + - const: asus,tf600t 67 67 - const: nvidia,tegra30 68 68 - description: LG Optimus 4X P880 69 69 items: ··· 250 242 - const: nvidia,p3768-0000+p3767-0005 251 243 - const: nvidia,p3767-0005 252 244 - const: nvidia,tegra234 245 + - description: NVIDIA P3971-0089+P3834-0008 Engineering Reference Platform 246 + items: 247 + - const: nvidia,p3971-0089+p3834-0008 248 + - const: nvidia,p3834-0008 249 + - const: nvidia,tegra264 253 250 254 251 additionalProperties: true

+1

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml

··· 16 16 - nvidia,tegra186-pmc 17 17 - nvidia,tegra194-pmc 18 18 - nvidia,tegra234-pmc 19 + - nvidia,tegra264-pmc 19 20 20 21 reg: 21 22 minItems: 4

+1

Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml

··· 24 24 - const: nvidia,tegra186-gpcdma 25 25 - items: 26 26 - enum: 27 + - nvidia,tegra264-gpcdma 27 28 - nvidia,tegra234-gpcdma 28 29 - nvidia,tegra194-gpcdma 29 30 - const: nvidia,tegra186-gpcdma

+1

Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml

··· 70 70 - enum: 71 71 - nvidia,tegra194-bpmp 72 72 - nvidia,tegra234-bpmp 73 + - nvidia,tegra264-bpmp 73 74 - const: nvidia,tegra186-bpmp 74 75 - const: nvidia,tegra186-bpmp 75 76

+24 -4

Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml

··· 64 64 65 65 compatible: 66 66 oneOf: 67 - - const: nvidia,tegra186-hsp 68 - - const: nvidia,tegra194-hsp 69 - - const: nvidia,tegra264-hsp 67 + - enum: 68 + - nvidia,tegra186-hsp 69 + - nvidia,tegra194-hsp 70 + - nvidia,tegra264-hsp 70 71 - items: 71 72 - const: nvidia,tegra234-hsp 72 73 - const: nvidia,tegra194-hsp ··· 77 76 78 77 interrupts: 79 78 minItems: 1 80 - maxItems: 9 79 + maxItems: 17 81 80 82 81 interrupt-names: 83 82 oneOf: 84 83 # shared interrupts are optional 85 84 - items: 86 85 - const: doorbell 86 + 87 + - items: 88 + - const: doorbell 89 + - pattern: "^shared([0-9]|1[0-5])$" 90 + - pattern: "^shared([0-9]|1[0-5])$" 91 + - pattern: "^shared([0-9]|1[0-5])$" 92 + - pattern: "^shared([0-9]|1[0-5])$" 93 + - pattern: "^shared([0-9]|1[0-5])$" 94 + - pattern: "^shared([0-9]|1[0-5])$" 95 + - pattern: "^shared([0-9]|1[0-5])$" 96 + - pattern: "^shared([0-9]|1[0-5])$" 97 + - pattern: "^shared([0-9]|1[0-5])$" 98 + - pattern: "^shared([0-9]|1[0-5])$" 99 + - pattern: "^shared([0-9]|1[0-5])$" 100 + - pattern: "^shared([0-9]|1[0-5])$" 101 + - pattern: "^shared([0-9]|1[0-5])$" 102 + - pattern: "^shared([0-9]|1[0-5])$" 103 + - pattern: "^shared([0-9]|1[0-5])$" 104 + - pattern: "^shared([0-9]|1[0-5])$" 87 105 88 106 - items: 89 107 - const: doorbell

+82 -2

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml

··· 32 32 - nvidia,tegra186-mc 33 33 - nvidia,tegra194-mc 34 34 - nvidia,tegra234-mc 35 + - nvidia,tegra264-mc 35 36 36 37 reg: 37 38 minItems: 6 ··· 43 42 maxItems: 18 44 43 45 44 interrupts: 46 - items: 47 - - description: MC general interrupt 45 + minItems: 1 46 + maxItems: 8 47 + 48 + interrupt-names: 49 + minItems: 1 50 + maxItems: 8 48 51 49 52 "#address-cells": 50 53 const: 2 ··· 79 74 - nvidia,tegra186-emc 80 75 - nvidia,tegra194-emc 81 76 - nvidia,tegra234-emc 77 + - nvidia,tegra264-emc 82 78 83 79 reg: 84 80 minItems: 1 ··· 133 127 reg: 134 128 minItems: 2 135 129 130 + - if: 131 + properties: 132 + compatible: 133 + const: nvidia,tegra264-emc 134 + then: 135 + properties: 136 + reg: 137 + minItems: 2 138 + 136 139 additionalProperties: false 137 140 138 141 required: ··· 172 157 - const: ch1 173 158 - const: ch2 174 159 - const: ch3 160 + 161 + interrupts: 162 + items: 163 + - description: MC general interrupt 164 + 165 + interrupt-names: false 175 166 176 167 - if: 177 168 properties: ··· 210 189 - const: ch14 211 190 - const: ch15 212 191 192 + interrupts: 193 + items: 194 + - description: MC general interrupt 195 + 196 + interrupt-names: false 197 + 213 198 - if: 214 199 properties: 215 200 compatible: ··· 246 219 - const: ch13 247 220 - const: ch14 248 221 - const: ch15 222 + 223 + interrupts: 224 + items: 225 + - description: MC general interrupt 226 + 227 + interrupt-names: false 228 + 229 + - if: 230 + properties: 231 + compatible: 232 + const: nvidia,tegra264-mc 233 + then: 234 + properties: 235 + reg: 236 + minItems: 17 237 + maxItems: 17 238 + description: 17 memory controller channels 239 + 240 + reg-names: 241 + items: 242 + - const: broadcast 243 + - const: ch0 244 + - const: ch1 245 + - const: ch2 246 + - const: ch3 247 + - const: ch4 248 + - const: ch5 249 + - const: ch6 250 + - const: ch7 251 + - const: ch8 252 + - const: ch9 253 + - const: ch10 254 + - const: ch11 255 + - const: ch12 256 + - const: ch13 257 + - const: ch14 258 + - const: ch15 259 + 260 + interrupts: 261 + minItems: 8 262 + maxItems: 8 263 + description: One interrupt line for each MC component 264 + 265 + interrupt-names: 266 + items: 267 + - const: mcf 268 + - const: hub1 269 + - const: hub2 270 + - const: hub3 271 + - const: hub4 272 + - const: hub5 273 + - const: sbs 274 + - const: channel 249 275 250 276 additionalProperties: false 251 277

+1

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml

··· 20 20 - nvidia,tegra186-misc 21 21 - nvidia,tegra194-misc 22 22 - nvidia,tegra234-misc 23 + - nvidia,tegra264-misc 23 24 24 25 reg: 25 26 items:

+1

Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml

··· 28 28 - nvidia,tegra186-rtc 29 29 - nvidia,tegra194-rtc 30 30 - nvidia,tegra234-rtc 31 + - nvidia,tegra264-rtc 31 32 - const: nvidia,tegra20-rtc 32 33 33 34 reg:

+466

include/dt-bindings/clock/nvidia,tegra264.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ 3 + 4 + #ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H 5 + #define DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H 6 + 7 + #define TEGRA264_CLK_OSC 1 8 + #define TEGRA264_CLK_CLK_S 2 9 + #define TEGRA264_CLK_JTAG_REG 3 10 + #define TEGRA264_CLK_SPLL 4 11 + #define TEGRA264_CLK_SPLL_OUT0 5 12 + #define TEGRA264_CLK_SPLL_OUT1 6 13 + #define TEGRA264_CLK_SPLL_OUT2 7 14 + #define TEGRA264_CLK_SPLL_OUT3 8 15 + #define TEGRA264_CLK_SPLL_OUT4 9 16 + #define TEGRA264_CLK_SPLL_OUT5 10 17 + #define TEGRA264_CLK_SPLL_OUT6 11 18 + #define TEGRA264_CLK_SPLL_OUT7 12 19 + #define TEGRA264_CLK_AON_I2C 13 20 + #define TEGRA264_CLK_HOST1X 14 21 + #define TEGRA264_CLK_ISP 15 22 + #define TEGRA264_CLK_ISP1 16 23 + #define TEGRA264_CLK_ISP_ROOT 17 24 + #define TEGRA264_CLK_NAFLL_PVA0_CORE 18 25 + #define TEGRA264_CLK_NAFLL_PVA0_VPS 19 26 + #define TEGRA264_CLK_NVCSI 20 27 + #define TEGRA264_CLK_NVCSILP 21 28 + #define TEGRA264_CLK_PLLP_OUT0 22 29 + #define TEGRA264_CLK_PVA0_CPU_AXI 23 30 + #define TEGRA264_CLK_PVA0_VPS 24 31 + #define TEGRA264_CLK_PWM10 25 32 + #define TEGRA264_CLK_PWM2 26 33 + #define TEGRA264_CLK_PWM3 27 34 + #define TEGRA264_CLK_PWM4 28 35 + #define TEGRA264_CLK_PWM5 29 36 + #define TEGRA264_CLK_PWM9 30 37 + #define TEGRA264_CLK_QSPI0 31 38 + #define TEGRA264_CLK_QSPI0_2X_PM 32 39 + #define TEGRA264_CLK_RCE1_CPU 33 40 + #define TEGRA264_CLK_RCE1_NIC 34 41 + #define TEGRA264_CLK_RCE_CPU 35 42 + #define TEGRA264_CLK_RCE_NIC 36 43 + #define TEGRA264_CLK_SE 37 44 + #define TEGRA264_CLK_SEU1 38 45 + #define TEGRA264_CLK_SEU2 39 46 + #define TEGRA264_CLK_SEU3 40 47 + #define TEGRA264_CLK_SE_ROOT 41 48 + #define TEGRA264_CLK_SPI1 42 49 + #define TEGRA264_CLK_SPI2 43 50 + #define TEGRA264_CLK_SPI3 44 51 + #define TEGRA264_CLK_SPI4 45 52 + #define TEGRA264_CLK_SPI5 46 53 + #define TEGRA264_CLK_TOP_I2C 47 54 + #define TEGRA264_CLK_TSEC 48 55 + #define TEGRA264_CLK_TSEC_PKA 49 56 + #define TEGRA264_CLK_UART0 50 57 + #define TEGRA264_CLK_UART10 51 58 + #define TEGRA264_CLK_UART11 52 59 + #define TEGRA264_CLK_UART4 53 60 + #define TEGRA264_CLK_UART5 54 61 + #define TEGRA264_CLK_UART8 55 62 + #define TEGRA264_CLK_UART9 56 63 + #define TEGRA264_CLK_VI 57 64 + #define TEGRA264_CLK_VI1 58 65 + #define TEGRA264_CLK_VIC 59 66 + #define TEGRA264_CLK_VI_ROOT 60 67 + #define TEGRA264_CLK_DISPPLL 61 68 + #define TEGRA264_CLK_SPPLL0 62 69 + #define TEGRA264_CLK_SPPLL0_CLKOUT1A 63 70 + #define TEGRA264_CLK_SPPLL0_CLKOUT2A 64 71 + #define TEGRA264_CLK_SPPLL1 65 72 + #define TEGRA264_CLK_VPLL0 66 73 + #define TEGRA264_CLK_VPLL1 67 74 + #define TEGRA264_CLK_VPLL2 68 75 + #define TEGRA264_CLK_VPLL3 69 76 + #define TEGRA264_CLK_VPLL4 70 77 + #define TEGRA264_CLK_VPLL5 71 78 + #define TEGRA264_CLK_VPLL6 72 79 + #define TEGRA264_CLK_VPLL7 73 80 + #define TEGRA264_CLK_RG0_DIV 74 81 + #define TEGRA264_CLK_RG1_DIV 75 82 + #define TEGRA264_CLK_RG2_DIV 76 83 + #define TEGRA264_CLK_RG3_DIV 77 84 + #define TEGRA264_CLK_RG4_DIV 78 85 + #define TEGRA264_CLK_RG5_DIV 79 86 + #define TEGRA264_CLK_RG6_DIV 80 87 + #define TEGRA264_CLK_RG7_DIV 81 88 + #define TEGRA264_CLK_RG0 82 89 + #define TEGRA264_CLK_RG1 83 90 + #define TEGRA264_CLK_RG2 84 91 + #define TEGRA264_CLK_RG3 85 92 + #define TEGRA264_CLK_RG4 86 93 + #define TEGRA264_CLK_RG5 87 94 + #define TEGRA264_CLK_RG6 88 95 + #define TEGRA264_CLK_RG7 89 96 + #define TEGRA264_CLK_DISP 90 97 + #define TEGRA264_CLK_DSC 91 98 + #define TEGRA264_CLK_DSC_ROOT 92 99 + #define TEGRA264_CLK_HUB 93 100 + #define TEGRA264_CLK_VPLLX_SOR0_MUXED 94 101 + #define TEGRA264_CLK_VPLLX_SOR1_MUXED 95 102 + #define TEGRA264_CLK_VPLLX_SOR2_MUXED 96 103 + #define TEGRA264_CLK_VPLLX_SOR3_MUXED 97 104 + #define TEGRA264_CLK_LINKA_SYM 98 105 + #define TEGRA264_CLK_LINKB_SYM 99 106 + #define TEGRA264_CLK_LINKC_SYM 100 107 + #define TEGRA264_CLK_LINKD_SYM 101 108 + #define TEGRA264_CLK_PRE_SOR0 102 109 + #define TEGRA264_CLK_PRE_SOR1 103 110 + #define TEGRA264_CLK_PRE_SOR2 104 111 + #define TEGRA264_CLK_PRE_SOR3 105 112 + #define TEGRA264_CLK_SOR0_PLL_REF 106 113 + #define TEGRA264_CLK_SOR1_PLL_REF 107 114 + #define TEGRA264_CLK_SOR2_PLL_REF 108 115 + #define TEGRA264_CLK_SOR3_PLL_REF 109 116 + #define TEGRA264_CLK_SOR0_PAD 110 117 + #define TEGRA264_CLK_SOR1_PAD 111 118 + #define TEGRA264_CLK_SOR2_PAD 112 119 + #define TEGRA264_CLK_SOR3_PAD 113 120 + #define TEGRA264_CLK_SOR0_REF 114 121 + #define TEGRA264_CLK_SOR1_REF 115 122 + #define TEGRA264_CLK_SOR2_REF 116 123 + #define TEGRA264_CLK_SOR3_REF 117 124 + #define TEGRA264_CLK_SOR0_DIV 118 125 + #define TEGRA264_CLK_SOR1_DIV 119 126 + #define TEGRA264_CLK_SOR2_DIV 120 127 + #define TEGRA264_CLK_SOR3_DIV 121 128 + #define TEGRA264_CLK_SOR0 122 129 + #define TEGRA264_CLK_SOR1 123 130 + #define TEGRA264_CLK_SOR2 124 131 + #define TEGRA264_CLK_SOR3 125 132 + #define TEGRA264_CLK_SF0_SOR 126 133 + #define TEGRA264_CLK_SF1_SOR 127 134 + #define TEGRA264_CLK_SF2_SOR 128 135 + #define TEGRA264_CLK_SF3_SOR 129 136 + #define TEGRA264_CLK_SF4_SOR 130 137 + #define TEGRA264_CLK_SF5_SOR 131 138 + #define TEGRA264_CLK_SF6_SOR 132 139 + #define TEGRA264_CLK_SF7_SOR 133 140 + #define TEGRA264_CLK_SF0 134 141 + #define TEGRA264_CLK_SF1 135 142 + #define TEGRA264_CLK_SF2 136 143 + #define TEGRA264_CLK_SF3 137 144 + #define TEGRA264_CLK_SF4 138 145 + #define TEGRA264_CLK_SF5 139 146 + #define TEGRA264_CLK_SF6 140 147 + #define TEGRA264_CLK_SF7 141 148 + #define TEGRA264_CLK_MAUD 142 149 + #define TEGRA264_CLK_AZA_2XBIT 143 150 + #define TEGRA264_CLK_DCE_CPU 144 151 + #define TEGRA264_CLK_DCE_NIC 145 152 + #define TEGRA264_CLK_PLLC4 146 153 + #define TEGRA264_CLK_PLLC4_OUT0 147 154 + #define TEGRA264_CLK_PLLC4_OUT1 148 155 + #define TEGRA264_CLK_PLLC4_MUXED 149 156 + #define TEGRA264_CLK_SDMMC1 150 157 + #define TEGRA264_CLK_SDMMC_LEGACY_TM 151 158 + #define TEGRA264_CLK_PLLC0 152 159 + #define TEGRA264_CLK_NAFLL_BPMP 153 160 + #define TEGRA264_CLK_PLLP_OUT_PDIV 154 161 + #define TEGRA264_CLK_DISP_ROOT 155 162 + #define TEGRA264_CLK_ADSP 156 163 + #define TEGRA264_CLK_PLLA 157 164 + #define TEGRA264_CLK_PLLA1 158 165 + #define TEGRA264_CLK_PLLA1_OUT1 159 166 + #define TEGRA264_CLK_PLLAON 160 167 + #define TEGRA264_CLK_PLLAON_APE 161 168 + #define TEGRA264_CLK_PLLA_OUT0 162 169 + #define TEGRA264_CLK_AHUB 163 170 + #define TEGRA264_CLK_APE 164 171 + #define TEGRA264_CLK_I2S1_SCLK_IN 165 172 + #define TEGRA264_CLK_I2S2_SCLK_IN 166 173 + #define TEGRA264_CLK_I2S3_SCLK_IN 167 174 + #define TEGRA264_CLK_I2S4_SCLK_IN 168 175 + #define TEGRA264_CLK_I2S5_SCLK_IN 169 176 + #define TEGRA264_CLK_I2S6_SCLK_IN 170 177 + #define TEGRA264_CLK_I2S7_SCLK_IN 171 178 + #define TEGRA264_CLK_I2S8_SCLK_IN 172 179 + #define TEGRA264_CLK_I2S9_SCLK_IN 173 180 + #define TEGRA264_CLK_I2S1_AUDIO_SYNC 174 181 + #define TEGRA264_CLK_I2S2_AUDIO_SYNC 175 182 + #define TEGRA264_CLK_I2S3_AUDIO_SYNC 176 183 + #define TEGRA264_CLK_I2S4_AUDIO_SYNC 177 184 + #define TEGRA264_CLK_I2S5_AUDIO_SYNC 178 185 + #define TEGRA264_CLK_I2S6_AUDIO_SYNC 179 186 + #define TEGRA264_CLK_I2S7_AUDIO_SYNC 180 187 + #define TEGRA264_CLK_I2S8_AUDIO_SYNC 181 188 + #define TEGRA264_CLK_DMIC1_AUDIO_SYNC 182 189 + #define TEGRA264_CLK_DSPK1_AUDIO_SYNC 183 190 + #define TEGRA264_CLK_I2S1 184 191 + #define TEGRA264_CLK_I2S2 185 192 + #define TEGRA264_CLK_I2S3 186 193 + #define TEGRA264_CLK_I2S4 187 194 + #define TEGRA264_CLK_I2S5 188 195 + #define TEGRA264_CLK_I2S6 189 196 + #define TEGRA264_CLK_I2S7 190 197 + #define TEGRA264_CLK_I2S8 191 198 + #define TEGRA264_CLK_I2S9 192 199 + #define TEGRA264_CLK_DMIC1 193 200 + #define TEGRA264_CLK_DMIC5 194 201 + #define TEGRA264_CLK_DSPK1 195 202 + #define TEGRA264_CLK_AON_CPU 196 203 + #define TEGRA264_CLK_AON_NIC 197 204 + #define TEGRA264_CLK_BPMP 198 205 + #define TEGRA264_CLK_AXI_CBB 199 206 + #define TEGRA264_CLK_FUSE 200 207 + #define TEGRA264_CLK_TSENSE 201 208 + #define TEGRA264_CLK_CSITE 202 209 + #define TEGRA264_CLK_HCSITE 203 210 + #define TEGRA264_CLK_DBGAPB 204 211 + #define TEGRA264_CLK_LA 205 212 + #define TEGRA264_CLK_PLLREFGP 206 213 + #define TEGRA264_CLK_PLLE0 207 214 + #define TEGRA264_CLK_UPHY0_PLL0_XDIG 208 215 + #define TEGRA264_CLK_EQOS_APP 209 216 + #define TEGRA264_CLK_EQOS_MAC 210 217 + #define TEGRA264_CLK_EQOS_MACSEC 211 218 + #define TEGRA264_CLK_EQOS_TX_PCS 212 219 + #define TEGRA264_CLK_MGBES_PTP_REF 213 220 + #define TEGRA264_CLK_MGBE0_UPHY1_PLL_XDIG 214 221 + #define TEGRA264_CLK_MGBE0_TX_PCS 215 222 + #define TEGRA264_CLK_MGBE0_MAC 216 223 + #define TEGRA264_CLK_MGBE0_MACSEC 217 224 + #define TEGRA264_CLK_MGBE0_APP 218 225 + #define TEGRA264_CLK_MGBE1_UPHY1_PLL_XDIG 219 226 + #define TEGRA264_CLK_MGBE1_TX_PCS 220 227 + #define TEGRA264_CLK_MGBE1_MAC 221 228 + #define TEGRA264_CLK_MGBE1_MACSEC 222 229 + #define TEGRA264_CLK_MGBE1_APP 223 230 + #define TEGRA264_CLK_MGBE2_UPHY1_PLL_XDIG 224 231 + #define TEGRA264_CLK_MGBE2_TX_PCS 225 232 + #define TEGRA264_CLK_MGBE2_MAC 226 233 + #define TEGRA264_CLK_MGBE2_MACSEC 227 234 + #define TEGRA264_CLK_MGBE2_APP 228 235 + #define TEGRA264_CLK_MGBE3_UPHY1_PLL_XDIG 229 236 + #define TEGRA264_CLK_MGBE3_TX_PCS 230 237 + #define TEGRA264_CLK_MGBE3_MAC 231 238 + #define TEGRA264_CLK_MGBE3_MACSEC 232 239 + #define TEGRA264_CLK_MGBE3_APP 233 240 + #define TEGRA264_CLK_PLLREFUFS 234 241 + #define TEGRA264_CLK_PLLREFUFS_CLKOUT624 235 242 + #define TEGRA264_CLK_PLLREFUFS_REFCLKOUT 236 243 + #define TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT 237 244 + #define TEGRA264_CLK_UFSHC_CG_SYS 238 245 + #define TEGRA264_CLK_MPHY_L0_RX_LS_BIT_DIV 239 246 + #define TEGRA264_CLK_MPHY_L0_RX_LS_BIT 240 247 + #define TEGRA264_CLK_MPHY_L0_RX_LS_SYMB_DIV 241 248 + #define TEGRA264_CLK_MPHY_L0_RX_HS_SYMB_DIV 242 249 + #define TEGRA264_CLK_MPHY_L0_RX_SYMB 243 250 + #define TEGRA264_CLK_MPHY_L0_UPHY_TX_FIFO 244 251 + #define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT_DIV 245 252 + #define TEGRA264_CLK_MPHY_L0_TX_LS_SYMB_DIV 246 253 + #define TEGRA264_CLK_UPHY0_PLL4_XDIG 247 254 + #define TEGRA264_CLK_MPHY_L0_TX_HS_SYMB_DIV 248 255 + #define TEGRA264_CLK_MPHY_L0_TX_SYMB 249 256 + #define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT 250 257 + #define TEGRA264_CLK_MPHY_L0_RX_ANA 251 258 + #define TEGRA264_CLK_MPHY_L1_RX_ANA 252 259 + #define TEGRA264_CLK_MPHY_TX_1MHZ_REF 253 260 + #define TEGRA264_CLK_MPHY_CORE_PLL_FIXED 254 261 + #define TEGRA264_CLK_MPHY_IOBIST 255 262 + #define TEGRA264_CLK_UFSHC_CG_SYS_DIV 256 263 + #define TEGRA264_CLK_XUSB1_CORE 257 264 + #define TEGRA264_CLK_XUSB1_FALCON 258 265 + #define TEGRA264_CLK_XUSB1_FS 259 266 + #define TEGRA264_CLK_XUSB1_SS 260 267 + #define TEGRA264_CLK_UPHY0_USB_P0_RX_CORE 261 268 + #define TEGRA264_CLK_UPHY0_USB_P1_RX_CORE 262 269 + #define TEGRA264_CLK_UPHY0_USB_P2_RX_CORE 263 270 + #define TEGRA264_CLK_UPHY0_USB_P3_RX_CORE 264 271 + #define TEGRA264_CLK_XUSB1_CLK480M_NVWRAP_CORE 265 272 + #define TEGRA264_CLK_XUSB1_CORE_HOST 266 273 + #define TEGRA264_CLK_XUSB1_CORE_DEV 267 274 + #define TEGRA264_CLK_XUSB1_CORE_SUPERSPEED 268 275 + #define TEGRA264_CLK_XUSB1_FALCON_HOST 269 276 + #define TEGRA264_CLK_XUSB1_FALCON_SUPERSPEED 270 277 + #define TEGRA264_CLK_XUSB1_FS_HOST 271 278 + #define TEGRA264_CLK_XUSB1_FS_DEV 272 279 + #define TEGRA264_CLK_XUSB1_HS_HSICP 273 280 + #define TEGRA264_CLK_XUSB1_SS_DEV 274 281 + #define TEGRA264_CLK_XUSB1_SS_SUPERSPEED 275 282 + #define TEGRA264_CLK_AON_TOUCH 276 283 + #define TEGRA264_CLK_AUD_MCLK 277 284 + #define TEGRA264_CLK_EXTPERIPH1 278 285 + #define TEGRA264_CLK_EXTPERIPH2 279 286 + #define TEGRA264_CLK_EXTPERIPH3 280 287 + #define TEGRA264_CLK_EXTPERIPH4 281 288 + #define TEGRA264_CLK_JTAG_REG_UNGATED 282 289 + #define TEGRA264_CLK_IST_BUS 283 290 + #define TEGRA264_CLK_IST_BUS_RIST_MCC 284 291 + #define TEGRA264_CLK_MATHS_SEC_RIST 285 292 + #define TEGRA264_CLK_NAFLL_IST 286 293 + #define TEGRA264_CLK_RIST_ROOT 287 294 + #define TEGRA264_CLK_IST_CONTROLLER_RIST 288 295 + #define TEGRA264_CLK_MSS_ENCRYPT 289 296 + #define TEGRA264_CLK_EMC 290 297 + #define TEGRA264_CLK_SPPLL0_CLKOUT100 291 298 + #define TEGRA264_CLK_SPPLL0_CLKOUT270 292 299 + #define TEGRA264_CLK_SPPLL1_CLKOUT100 293 300 + #define TEGRA264_CLK_SPPLL1_CLKOUT270 294 301 + #define TEGRA264_CLK_DP_LINKA_REF 295 302 + #define TEGRA264_CLK_DP_LINKB_REF 296 303 + #define TEGRA264_CLK_DP_LINKC_REF 297 304 + #define TEGRA264_CLK_DP_LINKD_REF 298 305 + #define TEGRA264_CLK_PLLNVCSI 299 306 + #define TEGRA264_CLK_PLLBPMPCAM 300 307 + #define TEGRA264_CLK_UTMI_PLL1 301 308 + #define TEGRA264_CLK_UTMI_PLL1_CLKOUT48 302 309 + #define TEGRA264_CLK_UTMI_PLL1_CLKOUT60 303 310 + #define TEGRA264_CLK_UTMI_PLL1_CLKOUT480 304 311 + #define TEGRA264_CLK_NAFLL_ISP 305 312 + #define TEGRA264_CLK_NAFLL_RCE 306 313 + #define TEGRA264_CLK_NAFLL_RCE1 307 314 + #define TEGRA264_CLK_NAFLL_SE 308 315 + #define TEGRA264_CLK_NAFLL_VI 309 316 + #define TEGRA264_CLK_NAFLL_VIC 310 317 + #define TEGRA264_CLK_NAFLL_DCE 311 318 + #define TEGRA264_CLK_NAFLL_TSEC 312 319 + #define TEGRA264_CLK_NAFLL_CPAIR0 313 320 + #define TEGRA264_CLK_NAFLL_CPAIR1 314 321 + #define TEGRA264_CLK_NAFLL_CPAIR2 315 322 + #define TEGRA264_CLK_NAFLL_CPAIR3 316 323 + #define TEGRA264_CLK_NAFLL_CPAIR4 317 324 + #define TEGRA264_CLK_NAFLL_CPAIR5 318 325 + #define TEGRA264_CLK_NAFLL_CPAIR6 319 326 + #define TEGRA264_CLK_NAFLL_GPU_SYS 320 327 + #define TEGRA264_CLK_NAFLL_GPU_NVD 321 328 + #define TEGRA264_CLK_NAFLL_GPU_UPROC 322 329 + #define TEGRA264_CLK_NAFLL_GPU_GPC0 323 330 + #define TEGRA264_CLK_NAFLL_GPU_GPC1 324 331 + #define TEGRA264_CLK_NAFLL_GPU_GPC2 325 332 + #define TEGRA264_CLK_SOR_LINKA_INPUT 326 333 + #define TEGRA264_CLK_SOR_LINKB_INPUT 327 334 + #define TEGRA264_CLK_SOR_LINKC_INPUT 328 335 + #define TEGRA264_CLK_SOR_LINKD_INPUT 329 336 + #define TEGRA264_CLK_SOR_LINKA_AFIFO 330 337 + #define TEGRA264_CLK_SOR_LINKB_AFIFO 331 338 + #define TEGRA264_CLK_SOR_LINKC_AFIFO 332 339 + #define TEGRA264_CLK_SOR_LINKD_AFIFO 333 340 + #define TEGRA264_CLK_I2S1_PAD_M 334 341 + #define TEGRA264_CLK_I2S2_PAD_M 335 342 + #define TEGRA264_CLK_I2S3_PAD_M 336 343 + #define TEGRA264_CLK_I2S4_PAD_M 337 344 + #define TEGRA264_CLK_I2S5_PAD_M 338 345 + #define TEGRA264_CLK_I2S6_PAD_M 339 346 + #define TEGRA264_CLK_I2S7_PAD_M 340 347 + #define TEGRA264_CLK_I2S8_PAD_M 341 348 + #define TEGRA264_CLK_I2S9_PAD_M 342 349 + #define TEGRA264_CLK_BPMP_NIC 343 350 + #define TEGRA264_CLK_CLK1M 344 351 + #define TEGRA264_CLK_RDET 345 352 + #define TEGRA264_CLK_ADC_SOC_REF 346 353 + #define TEGRA264_CLK_UPHY0_PLL0_TXREF 347 354 + #define TEGRA264_CLK_EQOS_TX 348 355 + #define TEGRA264_CLK_EQOS_TX_M 349 356 + #define TEGRA264_CLK_EQOS_RX_PCS_IN 350 357 + #define TEGRA264_CLK_EQOS_RX_PCS_M 351 358 + #define TEGRA264_CLK_EQOS_RX_IN 352 359 + #define TEGRA264_CLK_EQOS_RX 353 360 + #define TEGRA264_CLK_EQOS_RX_M 354 361 + #define TEGRA264_CLK_MGBE0_UPHY1_PLL_TXREF 355 362 + #define TEGRA264_CLK_MGBE0_TX 356 363 + #define TEGRA264_CLK_MGBE0_TX_M 357 364 + #define TEGRA264_CLK_MGBE0_RX_PCS_IN 358 365 + #define TEGRA264_CLK_MGBE0_RX_PCS_M 359 366 + #define TEGRA264_CLK_MGBE0_RX_IN 360 367 + #define TEGRA264_CLK_MGBE0_RX_M 361 368 + #define TEGRA264_CLK_MGBE1_UPHY1_PLL_TXREF 362 369 + #define TEGRA264_CLK_MGBE1_TX 363 370 + #define TEGRA264_CLK_MGBE1_TX_M 364 371 + #define TEGRA264_CLK_MGBE1_RX_PCS_IN 365 372 + #define TEGRA264_CLK_MGBE1_RX_PCS_M 366 373 + #define TEGRA264_CLK_MGBE1_RX_IN 367 374 + #define TEGRA264_CLK_MGBE1_RX_M 368 375 + #define TEGRA264_CLK_MGBE2_UPHY1_PLL_TXREF 369 376 + #define TEGRA264_CLK_MGBE2_TX 370 377 + #define TEGRA264_CLK_MGBE2_TX_M 371 378 + #define TEGRA264_CLK_MGBE2_RX_PCS_IN 372 379 + #define TEGRA264_CLK_MGBE2_RX_PCS_M 373 380 + #define TEGRA264_CLK_MGBE2_RX_IN 374 381 + #define TEGRA264_CLK_MGBE2_RX_M 375 382 + #define TEGRA264_CLK_MGBE3_UPHY1_PLL_TXREF 376 383 + #define TEGRA264_CLK_MGBE3_TX 377 384 + #define TEGRA264_CLK_MGBE3_TX_M 378 385 + #define TEGRA264_CLK_MGBE3_RX_PCS_IN 379 386 + #define TEGRA264_CLK_MGBE3_RX_PCS_M 380 387 + #define TEGRA264_CLK_MGBE3_RX_IN 381 388 + #define TEGRA264_CLK_MGBE3_RX_M 382 389 + #define TEGRA264_CLK_UPHY0_USB_P0_TX_CORE 383 390 + #define TEGRA264_CLK_UPHY0_USB_P1_TX_CORE 384 391 + #define TEGRA264_CLK_UPHY0_USB_P2_TX_CORE 385 392 + #define TEGRA264_CLK_UPHY0_USB_P3_TX_CORE 386 393 + #define TEGRA264_CLK_UPHY0_USB_P0_TX 387 394 + #define TEGRA264_CLK_UPHY0_USB_P1_TX 388 395 + #define TEGRA264_CLK_UPHY0_USB_P2_TX 389 396 + #define TEGRA264_CLK_UPHY0_USB_P3_TX 390 397 + #define TEGRA264_CLK_UPHY0_USB_P0_RX_IN 391 398 + #define TEGRA264_CLK_UPHY0_USB_P1_RX_IN 392 399 + #define TEGRA264_CLK_UPHY0_USB_P2_RX_IN 393 400 + #define TEGRA264_CLK_UPHY0_USB_P3_RX_IN 394 401 + #define TEGRA264_CLK_UPHY0_USB_P0_RX_M 395 402 + #define TEGRA264_CLK_UPHY0_USB_P1_RX_M 396 403 + #define TEGRA264_CLK_UPHY0_USB_P2_RX_M 397 404 + #define TEGRA264_CLK_UPHY0_USB_P3_RX_M 398 405 + #define TEGRA264_CLK_UPHY0_LANE0_TX_M 399 406 + #define TEGRA264_CLK_PCIE_C1_XCLK_NOBG_M 400 407 + #define TEGRA264_CLK_PCIE_C2_XCLK_NOBG_M 401 408 + #define TEGRA264_CLK_PCIE_C3_XCLK_NOBG_M 402 409 + #define TEGRA264_CLK_PCIE_C4_XCLK_NOBG_M 403 410 + #define TEGRA264_CLK_PCIE_C5_XCLK_NOBG_M 404 411 + #define TEGRA264_CLK_PCIE_C1_L0_RX_M 405 412 + #define TEGRA264_CLK_PCIE_C1_L1_RX_M 406 413 + #define TEGRA264_CLK_PCIE_C1_L2_RX_M 407 414 + #define TEGRA264_CLK_PCIE_C1_L3_RX_M 408 415 + #define TEGRA264_CLK_PCIE_C2_L0_RX_M 409 416 + #define TEGRA264_CLK_PCIE_C2_L1_RX_M 410 417 + #define TEGRA264_CLK_PCIE_C2_L2_RX_M 411 418 + #define TEGRA264_CLK_PCIE_C2_L3_RX_M 412 419 + #define TEGRA264_CLK_PCIE_C3_L0_RX_M 413 420 + #define TEGRA264_CLK_PCIE_C3_L1_RX_M 414 421 + #define TEGRA264_CLK_PCIE_C4_L0_RX_M 415 422 + #define TEGRA264_CLK_PCIE_C4_L1_RX_M 416 423 + #define TEGRA264_CLK_PCIE_C4_L2_RX_M 417 424 + #define TEGRA264_CLK_PCIE_C4_L3_RX_M 418 425 + #define TEGRA264_CLK_PCIE_C4_L4_RX_M 419 426 + #define TEGRA264_CLK_PCIE_C4_L5_RX_M 420 427 + #define TEGRA264_CLK_PCIE_C4_L6_RX_M 421 428 + #define TEGRA264_CLK_PCIE_C4_L7_RX_M 422 429 + #define TEGRA264_CLK_PCIE_C5_L0_RX_M 423 430 + #define TEGRA264_CLK_PCIE_C5_L1_RX_M 424 431 + #define TEGRA264_CLK_PCIE_C5_L2_RX_M 425 432 + #define TEGRA264_CLK_PCIE_C5_L3_RX_M 426 433 + #define TEGRA264_CLK_MPHY_L0_RX_PWM_BIT_M 427 434 + #define TEGRA264_CLK_MPHY_L1_RX_PWM_BIT_M 428 435 + #define TEGRA264_CLK_DBB_UPHY0 429 436 + #define TEGRA264_CLK_UPHY0_UXL_CORE 430 437 + #define TEGRA264_CLK_ISC_CPU_ROOT 431 438 + #define TEGRA264_CLK_ISC_NIC 432 439 + #define TEGRA264_CLK_CTC_TXCLK0_M 433 440 + #define TEGRA264_CLK_CTC_TXCLK1_M 434 441 + #define TEGRA264_CLK_CTC_RXCLK0_M 435 442 + #define TEGRA264_CLK_CTC_RXCLK1_M 436 443 + #define TEGRA264_CLK_PLLREFGP_OUT 437 444 + #define TEGRA264_CLK_PLLREFGP_OUT1 438 445 + #define TEGRA264_CLK_GPU_SYS 439 446 + #define TEGRA264_CLK_GPU_NVD 440 447 + #define TEGRA264_CLK_GPU_UPROC 441 448 + #define TEGRA264_CLK_GPU_GPC0 442 449 + #define TEGRA264_CLK_GPU_GPC1 443 450 + #define TEGRA264_CLK_GPU_GPC2 444 451 + #define TEGRA264_CLK_PLLX 445 452 + #define TEGRA264_CLK_APE_SOUNDWIRE_MSRC0 446 453 + #define TEGRA264_CLK_APE_SOUNDWIRE_DATA_EN_SHAPER 447 454 + #define TEGRA264_CLK_AO_SOUNDWIRE_MSRC0 448 455 + #define TEGRA264_CLK_AO_SOUNDWIRE_DATA_EN_SHAPER 449 456 + #define TEGRA264_CLK_MGBE0_TX_SER 459 457 + #define TEGRA264_CLK_MGBE1_TX_SER 460 458 + #define TEGRA264_CLK_MGBE2_TX_SER 461 459 + #define TEGRA264_CLK_MGBE3_TX_SER 462 460 + #define TEGRA264_CLK_MGBE0_RX_SER 463 461 + #define TEGRA264_CLK_MGBE1_RX_SER 464 462 + #define TEGRA264_CLK_MGBE2_RX_SER 465 463 + #define TEGRA264_CLK_MGBE3_RX_SER 466 464 + #define TEGRA264_CLK_DPAUX 467 465 + 466 + #endif /* DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H */

+136

include/dt-bindings/memory/nvidia,tegra264.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 3 + 4 + #ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 5 + #define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 6 + 7 + #define TEGRA264_SID(x) ((x) << 8) 8 + 9 + /* 10 + * SMMU stream IDs 11 + */ 12 + 13 + #define TEGRA264_SID_AON TEGRA264_SID(0x01) 14 + #define TEGRA264_SID_APE TEGRA264_SID(0x02) 15 + #define TEGRA264_SID_ETR TEGRA264_SID(0x03) 16 + #define TEGRA264_SID_BPMP TEGRA264_SID(0x04) 17 + #define TEGRA264_SID_DCE TEGRA264_SID(0x05) 18 + #define TEGRA264_SID_EQOS TEGRA264_SID(0x06) 19 + #define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08) 20 + #define TEGRA264_SID_DISP TEGRA264_SID(0x09) 21 + #define TEGRA264_SID_HDA TEGRA264_SID(0x0a) 22 + #define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b) 23 + #define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c) 24 + #define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d) 25 + #define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e) 26 + #define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f) 27 + #define TEGRA264_SID_FSI1 TEGRA264_SID(0x10) 28 + #define TEGRA264_SID_PVA TEGRA264_SID(0x11) 29 + #define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12) 30 + #define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13) 31 + #define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14) 32 + #define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15) 33 + #define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16) 34 + #define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17) 35 + #define TEGRA264_SID_SE TEGRA264_SID(0x18) 36 + #define TEGRA264_SID_SEU1 TEGRA264_SID(0x19) 37 + #define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a) 38 + #define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b) 39 + #define TEGRA264_SID_PSC TEGRA264_SID(0x1c) 40 + #define TEGRA264_SID_OESP TEGRA264_SID(0x23) 41 + #define TEGRA264_SID_SB TEGRA264_SID(0x24) 42 + #define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25) 43 + #define TEGRA264_SID_TSEC TEGRA264_SID(0x29) 44 + #define TEGRA264_SID_UFS TEGRA264_SID(0x2a) 45 + #define TEGRA264_SID_RCE TEGRA264_SID(0x2b) 46 + #define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c) 47 + #define TEGRA264_SID_VI TEGRA264_SID(0x2e) 48 + #define TEGRA264_SID_VI1 TEGRA264_SID(0x2f) 49 + #define TEGRA264_SID_VIC TEGRA264_SID(0x30) 50 + #define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32) 51 + #define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33) 52 + #define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34) 53 + #define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35) 54 + #define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36) 55 + #define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37) 56 + 57 + /* 58 + * memory client IDs 59 + */ 60 + 61 + /* HOST1X read client */ 62 + #define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16 63 + /* VIC read client */ 64 + #define TEGRA264_MEMORY_CLIENT_VICR 0x6c 65 + /* VIC Write client */ 66 + #define TEGRA264_MEMORY_CLIENT_VICW 0x6d 67 + /* VI R5 Write client */ 68 + #define TEGRA264_MEMORY_CLIENT_VIW 0x72 69 + #define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78 70 + #define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79 71 + /* Audio processor(APE) Read client */ 72 + #define TEGRA264_MEMORY_CLIENT_APER 0x7a 73 + /* Audio processor(APE) Write client */ 74 + #define TEGRA264_MEMORY_CLIENT_APEW 0x7b 75 + /* Audio DMA Read client */ 76 + #define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f 77 + /* Audio DMA Write client */ 78 + #define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0 79 + #define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6 80 + #define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7 81 + /* VI Falcon Read client */ 82 + #define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc 83 + /* VI Falcon Write client */ 84 + #define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd 85 + /* Read Client of RCE */ 86 + #define TEGRA264_MEMORY_CLIENT_RCER 0xd2 87 + /* Write client of RCE */ 88 + #define TEGRA264_MEMORY_CLIENT_RCEW 0xd3 89 + /* PCIE0/MSI Write clients */ 90 + #define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9 91 + /* PCIE1/RPX4 Read clients */ 92 + #define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda 93 + /* PCIE1/RPX4 Write clients */ 94 + #define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb 95 + /* PCIE2/DMX4 Read clients */ 96 + #define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc 97 + /* PCIE2/DMX4 Write clients */ 98 + #define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd 99 + /* PCIE3/RPX4 Read clients */ 100 + #define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde 101 + /* PCIE3/RPX4 Write clients */ 102 + #define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf 103 + /* PCIE4/DMX8 Read clients */ 104 + #define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0 105 + /* PCIE4/DMX8 Write clients */ 106 + #define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1 107 + /* PCIE5/DMX4 Read clients */ 108 + #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 109 + /* PCIE5/DMX4 Write clients */ 110 + #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 111 + /* UFS Read client */ 112 + #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c 113 + /* UFS write client */ 114 + #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d 115 + /* HDA Read client */ 116 + #define TEGRA264_MEMORY_CLIENT_HDAR 0x17c 117 + /* HDA Write client */ 118 + #define TEGRA264_MEMORY_CLIENT_HDAW 0x17d 119 + /* Disp ISO Read Client */ 120 + #define TEGRA264_MEMORY_CLIENT_DISPR 0x182 121 + /* MGBE0 Read mccif */ 122 + #define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2 123 + /* MGBE0 Write mccif */ 124 + #define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3 125 + /* MGBE1 Read mccif */ 126 + #define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4 127 + /* MGBE1 Write mccif */ 128 + #define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5 129 + /* VI1 R5 Write client */ 130 + #define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6 131 + /* SDMMC0 Read mccif */ 132 + #define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2 133 + /* SDMMC0 Write mccif */ 134 + #define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3 135 + 136 + #endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */

+92

include/dt-bindings/reset/nvidia,tegra264.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ 3 + 4 + #ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA264_H 5 + #define DT_BINDINGS_RESET_NVIDIA_TEGRA264_H 6 + 7 + #define TEGRA264_RESET_APE_TKE 1 8 + #define TEGRA264_RESET_CEC 2 9 + #define TEGRA264_RESET_ADSP_ALL 3 10 + #define TEGRA264_RESET_RCE_ALL 4 11 + #define TEGRA264_RESET_UFSHC 5 12 + #define TEGRA264_RESET_UFSHC_AXI_M 6 13 + #define TEGRA264_RESET_UFSHC_LP_SEQ 7 14 + #define TEGRA264_RESET_DPAUX 8 15 + #define TEGRA264_RESET_EQOS_PCS 9 16 + #define TEGRA264_RESET_HWPM 10 17 + #define TEGRA264_RESET_I2C1 11 18 + #define TEGRA264_RESET_I2C2 12 19 + #define TEGRA264_RESET_I2C3 13 20 + #define TEGRA264_RESET_I2C4 14 21 + #define TEGRA264_RESET_I2C6 15 22 + #define TEGRA264_RESET_I2C7 16 23 + #define TEGRA264_RESET_I2C8 17 24 + #define TEGRA264_RESET_I2C9 18 25 + #define TEGRA264_RESET_ISP 19 26 + #define TEGRA264_RESET_LA 20 27 + #define TEGRA264_RESET_NVCSI 21 28 + #define TEGRA264_RESET_EQOS_MAC 22 29 + #define TEGRA264_RESET_PWM10 23 30 + #define TEGRA264_RESET_PWM2 24 31 + #define TEGRA264_RESET_PWM3 25 32 + #define TEGRA264_RESET_PWM4 26 33 + #define TEGRA264_RESET_PWM5 27 34 + #define TEGRA264_RESET_PWM9 28 35 + #define TEGRA264_RESET_QSPI0 29 36 + #define TEGRA264_RESET_HDA 30 37 + #define TEGRA264_RESET_HDACODEC 31 38 + #define TEGRA264_RESET_I2C0 32 39 + #define TEGRA264_RESET_I2C10 33 40 + #define TEGRA264_RESET_SDMMC1 34 41 + #define TEGRA264_RESET_MIPI_CAL 35 42 + #define TEGRA264_RESET_SPI1 36 43 + #define TEGRA264_RESET_SPI2 37 44 + #define TEGRA264_RESET_SPI3 38 45 + #define TEGRA264_RESET_SPI4 39 46 + #define TEGRA264_RESET_SPI5 40 47 + #define TEGRA264_RESET_SPI7 41 48 + #define TEGRA264_RESET_SPI8 42 49 + #define TEGRA264_RESET_SPI9 43 50 + #define TEGRA264_RESET_TACH0 44 51 + #define TEGRA264_RESET_TSEC 45 52 + #define TEGRA264_RESET_VI 46 53 + #define TEGRA264_RESET_VI1 47 54 + #define TEGRA264_RESET_PVA0_ALL 48 55 + #define TEGRA264_RESET_VIC 49 56 + #define TEGRA264_RESET_MPHY_CLK_CTL 50 57 + #define TEGRA264_RESET_MPHY_L0_RX 51 58 + #define TEGRA264_RESET_MPHY_L0_TX 52 59 + #define TEGRA264_RESET_MPHY_L1_RX 53 60 + #define TEGRA264_RESET_MPHY_L1_TX 54 61 + #define TEGRA264_RESET_ISP1 55 62 + #define TEGRA264_RESET_I2C11 56 63 + #define TEGRA264_RESET_I2C12 57 64 + #define TEGRA264_RESET_I2C14 58 65 + #define TEGRA264_RESET_I2C15 59 66 + #define TEGRA264_RESET_I2C16 60 67 + #define TEGRA264_RESET_EQOS_MACSEC 61 68 + #define TEGRA264_RESET_MGBE0_PCS 62 69 + #define TEGRA264_RESET_MGBE0_MAC 63 70 + #define TEGRA264_RESET_MGBE0_MACSEC 64 71 + #define TEGRA264_RESET_MGBE1_PCS 65 72 + #define TEGRA264_RESET_MGBE1_MAC 66 73 + #define TEGRA264_RESET_MGBE1_MACSEC 67 74 + #define TEGRA264_RESET_MGBE2_PCS 68 75 + #define TEGRA264_RESET_MGBE2_MAC 69 76 + #define TEGRA264_RESET_MGBE2_MACSEC 70 77 + #define TEGRA264_RESET_MGBE3_PCS 71 78 + #define TEGRA264_RESET_MGBE3_MAC 72 79 + #define TEGRA264_RESET_MGBE3_MACSEC 73 80 + #define TEGRA264_RESET_ADSP_CORE0 74 81 + #define TEGRA264_RESET_ADSP_CORE1 75 82 + #define TEGRA264_RESET_APE 76 83 + #define TEGRA264_RESET_XUSB1_PADCTL 77 84 + #define TEGRA264_RESET_AON_CPU_ALL 78 85 + #define TEGRA264_RESET_AON_HSP 79 86 + #define TEGRA264_RESET_UART4 80 87 + #define TEGRA264_RESET_UART5 81 88 + #define TEGRA264_RESET_UART9 82 89 + #define TEGRA264_RESET_UART10 83 90 + #define TEGRA264_RESET_UART8 84 91 + 92 + #endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA264_H */