Detect the MIPS R2 vectored interrupt, external interrupt controller options and the precense of the MT ASE.

+6

arch/mips/kernel/cpu-probe.c

··· 501 501 c->ases |= MIPS_ASE_SMARTMIPS; 502 502 if (config3 & MIPS_CONF3_DSP) 503 503 c->ases |= MIPS_ASE_DSP; 504 + if (config3 & MIPS_CONF3_VINT) 505 + c->options |= MIPS_CPU_VINT; 506 + if (config3 & MIPS_CONF3_VEIC) 507 + c->options |= MIPS_CPU_VEIC; 508 + if (config3 & MIPS_CONF3_MT) 509 + c->ases |= MIPS_ASE_MIPSMT; 504 510 505 511 return config3 & MIPS_CONF_M; 506 512 }

+24

include/asm-mips/cpu-features.h

··· 109 109 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 110 110 #endif 111 111 112 + #ifdef CONFIG_MIPS_MT 113 + #ifndef cpu_has_mipsmt 114 + # define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 115 + #endif 116 + #else 117 + # define cpu_has_mipsmt 0 118 + #endif 119 + 112 120 #ifdef CONFIG_32BIT 113 121 # ifndef cpu_has_nofpuex 114 122 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) ··· 151 143 # ifndef cpu_has_64bit_addresses 152 144 # define cpu_has_64bit_addresses 1 153 145 # endif 146 + #endif 147 + 148 + #ifdef CONFIG_CPU_MIPSR2 149 + # if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 150 + # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 151 + # else 152 + # define cpu_has_vint 0 153 + # endif 154 + # if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 155 + # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 156 + # else 157 + # define cpu_has_veic 0 158 + # endif 159 + #else 160 + # define cpu_has_vint 0 161 + # define cpu_has_veic 0 154 162 #endif 155 163 156 164 #ifndef cpu_has_subset_pcaches

+4

include/asm-mips/cpu.h

··· 227 227 #define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 228 228 #define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ 229 229 #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 230 + #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ 231 + #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ 230 232 231 233 /* 232 234 * CPU ASE encodings ··· 238 236 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 239 237 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 240 238 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 239 + #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 240 + 241 241 242 242 #endif /* _ASM_CPU_H */

+70 -48

include/asm-mips/mipsmtregs.h

··· 175 175 " .set noreorder \n" 176 176 " .set noat \n" 177 177 " .set mips32r2 \n" 178 - " move $1, %0 \n" 179 178 " .word 0x41610001 # dvpe $1 \n" 179 + " move %0, $1 \n" 180 180 " ehb \n" 181 181 " .set pop \n" 182 182 : "=r" (res)); ··· 214 214 int res; 215 215 216 216 __asm__ __volatile__( 217 - " .set noreorder \n" 217 + " .set push \n" 218 218 " .set mips32r2 \n" 219 - " dmt %0 \n" 219 + " .set noat \n" 220 + " .word 0x41610BC1 # dmt $1 \n" 220 221 " ehb \n" 221 - " .set mips0 \n" 222 - " .set reorder \n" 222 + " move %0, $1 \n" 223 + " .set pop \n" 223 224 : "=r" (res)); 224 225 225 226 instruction_hazard(); ··· 252 251 253 252 static inline void ehb(void) 254 253 { 255 - __asm__ __volatile__("ehb"); 254 + __asm__ __volatile__( 255 + " .set mips32r2 \n" 256 + " ehb \n" 257 + " .set mips0 \n"); 256 258 } 257 259 258 260 #define mftc0(rt,sel) \ ··· 263 259 unsigned long __res; \ 264 260 \ 265 261 __asm__ __volatile__( \ 266 - " .set noat\n\t" \ 267 - " mftc0\t%0," #rt ", " #sel "\n\t" \ 268 - " .set at\n\t" \ 269 - : "=r" (__res)); \ 262 + " .set push \n" \ 263 + " .set mips32r2 \n" \ 264 + " .set noat \n" \ 265 + " # mftc0 $1, $" #rt ", " #sel " \n" \ 266 + " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ 267 + " move %0, $1 \n" \ 268 + " .set pop \n" \ 269 + : "=r" (__res)); \ 270 270 \ 271 271 __res; \ 272 272 }) ··· 280 272 unsigned long __res; \ 281 273 \ 282 274 __asm__ __volatile__( \ 283 - " .set noat \n" \ 275 + " .set push \n" \ 276 + " .set mips32r2 \n" \ 284 277 " mftgpr %0," #rt " \n" \ 285 - " .set at \n" \ 278 + " .set pop \n" \ 286 279 : "=r" (__res)); \ 287 280 \ 288 281 __res; \ ··· 303 294 }) 304 295 305 296 #define mttgpr(rd,v) \ 306 - ({ \ 297 + do { \ 307 298 __asm__ __volatile__( \ 308 - "mttgpr %0," #rd \ 299 + " .set push \n" \ 300 + " .set mips32r2 \n" \ 301 + " .set noat \n" \ 302 + " move $1, %0 \n" \ 303 + " # mttgpr $1, " #rd " \n" \ 304 + " .word 0x41810020 | (" #rd " << 11) \n" \ 305 + " .set pop \n" \ 309 306 : : "r" (v)); \ 310 - }) 307 + } while (0) 311 308 312 309 #define mttc0(rd,sel,v) \ 313 310 ({ \ 314 311 __asm__ __volatile__( \ 315 - "mttc0\t %0," #rd ", " #sel \ 316 - : : "r" (v)); \ 312 + " .set push \n" \ 313 + " .set mips32r2 \n" \ 314 + " .set noat \n" \ 315 + " move $1, %0 \n" \ 316 + " # mttc0 %0," #rd ", " #sel " \n" \ 317 + " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ 318 + " .set pop \n" \ 319 + : \ 320 + : "r" (v)); \ 317 321 }) 318 322 319 323 ··· 346 324 347 325 348 326 /* you *must* set the target tc (settc) before trying to use these */ 349 - #define read_vpe_c0_vpecontrol() mftc0($1, 1) 350 - #define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val) 351 - #define read_vpe_c0_vpeconf0() mftc0($1, 2) 352 - #define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val) 353 - #define read_vpe_c0_status() mftc0($12, 0) 354 - #define write_vpe_c0_status(val) mttc0($12, 0, val) 355 - #define read_vpe_c0_cause() mftc0($13, 0) 356 - #define write_vpe_c0_cause(val) mttc0($13, 0, val) 357 - #define read_vpe_c0_config() mftc0($16, 0) 358 - #define write_vpe_c0_config(val) mttc0($16, 0, val) 359 - #define read_vpe_c0_config1() mftc0($16, 1) 360 - #define write_vpe_c0_config1(val) mttc0($16, 1, val) 361 - #define read_vpe_c0_config7() mftc0($16, 7) 362 - #define write_vpe_c0_config7(val) mttc0($16, 7, val) 363 - #define read_vpe_c0_ebase() mftc0($15,1) 364 - #define write_vpe_c0_ebase(val) mttc0($15, 1, val) 365 - #define write_vpe_c0_compare(val) mttc0($11, 0, val) 327 + #define read_vpe_c0_vpecontrol() mftc0(1, 1) 328 + #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) 329 + #define read_vpe_c0_vpeconf0() mftc0(1, 2) 330 + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) 331 + #define read_vpe_c0_status() mftc0(12, 0) 332 + #define write_vpe_c0_status(val) mttc0(12, 0, val) 333 + #define read_vpe_c0_cause() mftc0(13, 0) 334 + #define write_vpe_c0_cause(val) mttc0(13, 0, val) 335 + #define read_vpe_c0_config() mftc0(16, 0) 336 + #define write_vpe_c0_config(val) mttc0(16, 0, val) 337 + #define read_vpe_c0_config1() mftc0(16, 1) 338 + #define write_vpe_c0_config1(val) mttc0(16, 1, val) 339 + #define read_vpe_c0_config7() mftc0(16, 7) 340 + #define write_vpe_c0_config7(val) mttc0(16, 7, val) 341 + #define read_vpe_c0_ebase() mftc0(15,1) 342 + #define write_vpe_c0_ebase(val) mttc0(15, 1, val) 343 + #define write_vpe_c0_compare(val) mttc0(11, 0, val) 366 344 367 345 368 346 /* TC */ 369 - #define read_tc_c0_tcstatus() mftc0($2, 1) 370 - #define write_tc_c0_tcstatus(val) mttc0($2,1,val) 371 - #define read_tc_c0_tcbind() mftc0($2, 2) 372 - #define write_tc_c0_tcbind(val) mttc0($2,2,val) 373 - #define read_tc_c0_tcrestart() mftc0($2, 3) 374 - #define write_tc_c0_tcrestart(val) mttc0($2,3,val) 375 - #define read_tc_c0_tchalt() mftc0($2, 4) 376 - #define write_tc_c0_tchalt(val) mttc0($2,4,val) 377 - #define read_tc_c0_tccontext() mftc0($2, 5) 378 - #define write_tc_c0_tccontext(val) mttc0($2,5,val) 347 + #define read_tc_c0_tcstatus() mftc0(2, 1) 348 + #define write_tc_c0_tcstatus(val) mttc0(2,1,val) 349 + #define read_tc_c0_tcbind() mftc0(2, 2) 350 + #define write_tc_c0_tcbind(val) mttc0(2,2,val) 351 + #define read_tc_c0_tcrestart() mftc0(2, 3) 352 + #define write_tc_c0_tcrestart(val) mttc0(2,3,val) 353 + #define read_tc_c0_tchalt() mftc0(2, 4) 354 + #define write_tc_c0_tchalt(val) mttc0(2,4,val) 355 + #define read_tc_c0_tccontext() mftc0(2, 5) 356 + #define write_tc_c0_tccontext(val) mttc0(2,5,val) 379 357 380 358 /* GPR */ 381 - #define read_tc_gpr_sp() mftgpr($29) 382 - #define write_tc_gpr_sp(val) mttgpr($29, val) 383 - #define read_tc_gpr_gp() mftgpr($28) 384 - #define write_tc_gpr_gp(val) mttgpr($28, val) 359 + #define read_tc_gpr_sp() mftgpr(29) 360 + #define write_tc_gpr_sp(val) mttgpr(29, val) 361 + #define read_tc_gpr_gp() mftgpr(28) 362 + #define write_tc_gpr_gp(val) mttgpr(28, val) 385 363 386 364 387 365 #endif /* Not __ASSEMBLY__ */

+1

include/asm-mips/mipsregs.h

··· 528 528 529 529 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 530 530 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 531 + #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 531 532 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 532 533 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 533 534 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)