tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'at91-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 & LAN966 DT #1 for 5.19:
- at91: DT compliance updates to gic and dataflash nodes
- lan966: addition to many basic nodes for various peripherals
- lan966: Kontron KSwitch D10: support for this new board
and its network switch
* tag 'at91-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: kswitch-d10: enable networking
ARM: dts: lan966x: add switch node
ARM: dts: lan966x: add serdes node
ARM: dts: lan966x: add reset switch reset node
ARM: dts: lan966x: add MIIM nodes
ARM: dts: lan966x: add hwmon node
ARM: dts: lan966x: add basic Kontron KSwitch D10 support
ARM: dts: lan966x: add flexcom I2C nodes
ARM: dts: lan966x: add flexcom SPI nodes
ARM: dts: lan966x: add all flexcom usart nodes
ARM: dts: lan966x: add missing uart DMA channel
ARM: dts: lan966x: add sgpio node
ARM: dts: lan966x: swap dma channels for crypto node
ARM: dts: lan966x: rename pinctrl nodes
ARM: dts: at91: sama7g5: remove interrupt-parent from gic node
ARM: dts: at91: use generic node name for dataflash
Link: https://lore.kernel.org/r/20220513162338.87717-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+687
-16
+1
-1
Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
+1
-1
Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
+3
-1
arch/arm/boot/dts/Makefile
+3
-1
arch/arm/boot/dts/Makefile
···
768
768
dtb-$(CONFIG_SOC_IMXRT) += \
769
769
imxrt1050-evk.dtb
770
770
dtb-$(CONFIG_SOC_LAN966) += \
771
-
lan966x-pcb8291.dtb
771
+
lan966x-pcb8291.dtb \
772
+
lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
773
+
lan966x-kontron-kswitch-d10-mmt-8g.dtb
772
774
dtb-$(CONFIG_SOC_LS1021A) += \
773
775
ls1021a-iot.dtb \
774
776
ls1021a-moxa-uc-8410a.dtb \
+2
-2
arch/arm/boot/dts/at91rm9200ek.dts
+2
-2
arch/arm/boot/dts/at91rm9200ek.dts
···
73
73
spi0: spi@fffe0000 {
74
74
status = "okay";
75
75
cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
76
-
mtd_dataflash@0 {
76
+
flash@0 {
77
77
compatible = "atmel,at45", "atmel,dataflash";
78
78
spi-max-frequency = <15000000>;
79
79
reg = <0>;
···
94
94
status = "okay";
95
95
};
96
96
97
-
nor_flash@10000000 {
97
+
flash@10000000 {
98
98
compatible = "cfi-flash";
99
99
reg = <0x10000000 0x800000>;
100
100
linux,mtd-name = "physmap-flash.0";
+1
-1
arch/arm/boot/dts/at91sam9260ek.dts
+1
-1
arch/arm/boot/dts/at91sam9260ek.dts
+1
-1
arch/arm/boot/dts/at91sam9261ek.dts
+1
-1
arch/arm/boot/dts/at91sam9261ek.dts
+1
-1
arch/arm/boot/dts/at91sam9263ek.dts
+1
-1
arch/arm/boot/dts/at91sam9263ek.dts
+1
-1
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+1
-1
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+1
-1
arch/arm/boot/dts/at91sam9m10g45ek.dts
+1
-1
arch/arm/boot/dts/at91sam9m10g45ek.dts
+1
-1
arch/arm/boot/dts/at91sam9rlek.dts
+1
-1
arch/arm/boot/dts/at91sam9rlek.dts
+94
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
+94
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
4
+
*/
5
+
6
+
/dts-v1/;
7
+
#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
8
+
9
+
/ {
10
+
model = "Kontron KSwitch D10 MMT 6G-2GS";
11
+
compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
12
+
"microchip,lan9668", "microchip,lan966";
13
+
14
+
aliases {
15
+
i2c0 = &i2c4;
16
+
i2c1 = &i2c1;
17
+
};
18
+
19
+
sfp0: sfp0 {
20
+
compatible = "sff,sfp";
21
+
i2c-bus = <&i2c4>;
22
+
los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
23
+
mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
24
+
maximum-power-milliwatt = <2500>;
25
+
tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
26
+
tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
27
+
rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
28
+
rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
29
+
};
30
+
31
+
sfp1: sfp1 {
32
+
compatible = "sff,sfp";
33
+
i2c-bus = <&i2c1>;
34
+
los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
35
+
mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
36
+
maximum-power-milliwatt = <2500>;
37
+
tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
38
+
tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
39
+
rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
40
+
rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
41
+
};
42
+
};
43
+
44
+
&flx1 {
45
+
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
46
+
status = "okay";
47
+
48
+
i2c1: i2c@600 {
49
+
pinctrl-0 = <&fc1_c_pins>;
50
+
pinctrl-names = "default";
51
+
status = "okay";
52
+
};
53
+
};
54
+
55
+
&flx4 {
56
+
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
57
+
status = "okay";
58
+
59
+
i2c4: i2c@600 {
60
+
pinctrl-0 = <&fc4_b_pins>;
61
+
pinctrl-names = "default";
62
+
status = "okay";
63
+
};
64
+
};
65
+
66
+
&gpio {
67
+
fc1_c_pins: fc1-c-i2c-pins {
68
+
/* SCL, SDA */
69
+
pins = "GPIO_47", "GPIO_48";
70
+
function = "fc1_c";
71
+
};
72
+
73
+
fc4_b_pins: fc4-b-i2c-pins {
74
+
/* SCL, SDA */
75
+
pins = "GPIO_57", "GPIO_58";
76
+
function = "fc4_b";
77
+
};
78
+
};
79
+
80
+
&port2 {
81
+
phys = <&serdes 2 SERDES6G(0)>;
82
+
sfp = <&sfp0>;
83
+
managed = "in-band-status";
84
+
phy-mode = "sgmii";
85
+
status = "okay";
86
+
};
87
+
88
+
&port3 {
89
+
phys = <&serdes 3 SERDES6G(1)>;
90
+
sfp = <&sfp1>;
91
+
managed = "in-band-status";
92
+
phy-mode = "sgmii";
93
+
status = "okay";
94
+
};
+39
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
+39
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Device Tree file for the Kontron KSwitch D10 MMT 8G
4
+
*/
5
+
6
+
/dts-v1/;
7
+
#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
8
+
9
+
/ {
10
+
model = "Kontron KSwitch D10 MMT 8G";
11
+
compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
12
+
"microchip,lan9668", "microchip,lan966";
13
+
};
14
+
15
+
&mdio0 {
16
+
phy2: ethernet-phy@3 {
17
+
reg = <3>;
18
+
};
19
+
20
+
phy3: ethernet-phy@4 {
21
+
reg = <4>;
22
+
};
23
+
};
24
+
25
+
&port2 {
26
+
phys = <&serdes 2 SERDES6G(0)>;
27
+
phy-handle = <&phy2>;
28
+
phy-mode = "sgmii";
29
+
managed = "in-band-status";
30
+
status = "okay";
31
+
};
32
+
33
+
&port3 {
34
+
phys = <&serdes 3 SERDES6G(1)>;
35
+
phy-handle = <&phy3>;
36
+
phy-mode = "sgmii";
37
+
managed = "in-band-status";
38
+
status = "okay";
39
+
};
+190
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
+190
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Common part of the device tree for the Kontron KSwitch D10 MMT
4
+
*/
5
+
6
+
/dts-v1/;
7
+
#include "lan966x.dtsi"
8
+
#include "dt-bindings/phy/phy-lan966x-serdes.h"
9
+
10
+
/ {
11
+
aliases {
12
+
serial0 = &usart0;
13
+
};
14
+
15
+
chosen {
16
+
stdout-path = "serial0:115200n8";
17
+
};
18
+
19
+
gpio-restart {
20
+
compatible = "gpio-restart";
21
+
gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
22
+
priority = <200>;
23
+
};
24
+
};
25
+
26
+
&flx0 {
27
+
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
28
+
status = "okay";
29
+
30
+
usart0: serial@200 {
31
+
pinctrl-0 = <&usart0_pins>;
32
+
pinctrl-names = "default";
33
+
status = "okay";
34
+
};
35
+
};
36
+
37
+
&flx3 {
38
+
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
39
+
status = "okay";
40
+
41
+
spi3: spi@400 {
42
+
pinctrl-0 = <&fc3_b_pins>;
43
+
pinctrl-names = "default";
44
+
status = "okay";
45
+
cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
46
+
};
47
+
};
48
+
49
+
&gpio {
50
+
fc3_b_pins: fc3-b-pins {
51
+
/* SCK, MISO, MOSI */
52
+
pins = "GPIO_51", "GPIO_52", "GPIO_53";
53
+
function = "fc3_b";
54
+
};
55
+
56
+
miim_c_pins: miim-c-pins {
57
+
/* MDC, MDIO */
58
+
pins = "GPIO_59", "GPIO_60";
59
+
function = "miim_c";
60
+
};
61
+
62
+
sgpio_a_pins: sgpio-a-pins {
63
+
/* SCK, D0, D1 */
64
+
pins = "GPIO_32", "GPIO_33", "GPIO_34";
65
+
function = "sgpio_a";
66
+
};
67
+
68
+
sgpio_b_pins: sgpio-b-pins {
69
+
/* LD */
70
+
pins = "GPIO_64";
71
+
function = "sgpio_b";
72
+
};
73
+
74
+
usart0_pins: usart0-pins {
75
+
/* RXD, TXD */
76
+
pins = "GPIO_25", "GPIO_26";
77
+
function = "fc0_b";
78
+
};
79
+
};
80
+
81
+
&mdio0 {
82
+
pinctrl-0 = <&miim_c_pins>;
83
+
pinctrl-names = "default";
84
+
reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
85
+
clock-frequency = <2500000>;
86
+
status = "okay";
87
+
88
+
phy4: ethernet-phy@5 {
89
+
reg = <5>;
90
+
coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
91
+
};
92
+
93
+
phy5: ethernet-phy@6 {
94
+
reg = <6>;
95
+
coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
96
+
};
97
+
98
+
phy6: ethernet-phy@7 {
99
+
reg = <7>;
100
+
coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
101
+
};
102
+
103
+
phy7: ethernet-phy@8 {
104
+
reg = <8>;
105
+
coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
106
+
};
107
+
};
108
+
109
+
&mdio1 {
110
+
status = "okay";
111
+
};
112
+
113
+
&phy0 {
114
+
status = "okay";
115
+
};
116
+
117
+
&phy1 {
118
+
status = "okay";
119
+
};
120
+
121
+
&port0 {
122
+
phys = <&serdes 0 CU(0)>;
123
+
phy-handle = <&phy0>;
124
+
phy-mode = "gmii";
125
+
status = "okay";
126
+
};
127
+
128
+
&port1 {
129
+
phys = <&serdes 1 CU(1)>;
130
+
phy-handle = <&phy1>;
131
+
phy-mode = "gmii";
132
+
status = "okay";
133
+
};
134
+
135
+
&port4 {
136
+
phys = <&serdes 4 SERDES6G(2)>;
137
+
phy-handle = <&phy4>;
138
+
phy-mode = "qsgmii";
139
+
status = "okay";
140
+
};
141
+
142
+
&port5 {
143
+
phys = <&serdes 5 SERDES6G(2)>;
144
+
phy-handle = <&phy5>;
145
+
phy-mode = "qsgmii";
146
+
status = "okay";
147
+
};
148
+
149
+
&port6 {
150
+
phys = <&serdes 6 SERDES6G(2)>;
151
+
phy-handle = <&phy6>;
152
+
phy-mode = "qsgmii";
153
+
status = "okay";
154
+
};
155
+
156
+
&port7 {
157
+
phys = <&serdes 7 SERDES6G(2)>;
158
+
phy-handle = <&phy7>;
159
+
phy-mode = "qsgmii";
160
+
status = "okay";
161
+
};
162
+
163
+
&serdes {
164
+
status = "okay";
165
+
};
166
+
167
+
&sgpio {
168
+
pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
169
+
pinctrl-names = "default";
170
+
bus-frequency = <8000000>;
171
+
/* arbitrary range because all GPIOs are in software mode */
172
+
microchip,sgpio-port-ranges = <0 11>;
173
+
status = "okay";
174
+
175
+
sgpio_in: gpio@0 {
176
+
ngpios = <128>;
177
+
};
178
+
179
+
sgpio_out: gpio@1 {
180
+
ngpios = <128>;
181
+
};
182
+
};
183
+
184
+
&switch {
185
+
status = "okay";
186
+
};
187
+
188
+
&watchdog {
189
+
status = "okay";
190
+
};
+1
-1
arch/arm/boot/dts/lan966x-pcb8291.dts
+1
-1
arch/arm/boot/dts/lan966x-pcb8291.dts
+350
-3
arch/arm/boot/dts/lan966x.dtsi
+350
-3
arch/arm/boot/dts/lan966x.dtsi
···
84
84
#size-cells = <1>;
85
85
ranges;
86
86
87
+
switch: switch@e0000000 {
88
+
compatible = "microchip,lan966x-switch";
89
+
reg = <0xe0000000 0x0100000>,
90
+
<0xe2000000 0x0800000>;
91
+
reg-names = "cpu", "gcb";
92
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
93
+
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
94
+
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
95
+
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
96
+
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
97
+
interrupt-names = "xtr", "fdma", "ana", "ptp",
98
+
"ptp-ext";
99
+
resets = <&reset 0>;
100
+
reset-names = "switch";
101
+
status = "disabled";
102
+
103
+
ethernet-ports {
104
+
#address-cells = <1>;
105
+
#size-cells = <0>;
106
+
107
+
port0: port@0 {
108
+
reg = <0>;
109
+
status = "disabled";
110
+
};
111
+
112
+
port1: port@1 {
113
+
reg = <1>;
114
+
status = "disabled";
115
+
};
116
+
117
+
port2: port@2 {
118
+
reg = <2>;
119
+
status = "disabled";
120
+
};
121
+
122
+
port3: port@3 {
123
+
reg = <3>;
124
+
status = "disabled";
125
+
};
126
+
127
+
port4: port@4 {
128
+
reg = <4>;
129
+
status = "disabled";
130
+
};
131
+
132
+
port5: port@5 {
133
+
reg = <5>;
134
+
status = "disabled";
135
+
};
136
+
137
+
port6: port@6 {
138
+
reg = <6>;
139
+
status = "disabled";
140
+
};
141
+
142
+
port7: port@7 {
143
+
reg = <7>;
144
+
status = "disabled";
145
+
};
146
+
};
147
+
};
148
+
87
149
flx0: flexcom@e0040000 {
88
150
compatible = "atmel,sama5d2-flexcom";
89
151
reg = <0xe0040000 0x100>;
···
154
92
#size-cells = <1>;
155
93
ranges = <0x0 0xe0040000 0x800>;
156
94
status = "disabled";
95
+
96
+
usart0: serial@200 {
97
+
compatible = "atmel,at91sam9260-usart";
98
+
reg = <0x200 0x200>;
99
+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
100
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
101
+
<&dma0 AT91_XDMAC_DT_PERID(2)>;
102
+
dma-names = "tx", "rx";
103
+
clocks = <&nic_clk>;
104
+
clock-names = "usart";
105
+
atmel,fifo-size = <32>;
106
+
status = "disabled";
107
+
};
108
+
109
+
spi0: spi@400 {
110
+
compatible = "atmel,at91rm9200-spi";
111
+
reg = <0x400 0x200>;
112
+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
113
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
114
+
<&dma0 AT91_XDMAC_DT_PERID(2)>;
115
+
dma-names = "tx", "rx";
116
+
clocks = <&nic_clk>;
117
+
clock-names = "spi_clk";
118
+
atmel,fifo-size = <32>;
119
+
#address-cells = <1>;
120
+
#size-cells = <0>;
121
+
status = "disabled";
122
+
};
123
+
124
+
i2c0: i2c@600 {
125
+
compatible = "microchip,sam9x60-i2c";
126
+
reg = <0x600 0x200>;
127
+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
128
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
129
+
<&dma0 AT91_XDMAC_DT_PERID(2)>;
130
+
dma-names = "tx", "rx";
131
+
clocks = <&nic_clk>;
132
+
#address-cells = <1>;
133
+
#size-cells = <0>;
134
+
status = "disabled";
135
+
};
157
136
};
158
137
159
138
flx1: flexcom@e0044000 {
···
205
102
#size-cells = <1>;
206
103
ranges = <0x0 0xe0044000 0x800>;
207
104
status = "disabled";
105
+
106
+
usart1: serial@200 {
107
+
compatible = "atmel,at91sam9260-usart";
108
+
reg = <0x200 0x200>;
109
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
110
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
111
+
<&dma0 AT91_XDMAC_DT_PERID(4)>;
112
+
dma-names = "tx", "rx";
113
+
clocks = <&nic_clk>;
114
+
clock-names = "usart";
115
+
atmel,fifo-size = <32>;
116
+
status = "disabled";
117
+
};
118
+
119
+
spi1: spi@400 {
120
+
compatible = "atmel,at91rm9200-spi";
121
+
reg = <0x400 0x200>;
122
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
123
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
124
+
<&dma0 AT91_XDMAC_DT_PERID(4)>;
125
+
dma-names = "tx", "rx";
126
+
clocks = <&nic_clk>;
127
+
clock-names = "spi_clk";
128
+
atmel,fifo-size = <32>;
129
+
#address-cells = <1>;
130
+
#size-cells = <0>;
131
+
status = "disabled";
132
+
};
133
+
134
+
i2c1: i2c@600 {
135
+
compatible = "microchip,sam9x60-i2c";
136
+
reg = <0x600 0x200>;
137
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
138
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
139
+
<&dma0 AT91_XDMAC_DT_PERID(4)>;
140
+
dma-names = "tx", "rx";
141
+
clocks = <&nic_clk>;
142
+
#address-cells = <1>;
143
+
#size-cells = <0>;
144
+
status = "disabled";
145
+
};
208
146
};
209
147
210
148
trng: rng@e0048000 {
···
258
114
compatible = "atmel,at91sam9g46-aes";
259
115
reg = <0xe004c000 0x100>;
260
116
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
261
-
dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
262
-
<&dma0 AT91_XDMAC_DT_PERID(12)>;
263
-
dma-names = "rx", "tx";
117
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
118
+
<&dma0 AT91_XDMAC_DT_PERID(13)>;
119
+
dma-names = "tx", "rx";
264
120
clocks = <&nic_clk>;
265
121
clock-names = "aes_clk";
266
122
};
···
273
129
#size-cells = <1>;
274
130
ranges = <0x0 0xe0060000 0x800>;
275
131
status = "disabled";
132
+
133
+
usart2: serial@200 {
134
+
compatible = "atmel,at91sam9260-usart";
135
+
reg = <0x200 0x200>;
136
+
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
137
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
138
+
<&dma0 AT91_XDMAC_DT_PERID(6)>;
139
+
dma-names = "tx", "rx";
140
+
clocks = <&nic_clk>;
141
+
clock-names = "usart";
142
+
atmel,fifo-size = <32>;
143
+
status = "disabled";
144
+
};
145
+
146
+
spi2: spi@400 {
147
+
compatible = "atmel,at91rm9200-spi";
148
+
reg = <0x400 0x200>;
149
+
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
150
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
151
+
<&dma0 AT91_XDMAC_DT_PERID(6)>;
152
+
dma-names = "tx", "rx";
153
+
clocks = <&nic_clk>;
154
+
clock-names = "spi_clk";
155
+
atmel,fifo-size = <32>;
156
+
#address-cells = <1>;
157
+
#size-cells = <0>;
158
+
status = "disabled";
159
+
};
160
+
161
+
i2c2: i2c@600 {
162
+
compatible = "microchip,sam9x60-i2c";
163
+
reg = <0x600 0x200>;
164
+
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
165
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
166
+
<&dma0 AT91_XDMAC_DT_PERID(6)>;
167
+
dma-names = "tx", "rx";
168
+
clocks = <&nic_clk>;
169
+
#address-cells = <1>;
170
+
#size-cells = <0>;
171
+
status = "disabled";
172
+
};
276
173
};
277
174
278
175
flx3: flexcom@e0064000 {
···
329
144
compatible = "atmel,at91sam9260-usart";
330
145
reg = <0x200 0x200>;
331
146
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
147
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
148
+
<&dma0 AT91_XDMAC_DT_PERID(8)>;
149
+
dma-names = "tx", "rx";
332
150
clocks = <&nic_clk>;
333
151
clock-names = "usart";
334
152
atmel,fifo-size = <32>;
153
+
status = "disabled";
154
+
};
155
+
156
+
spi3: spi@400 {
157
+
compatible = "atmel,at91rm9200-spi";
158
+
reg = <0x400 0x200>;
159
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
160
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
161
+
<&dma0 AT91_XDMAC_DT_PERID(8)>;
162
+
dma-names = "tx", "rx";
163
+
clocks = <&nic_clk>;
164
+
clock-names = "spi_clk";
165
+
atmel,fifo-size = <32>;
166
+
#address-cells = <1>;
167
+
#size-cells = <0>;
168
+
status = "disabled";
169
+
};
170
+
171
+
i2c3: i2c@600 {
172
+
compatible = "microchip,sam9x60-i2c";
173
+
reg = <0x600 0x200>;
174
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
175
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
176
+
<&dma0 AT91_XDMAC_DT_PERID(8)>;
177
+
dma-names = "tx", "rx";
178
+
clocks = <&nic_clk>;
179
+
#address-cells = <1>;
180
+
#size-cells = <0>;
335
181
status = "disabled";
336
182
};
337
183
};
···
394
178
#size-cells = <1>;
395
179
ranges = <0x0 0xe0070000 0x800>;
396
180
status = "disabled";
181
+
182
+
usart4: serial@200 {
183
+
compatible = "atmel,at91sam9260-usart";
184
+
reg = <0x200 0x200>;
185
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
186
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
187
+
<&dma0 AT91_XDMAC_DT_PERID(10)>;
188
+
dma-names = "tx", "rx";
189
+
clocks = <&nic_clk>;
190
+
clock-names = "usart";
191
+
atmel,fifo-size = <32>;
192
+
status = "disabled";
193
+
};
194
+
195
+
spi4: spi@400 {
196
+
compatible = "atmel,at91rm9200-spi";
197
+
reg = <0x400 0x200>;
198
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
199
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
200
+
<&dma0 AT91_XDMAC_DT_PERID(10)>;
201
+
dma-names = "tx", "rx";
202
+
clocks = <&nic_clk>;
203
+
clock-names = "spi_clk";
204
+
atmel,fifo-size = <32>;
205
+
#address-cells = <1>;
206
+
#size-cells = <0>;
207
+
status = "disabled";
208
+
};
209
+
210
+
i2c4: i2c@600 {
211
+
compatible = "microchip,sam9x60-i2c";
212
+
reg = <0x600 0x200>;
213
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
214
+
dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
215
+
<&dma0 AT91_XDMAC_DT_PERID(10)>;
216
+
dma-names = "tx", "rx";
217
+
clocks = <&nic_clk>;
218
+
#address-cells = <1>;
219
+
#size-cells = <0>;
220
+
status = "disabled";
221
+
};
397
222
};
398
223
399
224
timer0: timer@e008c000 {
···
453
196
status = "disabled";
454
197
};
455
198
199
+
cpu_ctrl: syscon@e00c0000 {
200
+
compatible = "microchip,lan966x-cpu-syscon", "syscon";
201
+
reg = <0xe00c0000 0x350>;
202
+
};
203
+
456
204
can0: can@e081c000 {
457
205
compatible = "bosch,m_can";
458
206
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
···
473
211
status = "disabled";
474
212
};
475
213
214
+
reset: reset-controller@e200400c {
215
+
compatible = "microchip,lan966x-switch-reset";
216
+
reg = <0xe200400c 0x4>;
217
+
reg-names = "gcb";
218
+
#reset-cells = <1>;
219
+
cpu-syscon = <&cpu_ctrl>;
220
+
};
221
+
476
222
gpio: pinctrl@e2004064 {
477
223
compatible = "microchip,lan966x-pinctrl";
478
224
reg = <0xe2004064 0xb4>,
479
225
<0xe2010024 0x138>;
226
+
resets = <&reset 0>;
227
+
reset-names = "switch";
480
228
gpio-controller;
481
229
#gpio-cells = <2>;
482
230
gpio-ranges = <&gpio 0 0 78>;
483
231
interrupt-controller;
484
232
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
485
233
#interrupt-cells = <2>;
234
+
};
235
+
236
+
mdio0: mdio@e2004118 {
237
+
compatible = "microchip,lan966x-miim";
238
+
#address-cells = <1>;
239
+
#size-cells = <0>;
240
+
reg = <0xe2004118 0x24>;
241
+
clocks = <&sys_clk>;
242
+
status = "disabled";
243
+
};
244
+
245
+
mdio1: mdio@e200413c {
246
+
compatible = "microchip,lan966x-miim";
247
+
#address-cells = <1>;
248
+
#size-cells = <0>;
249
+
reg = <0xe200413c 0x24>,
250
+
<0xe2010020 0x4>;
251
+
clocks = <&sys_clk>;
252
+
status = "disabled";
253
+
254
+
phy0: ethernet-phy@1 {
255
+
reg = <1>;
256
+
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
257
+
status = "disabled";
258
+
};
259
+
260
+
phy1: ethernet-phy@2 {
261
+
reg = <2>;
262
+
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
263
+
status = "disabled";
264
+
};
265
+
};
266
+
267
+
sgpio: gpio@e2004190 {
268
+
compatible = "microchip,sparx5-sgpio";
269
+
reg = <0xe2004190 0x118>;
270
+
clocks = <&sys_clk>;
271
+
resets = <&reset 0>;
272
+
reset-names = "switch";
273
+
#address-cells = <1>;
274
+
#size-cells = <0>;
275
+
status = "disabled";
276
+
277
+
sgpio_in: gpio@0 {
278
+
compatible = "microchip,sparx5-sgpio-bank";
279
+
reg = <0>;
280
+
gpio-controller;
281
+
#gpio-cells = <3>;
282
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
283
+
interrupt-controller;
284
+
#interrupt-cells = <3>;
285
+
};
286
+
287
+
sgpio_out: gpio@1 {
288
+
compatible = "microchip,sparx5-sgpio-bank";
289
+
reg = <1>;
290
+
gpio-controller;
291
+
#gpio-cells = <3>;
292
+
};
293
+
};
294
+
295
+
hwmon: hwmon@e2010180 {
296
+
compatible = "microchip,lan9668-hwmon";
297
+
reg = <0xe2010180 0xc>,
298
+
<0xe20042a8 0xc>;
299
+
reg-names = "pvt", "fan";
300
+
clocks = <&sys_clk>;
301
+
};
302
+
303
+
serdes: serdes@e202c000 {
304
+
compatible = "microchip,lan966x-serdes";
305
+
reg = <0xe202c000 0x9c>,
306
+
<0xe2004010 0x4>;
307
+
#phy-cells = <2>;
308
+
status = "disabled";
486
309
};
487
310
488
311
gic: interrupt-controller@e8c11000 {
-1
arch/arm/boot/dts/sama7g5.dtsi
-1
arch/arm/boot/dts/sama7g5.dtsi