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tg3: spelling corrections

Correct spelling as flagged by codespell.

Signed-off-by: Simon Horman <horms@kernel.org>
Reviewed-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Simon Horman and committed by
David S. Miller
8efa26fc 67e3ba97

+3 -3
+2 -2
drivers/net/ethernet/broadcom/tg3.c
··· 6686 6686 * We only need to fill in the address because the other members 6687 6687 * of the RX descriptor are invariant, see tg3_init_rings. 6688 6688 * 6689 - * Note the purposeful assymetry of cpu vs. chip accesses. For 6689 + * Note the purposeful asymmetry of cpu vs. chip accesses. For 6690 6690 * posting buffers we only dirty the first cache line of the RX 6691 6691 * descriptor (containing the address). Whereas for the RX status 6692 6692 * buffers the cpu only reads the last cacheline of the RX descriptor ··· 10145 10145 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; 10146 10146 10147 10147 /* Pseudo-header checksum is done by hardware logic and not 10148 - * the offload processers, so make the chip do the pseudo- 10148 + * the offload processors, so make the chip do the pseudo- 10149 10149 * header checksums on receive. For transmit it is more 10150 10150 * convenient to do the pseudo-header checksum in software 10151 10151 * as Linux does that on transmit for us in all cases.
+1 -1
drivers/net/ethernet/broadcom/tg3.h
··· 2390 2390 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2391 2391 2392 2392 2393 - /* Fast Ethernet Tranceiver definitions */ 2393 + /* Fast Ethernet Transceiver definitions */ 2394 2394 #define MII_TG3_FET_PTEST 0x17 2395 2395 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2396 2396 #define MII_TG3_FET_PTEST_TRIM_2 0x0002