tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: IP27: Fix build errors with CONFIG_PCI disabled.
LD init/built-in.o
arch/mips/built-in.o: In function `startup_bridge_irq':
ip27-irq.c:(.text+0x434): undefined reference to `irq_to_slot'
ip27-irq.c:(.text+0x43c): undefined reference to `irq_to_slot'
ip27-irq.c:(.text+0x460): undefined reference to `irq_to_bridge'
ip27-irq.c:(.text+0x464): undefined reference to `irq_to_bridge'
arch/mips/built-in.o: In function `shutdown_bridge_irq':
ip27-irq.c:(.text+0x564): undefined reference to `irq_to_bridge'
ip27-irq.c:(.text+0x56c): undefined reference to `irq_to_bridge'
ip27-irq.c:(.text+0x5a0): undefined reference to `irq_to_slot'
ip27-irq.c:(.text+0x5a4): undefined reference to `irq_to_slot'
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+267
-214
+1
arch/mips/sgi-ip27/Makefile
+1
arch/mips/sgi-ip27/Makefile
+266
arch/mips/sgi-ip27/ip27-irq-pci.c
+266
arch/mips/sgi-ip27/ip27-irq-pci.c
···
1
+
/*
2
+
* ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
3
+
*
4
+
* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5
+
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6
+
* Copyright (C) 1999 - 2001 Kanoj Sarcar
7
+
*/
8
+
9
+
#undef DEBUG
10
+
11
+
#include <linux/init.h>
12
+
#include <linux/irq.h>
13
+
#include <linux/errno.h>
14
+
#include <linux/signal.h>
15
+
#include <linux/sched.h>
16
+
#include <linux/types.h>
17
+
#include <linux/interrupt.h>
18
+
#include <linux/ioport.h>
19
+
#include <linux/timex.h>
20
+
#include <linux/smp.h>
21
+
#include <linux/random.h>
22
+
#include <linux/kernel.h>
23
+
#include <linux/kernel_stat.h>
24
+
#include <linux/delay.h>
25
+
#include <linux/bitops.h>
26
+
27
+
#include <asm/bootinfo.h>
28
+
#include <asm/io.h>
29
+
#include <asm/mipsregs.h>
30
+
31
+
#include <asm/processor.h>
32
+
#include <asm/pci/bridge.h>
33
+
#include <asm/sn/addrs.h>
34
+
#include <asm/sn/agent.h>
35
+
#include <asm/sn/arch.h>
36
+
#include <asm/sn/hub.h>
37
+
#include <asm/sn/intr.h>
38
+
39
+
/*
40
+
* Linux has a controller-independent x86 interrupt architecture.
41
+
* every controller has a 'controller-template', that is used
42
+
* by the main code to do the right thing. Each driver-visible
43
+
* interrupt source is transparently wired to the appropriate
44
+
* controller. Thus drivers need not be aware of the
45
+
* interrupt-controller.
46
+
*
47
+
* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
48
+
* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
49
+
* (IO-APICs assumed to be messaging to Pentium local-APICs)
50
+
*
51
+
* the code is designed to be easily extended with new/different
52
+
* interrupt controllers, without having to do assembly magic.
53
+
*/
54
+
55
+
extern struct bridge_controller *irq_to_bridge[];
56
+
extern int irq_to_slot[];
57
+
58
+
/*
59
+
* use these macros to get the encoded nasid and widget id
60
+
* from the irq value
61
+
*/
62
+
#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
63
+
#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
64
+
65
+
static inline int alloc_level(int cpu, int irq)
66
+
{
67
+
struct hub_data *hub = hub_data(cpu_to_node(cpu));
68
+
struct slice_data *si = cpu_data[cpu].data;
69
+
int level;
70
+
71
+
level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
72
+
if (level >= LEVELS_PER_SLICE)
73
+
panic("Cpu %d flooded with devices", cpu);
74
+
75
+
__set_bit(level, hub->irq_alloc_mask);
76
+
si->level_to_irq[level] = irq;
77
+
78
+
return level;
79
+
}
80
+
81
+
static inline int find_level(cpuid_t *cpunum, int irq)
82
+
{
83
+
int cpu, i;
84
+
85
+
for_each_online_cpu(cpu) {
86
+
struct slice_data *si = cpu_data[cpu].data;
87
+
88
+
for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
89
+
if (si->level_to_irq[i] == irq) {
90
+
*cpunum = cpu;
91
+
92
+
return i;
93
+
}
94
+
}
95
+
96
+
panic("Could not identify cpu/level for irq %d", irq);
97
+
}
98
+
99
+
static int intr_connect_level(int cpu, int bit)
100
+
{
101
+
nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
102
+
struct slice_data *si = cpu_data[cpu].data;
103
+
104
+
set_bit(bit, si->irq_enable_mask);
105
+
106
+
if (!cputoslice(cpu)) {
107
+
REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
108
+
REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
109
+
} else {
110
+
REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
111
+
REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
112
+
}
113
+
114
+
return 0;
115
+
}
116
+
117
+
static int intr_disconnect_level(int cpu, int bit)
118
+
{
119
+
nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
120
+
struct slice_data *si = cpu_data[cpu].data;
121
+
122
+
clear_bit(bit, si->irq_enable_mask);
123
+
124
+
if (!cputoslice(cpu)) {
125
+
REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
126
+
REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
127
+
} else {
128
+
REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
129
+
REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
130
+
}
131
+
132
+
return 0;
133
+
}
134
+
135
+
/* Startup one of the (PCI ...) IRQs routes over a bridge. */
136
+
static unsigned int startup_bridge_irq(struct irq_data *d)
137
+
{
138
+
struct bridge_controller *bc;
139
+
bridgereg_t device;
140
+
bridge_t *bridge;
141
+
int pin, swlevel;
142
+
cpuid_t cpu;
143
+
144
+
pin = SLOT_FROM_PCI_IRQ(d->irq);
145
+
bc = IRQ_TO_BRIDGE(d->irq);
146
+
bridge = bc->base;
147
+
148
+
pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
149
+
/*
150
+
* "map" irq to a swlevel greater than 6 since the first 6 bits
151
+
* of INT_PEND0 are taken
152
+
*/
153
+
swlevel = find_level(&cpu, d->irq);
154
+
bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
155
+
bridge->b_int_enable |= (1 << pin);
156
+
bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
157
+
158
+
/*
159
+
* Enable sending of an interrupt clear packt to the hub on a high to
160
+
* low transition of the interrupt pin.
161
+
*
162
+
* IRIX sets additional bits in the address which are documented as
163
+
* reserved in the bridge docs.
164
+
*/
165
+
bridge->b_int_mode |= (1UL << pin);
166
+
167
+
/*
168
+
* We assume the bridge to have a 1:1 mapping between devices
169
+
* (slots) and intr pins.
170
+
*/
171
+
device = bridge->b_int_device;
172
+
device &= ~(7 << (pin*3));
173
+
device |= (pin << (pin*3));
174
+
bridge->b_int_device = device;
175
+
176
+
bridge->b_wid_tflush;
177
+
178
+
intr_connect_level(cpu, swlevel);
179
+
180
+
return 0; /* Never anything pending. */
181
+
}
182
+
183
+
/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
184
+
static void shutdown_bridge_irq(struct irq_data *d)
185
+
{
186
+
struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
187
+
bridge_t *bridge = bc->base;
188
+
int pin, swlevel;
189
+
cpuid_t cpu;
190
+
191
+
pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
192
+
pin = SLOT_FROM_PCI_IRQ(d->irq);
193
+
194
+
/*
195
+
* map irq to a swlevel greater than 6 since the first 6 bits
196
+
* of INT_PEND0 are taken
197
+
*/
198
+
swlevel = find_level(&cpu, d->irq);
199
+
intr_disconnect_level(cpu, swlevel);
200
+
201
+
bridge->b_int_enable &= ~(1 << pin);
202
+
bridge->b_wid_tflush;
203
+
}
204
+
205
+
static inline void enable_bridge_irq(struct irq_data *d)
206
+
{
207
+
cpuid_t cpu;
208
+
int swlevel;
209
+
210
+
swlevel = find_level(&cpu, d->irq); /* Criminal offence */
211
+
intr_connect_level(cpu, swlevel);
212
+
}
213
+
214
+
static inline void disable_bridge_irq(struct irq_data *d)
215
+
{
216
+
cpuid_t cpu;
217
+
int swlevel;
218
+
219
+
swlevel = find_level(&cpu, d->irq); /* Criminal offence */
220
+
intr_disconnect_level(cpu, swlevel);
221
+
}
222
+
223
+
static struct irq_chip bridge_irq_type = {
224
+
.name = "bridge",
225
+
.irq_startup = startup_bridge_irq,
226
+
.irq_shutdown = shutdown_bridge_irq,
227
+
.irq_mask = disable_bridge_irq,
228
+
.irq_unmask = enable_bridge_irq,
229
+
};
230
+
231
+
void register_bridge_irq(unsigned int irq)
232
+
{
233
+
irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
234
+
}
235
+
236
+
int request_bridge_irq(struct bridge_controller *bc)
237
+
{
238
+
int irq = allocate_irqno();
239
+
int swlevel, cpu;
240
+
nasid_t nasid;
241
+
242
+
if (irq < 0)
243
+
return irq;
244
+
245
+
/*
246
+
* "map" irq to a swlevel greater than 6 since the first 6 bits
247
+
* of INT_PEND0 are taken
248
+
*/
249
+
cpu = bc->irq_cpu;
250
+
swlevel = alloc_level(cpu, irq);
251
+
if (unlikely(swlevel < 0)) {
252
+
free_irqno(irq);
253
+
254
+
return -EAGAIN;
255
+
}
256
+
257
+
/* Make sure it's not already pending when we connect it. */
258
+
nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
259
+
REMOTE_HUB_CLR_INTR(nasid, swlevel);
260
+
261
+
intr_connect_level(cpu, swlevel);
262
+
263
+
register_bridge_irq(irq);
264
+
265
+
return irq;
266
+
}
-214
arch/mips/sgi-ip27/ip27-irq.c
-214
arch/mips/sgi-ip27/ip27-irq.c
···
29
29
#include <asm/mipsregs.h>
30
30
31
31
#include <asm/processor.h>
32
-
#include <asm/pci/bridge.h>
33
32
#include <asm/sn/addrs.h>
34
33
#include <asm/sn/agent.h>
35
34
#include <asm/sn/arch.h>
···
52
53
*/
53
54
54
55
extern asmlinkage void ip27_irq(void);
55
-
56
-
extern struct bridge_controller *irq_to_bridge[];
57
-
extern int irq_to_slot[];
58
-
59
-
/*
60
-
* use these macros to get the encoded nasid and widget id
61
-
* from the irq value
62
-
*/
63
-
#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
64
-
#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
65
-
66
-
static inline int alloc_level(int cpu, int irq)
67
-
{
68
-
struct hub_data *hub = hub_data(cpu_to_node(cpu));
69
-
struct slice_data *si = cpu_data[cpu].data;
70
-
int level;
71
-
72
-
level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
73
-
if (level >= LEVELS_PER_SLICE)
74
-
panic("Cpu %d flooded with devices", cpu);
75
-
76
-
__set_bit(level, hub->irq_alloc_mask);
77
-
si->level_to_irq[level] = irq;
78
-
79
-
return level;
80
-
}
81
-
82
-
static inline int find_level(cpuid_t *cpunum, int irq)
83
-
{
84
-
int cpu, i;
85
-
86
-
for_each_online_cpu(cpu) {
87
-
struct slice_data *si = cpu_data[cpu].data;
88
-
89
-
for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
90
-
if (si->level_to_irq[i] == irq) {
91
-
*cpunum = cpu;
92
-
93
-
return i;
94
-
}
95
-
}
96
-
97
-
panic("Could not identify cpu/level for irq %d", irq);
98
-
}
99
56
100
57
/*
101
58
* Find first bit set
···
157
202
static void ip27_hub_error(void)
158
203
{
159
204
panic("CPU %d got a hub error interrupt", smp_processor_id());
160
-
}
161
-
162
-
static int intr_connect_level(int cpu, int bit)
163
-
{
164
-
nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
165
-
struct slice_data *si = cpu_data[cpu].data;
166
-
167
-
set_bit(bit, si->irq_enable_mask);
168
-
169
-
if (!cputoslice(cpu)) {
170
-
REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
171
-
REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
172
-
} else {
173
-
REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
174
-
REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
175
-
}
176
-
177
-
return 0;
178
-
}
179
-
180
-
static int intr_disconnect_level(int cpu, int bit)
181
-
{
182
-
nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
183
-
struct slice_data *si = cpu_data[cpu].data;
184
-
185
-
clear_bit(bit, si->irq_enable_mask);
186
-
187
-
if (!cputoslice(cpu)) {
188
-
REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
189
-
REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
190
-
} else {
191
-
REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
192
-
REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
193
-
}
194
-
195
-
return 0;
196
-
}
197
-
198
-
/* Startup one of the (PCI ...) IRQs routes over a bridge. */
199
-
static unsigned int startup_bridge_irq(struct irq_data *d)
200
-
{
201
-
struct bridge_controller *bc;
202
-
bridgereg_t device;
203
-
bridge_t *bridge;
204
-
int pin, swlevel;
205
-
cpuid_t cpu;
206
-
207
-
pin = SLOT_FROM_PCI_IRQ(d->irq);
208
-
bc = IRQ_TO_BRIDGE(d->irq);
209
-
bridge = bc->base;
210
-
211
-
pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
212
-
/*
213
-
* "map" irq to a swlevel greater than 6 since the first 6 bits
214
-
* of INT_PEND0 are taken
215
-
*/
216
-
swlevel = find_level(&cpu, d->irq);
217
-
bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
218
-
bridge->b_int_enable |= (1 << pin);
219
-
bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
220
-
221
-
/*
222
-
* Enable sending of an interrupt clear packt to the hub on a high to
223
-
* low transition of the interrupt pin.
224
-
*
225
-
* IRIX sets additional bits in the address which are documented as
226
-
* reserved in the bridge docs.
227
-
*/
228
-
bridge->b_int_mode |= (1UL << pin);
229
-
230
-
/*
231
-
* We assume the bridge to have a 1:1 mapping between devices
232
-
* (slots) and intr pins.
233
-
*/
234
-
device = bridge->b_int_device;
235
-
device &= ~(7 << (pin*3));
236
-
device |= (pin << (pin*3));
237
-
bridge->b_int_device = device;
238
-
239
-
bridge->b_wid_tflush;
240
-
241
-
intr_connect_level(cpu, swlevel);
242
-
243
-
return 0; /* Never anything pending. */
244
-
}
245
-
246
-
/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
247
-
static void shutdown_bridge_irq(struct irq_data *d)
248
-
{
249
-
struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
250
-
bridge_t *bridge = bc->base;
251
-
int pin, swlevel;
252
-
cpuid_t cpu;
253
-
254
-
pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
255
-
pin = SLOT_FROM_PCI_IRQ(d->irq);
256
-
257
-
/*
258
-
* map irq to a swlevel greater than 6 since the first 6 bits
259
-
* of INT_PEND0 are taken
260
-
*/
261
-
swlevel = find_level(&cpu, d->irq);
262
-
intr_disconnect_level(cpu, swlevel);
263
-
264
-
bridge->b_int_enable &= ~(1 << pin);
265
-
bridge->b_wid_tflush;
266
-
}
267
-
268
-
static inline void enable_bridge_irq(struct irq_data *d)
269
-
{
270
-
cpuid_t cpu;
271
-
int swlevel;
272
-
273
-
swlevel = find_level(&cpu, d->irq); /* Criminal offence */
274
-
intr_connect_level(cpu, swlevel);
275
-
}
276
-
277
-
static inline void disable_bridge_irq(struct irq_data *d)
278
-
{
279
-
cpuid_t cpu;
280
-
int swlevel;
281
-
282
-
swlevel = find_level(&cpu, d->irq); /* Criminal offence */
283
-
intr_disconnect_level(cpu, swlevel);
284
-
}
285
-
286
-
static struct irq_chip bridge_irq_type = {
287
-
.name = "bridge",
288
-
.irq_startup = startup_bridge_irq,
289
-
.irq_shutdown = shutdown_bridge_irq,
290
-
.irq_mask = disable_bridge_irq,
291
-
.irq_unmask = enable_bridge_irq,
292
-
};
293
-
294
-
void register_bridge_irq(unsigned int irq)
295
-
{
296
-
irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
297
-
}
298
-
299
-
int request_bridge_irq(struct bridge_controller *bc)
300
-
{
301
-
int irq = allocate_irqno();
302
-
int swlevel, cpu;
303
-
nasid_t nasid;
304
-
305
-
if (irq < 0)
306
-
return irq;
307
-
308
-
/*
309
-
* "map" irq to a swlevel greater than 6 since the first 6 bits
310
-
* of INT_PEND0 are taken
311
-
*/
312
-
cpu = bc->irq_cpu;
313
-
swlevel = alloc_level(cpu, irq);
314
-
if (unlikely(swlevel < 0)) {
315
-
free_irqno(irq);
316
-
317
-
return -EAGAIN;
318
-
}
319
-
320
-
/* Make sure it's not already pending when we connect it. */
321
-
nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
322
-
REMOTE_HUB_CLR_INTR(nasid, swlevel);
323
-
324
-
intr_connect_level(cpu, swlevel);
325
-
326
-
register_bridge_irq(irq);
327
-
328
-
return irq;
329
205
}
330
206
331
207
asmlinkage void plat_irq_dispatch(void)