Merge tag 'power-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

+12 -2

arch/arm/mach-exynos/common.h

··· 134 134 135 135 /* PMU(Power Management Unit) support */ 136 136 137 - #define PMU_TABLE_END NULL 137 + #define PMU_TABLE_END (-1U) 138 138 139 139 enum sys_powerdown { 140 140 SYS_AFTR, ··· 144 144 }; 145 145 146 146 struct exynos_pmu_conf { 147 - void __iomem *reg; 147 + unsigned int offset; 148 148 unsigned int val[NUM_SYS_POWERDOWN]; 149 149 }; 150 150 ··· 159 159 160 160 extern void s5p_init_cpu(void __iomem *cpuid_addr); 161 161 extern unsigned int samsung_rev(void); 162 + 163 + static inline void pmu_raw_writel(u32 val, u32 offset) 164 + { 165 + __raw_writel(val, pmu_base_addr + offset); 166 + } 167 + 168 + static inline u32 pmu_raw_readl(u32 offset) 169 + { 170 + return __raw_readl(pmu_base_addr + offset); 171 + } 162 172 163 173 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

+5 -25

arch/arm/mach-exynos/exynos.c

··· 61 61 .length = SZ_4K, 62 62 .type = MT_DEVICE, 63 63 }, { 64 - .virtual = (unsigned long)S5P_VA_PMU, 65 - .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), 66 - .length = SZ_64K, 67 - .type = MT_DEVICE, 68 - }, { 69 64 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 70 65 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), 71 66 .length = SZ_4K, ··· 134 139 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 135 140 .length = 144 * SZ_1K, 136 141 .type = MT_DEVICE, 137 - }, { 138 - .virtual = (unsigned long)S5P_VA_PMU, 139 - .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), 140 - .length = SZ_64K, 141 - .type = MT_DEVICE, 142 142 }, 143 143 }; 144 144 ··· 141 151 { 142 152 struct device_node *np; 143 153 u32 val = 0x1; 144 - void __iomem *addr = EXYNOS_SWRESET; 154 + void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET; 145 155 146 156 if (of_machine_is_compatible("samsung,exynos5440")) { 147 157 u32 status; ··· 164 174 .dev.platform_data = exynos_enter_aftr, 165 175 .id = -1, 166 176 }; 167 - 168 - void __init exynos_cpuidle_init(void) 169 - { 170 - if (soc_is_exynos4210() || soc_is_exynos5250()) 171 - platform_device_register(&exynos_cpuidle); 172 - } 173 - 174 - void __init exynos_cpufreq_init(void) 175 - { 176 - platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); 177 - } 178 177 179 178 void __iomem *sysram_base_addr; 180 179 void __iomem *sysram_ns_base_addr; ··· 314 335 if (!IS_ENABLED(CONFIG_SMP)) 315 336 exynos_sysram_init(); 316 337 317 - if (!of_machine_is_compatible("samsung,exynos5420")) 318 - exynos_cpuidle_init(); 338 + if (of_machine_is_compatible("samsung,exynos4210") || 339 + of_machine_is_compatible("samsung,exynos5250")) 340 + platform_device_register(&exynos_cpuidle); 319 341 320 - exynos_cpufreq_init(); 342 + platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); 321 343 322 344 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 323 345 }

-3

arch/arm/mach-exynos/include/mach/map.h

··· 27 27 #define EXYNOS4_PA_SYSCON 0x10010000 28 28 #define EXYNOS5_PA_SYSCON 0x10050100 29 29 30 - #define EXYNOS4_PA_PMU 0x10020000 31 - #define EXYNOS5_PA_PMU 0x10040000 32 - 33 30 #define EXYNOS4_PA_CMU 0x10030000 34 31 #define EXYNOS5_PA_CMU 0x10010000 35 32

+33 -37

arch/arm/mach-exynos/mcpm-exynos.c

··· 26 26 #define EXYNOS5420_CPUS_PER_CLUSTER 4 27 27 #define EXYNOS5420_NR_CLUSTERS 2 28 28 29 + #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9) 30 + #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) 31 + #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) 32 + 29 33 /* 30 34 * The common v7_exit_coherency_flush API could not be used because of the 31 35 * Erratum 799270 workaround. This macro is the same as the common one (in ··· 55 51 "dsb\n\t" \ 56 52 "ldmfd sp!, {fp, ip}" \ 57 53 : \ 58 - : "Ir" (S5P_INFORM0) \ 54 + : "Ir" (pmu_base_addr + S5P_INFORM0) \ 59 55 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 60 56 "r9", "r10", "lr", "memory") 61 57 ··· 77 73 78 74 #define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster) 79 75 80 - static int exynos_cluster_power_control(unsigned int cluster, int enable) 81 - { 82 - unsigned int tries = 100; 83 - unsigned int val; 84 - 85 - if (enable) { 86 - exynos_cluster_power_up(cluster); 87 - val = S5P_CORE_LOCAL_PWR_EN; 88 - } else { 89 - exynos_cluster_power_down(cluster); 90 - val = 0; 91 - } 92 - 93 - /* Wait until cluster power control is applied */ 94 - while (tries--) { 95 - if (exynos_cluster_power_state(cluster) == val) 96 - return 0; 97 - 98 - cpu_relax(); 99 - } 100 - pr_debug("timed out waiting for cluster %u to power %s\n", cluster, 101 - enable ? "on" : "off"); 102 - 103 - return -ETIMEDOUT; 104 - } 105 - 106 76 static int exynos_power_up(unsigned int cpu, unsigned int cluster) 107 77 { 108 78 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); 109 - int err = 0; 110 79 111 80 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); 112 81 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || ··· 103 126 * cores. 104 127 */ 105 128 if (was_cluster_down) 106 - err = exynos_cluster_power_control(cluster, 1); 129 + exynos_cluster_power_up(cluster); 107 130 108 - if (!err) 109 - exynos_cpu_power_up(cpunr); 110 - else 111 - exynos_cluster_power_control(cluster, 0); 131 + exynos_cpu_power_up(cpunr); 112 132 } else if (cpu_use_count[cpu][cluster] != 2) { 113 133 /* 114 134 * The only possible values are: ··· 121 147 arch_spin_unlock(&exynos_mcpm_lock); 122 148 local_irq_enable(); 123 149 124 - return err; 150 + return 0; 125 151 } 126 152 127 153 /* ··· 152 178 if (cpu_use_count[cpu][cluster] == 0) { 153 179 exynos_cpu_power_down(cpunr); 154 180 155 - if (exynos_cluster_unused(cluster)) 156 - /* TODO: Turn off the cluster here to save power. */ 181 + if (exynos_cluster_unused(cluster)) { 182 + exynos_cluster_power_down(cluster); 157 183 last_man = true; 184 + } 158 185 } else if (cpu_use_count[cpu][cluster] == 1) { 159 186 /* 160 187 * A power_up request went ahead of us. ··· 310 335 { 311 336 struct device_node *node; 312 337 void __iomem *ns_sram_base_addr; 338 + unsigned int value, i; 313 339 int ret; 314 340 315 341 node = of_find_matching_node(NULL, exynos_dt_mcpm_match); ··· 337 361 * To increase the stability of KFC reset we need to program 338 362 * the PMU SPARE3 register 339 363 */ 340 - __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); 364 + pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); 341 365 342 366 exynos_mcpm_usage_count_init(); 343 367 ··· 352 376 mcpm_smp_set_ops(); 353 377 354 378 pr_info("Exynos MCPM support installed\n"); 379 + 380 + /* 381 + * On Exynos5420/5800 for the A15 and A7 clusters: 382 + * 383 + * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores 384 + * in a cluster are turned off before turning off the cluster L2. 385 + * 386 + * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered 387 + * off before waking it up. 388 + * 389 + * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be 390 + * turned on before the first man is powered up. 391 + */ 392 + for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) { 393 + value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i)); 394 + value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN | 395 + EXYNOS5420_USE_ARM_CORE_DOWN_STATE | 396 + EXYNOS5420_USE_L2_COMMON_UP_STATE; 397 + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); 398 + } 355 399 356 400 /* 357 401 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr

+3 -1

arch/arm/mach-exynos/platsmp.c

··· 26 26 #include <asm/smp_scu.h> 27 27 #include <asm/firmware.h> 28 28 29 + #include <mach/map.h> 30 + 29 31 #include "common.h" 30 32 #include "regs-pmu.h" 31 33 ··· 36 34 static inline void __iomem *cpu_boot_reg_base(void) 37 35 { 38 36 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 39 - return S5P_INFORM5; 37 + return pmu_base_addr + S5P_INFORM5; 40 38 return sysram_base_addr; 41 39 } 42 40

+40 -36

arch/arm/mach-exynos/pm.c

··· 111 111 */ 112 112 void exynos_cpu_power_down(int cpu) 113 113 { 114 - __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 114 + pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 115 115 } 116 116 117 117 /** ··· 122 122 */ 123 123 void exynos_cpu_power_up(int cpu) 124 124 { 125 - __raw_writel(S5P_CORE_LOCAL_PWR_EN, 126 - EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 125 + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, 126 + EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 127 127 } 128 128 129 129 /** ··· 133 133 */ 134 134 int exynos_cpu_power_state(int cpu) 135 135 { 136 - return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 136 + return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 137 137 S5P_CORE_LOCAL_PWR_EN); 138 138 } 139 139 ··· 143 143 */ 144 144 void exynos_cluster_power_down(int cluster) 145 145 { 146 - __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 146 + pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 147 147 } 148 148 149 149 /** ··· 152 152 */ 153 153 void exynos_cluster_power_up(int cluster) 154 154 { 155 - __raw_writel(S5P_CORE_LOCAL_PWR_EN, 156 - EXYNOS_COMMON_CONFIGURATION(cluster)); 155 + pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, 156 + EXYNOS_COMMON_CONFIGURATION(cluster)); 157 157 } 158 158 159 159 /** ··· 163 163 */ 164 164 int exynos_cluster_power_state(int cluster) 165 165 { 166 - return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 166 + return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 167 167 S5P_CORE_LOCAL_PWR_EN); 168 168 } 169 169 170 170 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 171 - S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 172 - (sysram_base_addr + 0x24) : S5P_INFORM0)) 171 + pmu_base_addr + S5P_INFORM7 : \ 172 + (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 173 + (sysram_base_addr + 0x24) : \ 174 + pmu_base_addr + S5P_INFORM0)) 173 175 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 174 - S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 175 - (sysram_base_addr + 0x20) : S5P_INFORM1)) 176 + pmu_base_addr + S5P_INFORM6 : \ 177 + (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 178 + (sysram_base_addr + 0x20) : \ 179 + pmu_base_addr + S5P_INFORM1)) 176 180 177 181 #define S5P_CHECK_AFTR 0xFCBA0D10 178 182 #define S5P_CHECK_SLEEP 0x00000BAD ··· 184 180 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 185 181 static void exynos_set_wakeupmask(long mask) 186 182 { 187 - __raw_writel(mask, S5P_WAKEUP_MASK); 183 + pmu_raw_writel(mask, S5P_WAKEUP_MASK); 188 184 } 189 185 190 186 static void exynos_cpu_set_boot_vector(long flags) ··· 261 257 unsigned int tmp; 262 258 263 259 /* Set wake-up mask registers */ 264 - __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 265 - __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 260 + pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 261 + pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 266 262 267 263 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 268 264 269 265 if (soc_is_exynos5250()) { 270 266 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 271 267 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 272 - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 268 + tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION); 273 269 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 274 - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 270 + pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 275 271 } 276 272 277 273 /* Set value of power down register for sleep mode */ 278 274 279 275 exynos_sys_powerdown_conf(SYS_SLEEP); 280 - __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 276 + pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 281 277 282 278 /* ensure at least INFORM0 has the resume address */ 283 279 284 - __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 280 + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 285 281 } 286 282 287 283 static void exynos_pm_central_suspend(void) ··· 289 285 unsigned long tmp; 290 286 291 287 /* Setting Central Sequence Register for power down mode */ 292 - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 288 + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 293 289 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 294 - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 290 + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 295 291 } 296 292 297 293 static int exynos_pm_suspend(void) ··· 303 299 /* Setting SEQ_OPTION register */ 304 300 305 301 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 306 - __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 302 + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 307 303 308 304 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 309 305 exynos_cpu_save_register(); ··· 321 317 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 322 318 * in this situation. 323 319 */ 324 - tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 320 + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 325 321 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 326 322 tmp |= S5P_CENTRAL_LOWPWR_CFG; 327 - __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 323 + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 328 324 /* clear the wakeup state register */ 329 - __raw_writel(0x0, S5P_WAKEUP_STAT); 325 + pmu_raw_writel(0x0, S5P_WAKEUP_STAT); 330 326 /* No need to perform below restore code */ 331 327 return -1; 332 328 } ··· 344 340 345 341 /* For release retention */ 346 342 347 - __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 348 - __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 349 - __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 350 - __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 351 - __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 352 - __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 353 - __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 343 + pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 344 + pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 345 + pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 346 + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 347 + pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 348 + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 349 + pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 354 350 355 351 if (soc_is_exynos5250()) 356 352 s3c_pm_do_restore(exynos5_sys_save, ··· 364 360 early_wakeup: 365 361 366 362 /* Clear SLEEP mode set in INFORM1 */ 367 - __raw_writel(0x0, S5P_INFORM1); 363 + pmu_raw_writel(0x0, S5P_INFORM1); 368 364 369 365 return; 370 366 } ··· 408 404 s3c_pm_restore_uarts(); 409 405 410 406 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 411 - __raw_readl(S5P_WAKEUP_STAT)); 407 + pmu_raw_readl(S5P_WAKEUP_STAT)); 412 408 413 409 s3c_pm_check_restore(); 414 410 ··· 479 475 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 480 476 481 477 /* All wakeup disable */ 482 - tmp = __raw_readl(S5P_WAKEUP_MASK); 478 + tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 483 479 tmp |= ((0xFF << 8) | (0x1F << 1)); 484 - __raw_writel(tmp, S5P_WAKEUP_MASK); 480 + pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 485 481 486 482 register_syscore_ops(&exynos_pm_syscore_ops); 487 483 suspend_set_ops(&exynos_suspend_ops);

+20 -20

arch/arm/mach-exynos/pmu.c

··· 18 18 static const struct exynos_pmu_conf *exynos_pmu_config; 19 19 20 20 static const struct exynos_pmu_conf exynos4210_pmu_config[] = { 21 - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 21 + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ 22 22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 23 23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 24 24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, ··· 212 212 }; 213 213 214 214 static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 215 - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 215 + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ 216 216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 217 217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 218 218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, ··· 315 315 { PMU_TABLE_END,}, 316 316 }; 317 317 318 - static void __iomem * const exynos5_list_both_cnt_feed[] = { 318 + static unsigned int const exynos5_list_both_cnt_feed[] = { 319 319 EXYNOS5_ARM_CORE0_OPTION, 320 320 EXYNOS5_ARM_CORE1_OPTION, 321 321 EXYNOS5_ARM_COMMON_OPTION, ··· 329 329 EXYNOS5_TOP_PWR_SYSMEM_OPTION, 330 330 }; 331 331 332 - static void __iomem * const exynos5_list_diable_wfi_wfe[] = { 332 + static unsigned int const exynos5_list_diable_wfi_wfe[] = { 333 333 EXYNOS5_ARM_CORE1_OPTION, 334 334 EXYNOS5_FSYS_ARM_OPTION, 335 335 EXYNOS5_ISP_ARM_OPTION, ··· 344 344 * Enable both SC_FEEDBACK and SC_COUNTER 345 345 */ 346 346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) { 347 - tmp = __raw_readl(exynos5_list_both_cnt_feed[i]); 347 + tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]); 348 348 tmp |= (EXYNOS5_USE_SC_FEEDBACK | 349 349 EXYNOS5_USE_SC_COUNTER); 350 - __raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 350 + pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 351 351 } 352 352 353 353 /* 354 354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 355 355 */ 356 - tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); 356 + tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION); 357 357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 358 - __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 358 + pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 359 359 360 360 /* 361 361 * Disable WFI/WFE on XXX_OPTION 362 362 */ 363 363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) { 364 - tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]); 364 + tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]); 365 365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 366 366 EXYNOS5_OPTION_USE_STANDBYWFI); 367 - __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]); 367 + pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]); 368 368 } 369 369 } 370 370 ··· 375 375 if (soc_is_exynos5250()) 376 376 exynos5_init_pmu(); 377 377 378 - for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++) 379 - __raw_writel(exynos_pmu_config[i].val[mode], 380 - exynos_pmu_config[i].reg); 378 + for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++) 379 + pmu_raw_writel(exynos_pmu_config[i].val[mode], 380 + exynos_pmu_config[i].offset); 381 381 382 382 if (soc_is_exynos4412()) { 383 - for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) 384 - __raw_writel(exynos4412_pmu_config[i].val[mode], 385 - exynos4412_pmu_config[i].reg); 383 + for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++) 384 + pmu_raw_writel(exynos4412_pmu_config[i].val[mode], 385 + exynos4412_pmu_config[i].offset); 386 386 } 387 387 } 388 388 ··· 403 403 * When SYS_WDTRESET is set, watchdog timer reset request 404 404 * is ignored by power management unit. 405 405 */ 406 - value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 406 + value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 407 407 value &= ~EXYNOS5_SYS_WDTRESET; 408 - __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 408 + pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 409 409 410 - value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 410 + value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 411 411 value &= ~EXYNOS5_SYS_WDTRESET; 412 - __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 412 + pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 413 413 414 414 exynos_pmu_config = exynos5250_pmu_config; 415 415 pr_info("EXYNOS5250 PMU Initialize\n");

+255 -257

arch/arm/mach-exynos/regs-pmu.h

··· 12 12 #ifndef __ASM_ARCH_REGS_PMU_H 13 13 #define __ASM_ARCH_REGS_PMU_H __FILE__ 14 14 15 - #include <mach/map.h> 16 - 17 - #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 18 - 19 - #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) 15 + #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 20 16 21 17 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 22 18 23 - #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) 19 + #define S5P_CENTRAL_SEQ_OPTION 0x0208 24 20 25 21 #define S5P_USE_STANDBY_WFI0 (1 << 16) 26 22 #define S5P_USE_STANDBY_WFE0 (1 << 24) 27 23 28 - #define EXYNOS_SWRESET S5P_PMUREG(0x0400) 29 - #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) 24 + #define EXYNOS_SWRESET 0x0400 25 + #define EXYNOS5440_SWRESET 0x00C4 30 26 31 - #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 32 - #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 33 - #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 27 + #define S5P_WAKEUP_STAT 0x0600 28 + #define S5P_EINT_WAKEUP_MASK 0x0604 29 + #define S5P_WAKEUP_MASK 0x0608 34 30 35 - #define S5P_INFORM0 S5P_PMUREG(0x0800) 36 - #define S5P_INFORM1 S5P_PMUREG(0x0804) 37 - #define S5P_INFORM5 S5P_PMUREG(0x0814) 38 - #define S5P_INFORM6 S5P_PMUREG(0x0818) 39 - #define S5P_INFORM7 S5P_PMUREG(0x081C) 40 - #define S5P_PMU_SPARE3 S5P_PMUREG(0x090C) 31 + #define S5P_INFORM0 0x0800 32 + #define S5P_INFORM1 0x0804 33 + #define S5P_INFORM5 0x0814 34 + #define S5P_INFORM6 0x0818 35 + #define S5P_INFORM7 0x081C 36 + #define S5P_PMU_SPARE3 0x090C 41 37 42 - #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) 43 - #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) 44 - #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) 45 - #define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) 46 - #define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) 47 - #define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) 48 - #define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) 49 - #define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) 50 - #define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) 51 - #define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) 52 - #define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) 53 - #define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) 54 - #define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) 55 - #define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) 56 - #define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) 57 - #define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) 58 - #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) 59 - #define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) 60 - #define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) 61 - #define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) 62 - #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 63 - #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 64 - #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 65 - #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 66 - #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 67 - #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 68 - #define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) 69 - #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 70 - #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 71 - #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 72 - #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 73 - #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 74 - #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 75 - #define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) 76 - #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 77 - #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 78 - #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 79 - #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 80 - #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 81 - #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 82 - #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 83 - #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 84 - #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 85 - #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 86 - #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 87 - #define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) 88 - #define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) 89 - #define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) 90 - #define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) 91 - #define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) 92 - #define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) 93 - #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) 94 - #define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) 95 - #define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) 96 - #define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) 97 - #define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) 98 - #define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) 99 - #define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) 100 - #define S5P_TV_LOWPWR S5P_PMUREG(0x1384) 101 - #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 102 - #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 103 - #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 104 - #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 105 - #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 106 - #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 38 + #define S5P_ARM_CORE0_LOWPWR 0x1000 39 + #define S5P_DIS_IRQ_CORE0 0x1004 40 + #define S5P_DIS_IRQ_CENTRAL0 0x1008 41 + #define S5P_ARM_CORE1_LOWPWR 0x1010 42 + #define S5P_DIS_IRQ_CORE1 0x1014 43 + #define S5P_DIS_IRQ_CENTRAL1 0x1018 44 + #define S5P_ARM_COMMON_LOWPWR 0x1080 45 + #define S5P_L2_0_LOWPWR 0x10C0 46 + #define S5P_L2_1_LOWPWR 0x10C4 47 + #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 48 + #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 49 + #define S5P_CMU_RESET_LOWPWR 0x110C 50 + #define S5P_APLL_SYSCLK_LOWPWR 0x1120 51 + #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 52 + #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 53 + #define S5P_EPLL_SYSCLK_LOWPWR 0x112C 54 + #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 55 + #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C 56 + #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 57 + #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 58 + #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 59 + #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C 60 + #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 61 + #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 62 + #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C 63 + #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 64 + #define S5P_CMU_RESET_TV_LOWPWR 0x1164 65 + #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 66 + #define S5P_CMU_RESET_G3D_LOWPWR 0x116C 67 + #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 68 + #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 69 + #define S5P_CMU_RESET_GPS_LOWPWR 0x117C 70 + #define S5P_TOP_BUS_LOWPWR 0x1180 71 + #define S5P_TOP_RETENTION_LOWPWR 0x1184 72 + #define S5P_TOP_PWR_LOWPWR 0x1188 73 + #define S5P_LOGIC_RESET_LOWPWR 0x11A0 74 + #define S5P_ONENAND_MEM_LOWPWR 0x11C0 75 + #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 76 + #define S5P_USBOTG_MEM_LOWPWR 0x11CC 77 + #define S5P_HSMMC_MEM_LOWPWR 0x11D0 78 + #define S5P_CSSYS_MEM_LOWPWR 0x11D4 79 + #define S5P_SECSS_MEM_LOWPWR 0x11D8 80 + #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 81 + #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 82 + #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 83 + #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 84 + #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 85 + #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C 86 + #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 87 + #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 88 + #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 89 + #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 90 + #define S5P_XUSBXTI_LOWPWR 0x1280 91 + #define S5P_XXTI_LOWPWR 0x1284 92 + #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 93 + #define S5P_GPIO_MODE_LOWPWR 0x1300 94 + #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 95 + #define S5P_CAM_LOWPWR 0x1380 96 + #define S5P_TV_LOWPWR 0x1384 97 + #define S5P_MFC_LOWPWR 0x1388 98 + #define S5P_G3D_LOWPWR 0x138C 99 + #define S5P_LCD0_LOWPWR 0x1390 100 + #define S5P_MAUDIO_LOWPWR 0x1398 101 + #define S5P_GPS_LOWPWR 0x139C 102 + #define S5P_GPS_ALIVE_LOWPWR 0x13A0 107 103 108 - #define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) 104 + #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 109 105 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 110 106 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 111 107 #define EXYNOS_ARM_CORE_STATUS(_nr) \ 112 108 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 113 109 114 - #define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500) 110 + #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 115 111 #define EXYNOS_COMMON_CONFIGURATION(_nr) \ 116 112 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 117 113 #define EXYNOS_COMMON_STATUS(_nr) \ 118 114 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 115 + #define EXYNOS_COMMON_OPTION(_nr) \ 116 + (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 119 117 120 - #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) 121 - #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) 122 - #define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) 123 - #define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) 124 - #define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) 125 - #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) 126 - #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) 118 + #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 119 + #define S5P_PAD_RET_GPIO_OPTION 0x3108 120 + #define S5P_PAD_RET_UART_OPTION 0x3128 121 + #define S5P_PAD_RET_MMCA_OPTION 0x3148 122 + #define S5P_PAD_RET_MMCB_OPTION 0x3168 123 + #define S5P_PAD_RET_EBIA_OPTION 0x3188 124 + #define S5P_PAD_RET_EBIB_OPTION 0x31A8 127 125 128 126 #define S5P_CORE_LOCAL_PWR_EN 0x3 129 127 130 128 /* Only for EXYNOS4210 */ 131 - #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) 132 - #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) 133 - #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) 134 - #define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) 135 - #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) 136 - #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) 129 + #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 130 + #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 131 + #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 132 + #define S5P_PCIE_MEM_LOWPWR 0x11E0 133 + #define S5P_SATA_MEM_LOWPWR 0x11E4 134 + #define S5P_LCD1_LOWPWR 0x1394 137 135 138 136 /* Only for EXYNOS4x12 */ 139 - #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 140 - #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 141 - #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 142 - #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) 143 - #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) 144 - #define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) 145 - #define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) 146 - #define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) 147 - #define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) 148 - #define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) 149 - #define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) 150 - #define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) 151 - #define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) 152 - #define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) 153 - #define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) 154 - #define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) 155 - #define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) 156 - #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) 157 - #define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) 158 - #define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) 159 - #define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) 160 - #define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) 161 - #define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) 162 - #define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) 163 - #define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) 164 - #define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) 165 - #define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) 166 - #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) 137 + #define S5P_ISP_ARM_LOWPWR 0x1050 138 + #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 139 + #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 140 + #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 141 + #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 142 + #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C 143 + #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 144 + #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 145 + #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 146 + #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 147 + #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 148 + #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 149 + #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 150 + #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 151 + #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 152 + #define S5P_HSI_MEM_LOWPWR 0x11C4 153 + #define S5P_ROTATOR_MEM_LOWPWR 0x11DC 154 + #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C 155 + #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 156 + #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 157 + #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 158 + #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 159 + #define S5P_ISP_LOWPWR 0x1394 160 + #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 161 + #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 162 + #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 163 + #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC 164 + #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 167 165 168 - #define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) 169 - #define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) 170 - #define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) 171 - #define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) 172 - #define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) 173 - #define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) 174 - #define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) 175 - #define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) 176 - #define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 177 - #define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 166 + #define S5P_ARM_L2_0_OPTION 0x2608 167 + #define S5P_ARM_L2_1_OPTION 0x2628 168 + #define S5P_ONENAND_MEM_OPTION 0x2E08 169 + #define S5P_HSI_MEM_OPTION 0x2E28 170 + #define S5P_G2D_ACP_MEM_OPTION 0x2E48 171 + #define S5P_USBOTG_MEM_OPTION 0x2E68 172 + #define S5P_HSMMC_MEM_OPTION 0x2E88 173 + #define S5P_CSSYS_MEM_OPTION 0x2EA8 174 + #define S5P_SECSS_MEM_OPTION 0x2EC8 175 + #define S5P_ROTATOR_MEM_OPTION 0x2F48 178 176 179 177 /* Only for EXYNOS4412 */ 180 - #define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) 181 - #define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) 182 - #define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) 183 - #define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) 184 - #define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) 185 - #define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) 178 + #define S5P_ARM_CORE2_LOWPWR 0x1020 179 + #define S5P_DIS_IRQ_CORE2 0x1024 180 + #define S5P_DIS_IRQ_CENTRAL2 0x1028 181 + #define S5P_ARM_CORE3_LOWPWR 0x1030 182 + #define S5P_DIS_IRQ_CORE3 0x1034 183 + #define S5P_DIS_IRQ_CENTRAL3 0x1038 186 184 187 185 /* For EXYNOS5 */ 188 186 189 - #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) 190 - #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) 187 + #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 188 + #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C 191 189 192 190 #define EXYNOS5_SYS_WDTRESET (1 << 20) 193 191 194 - #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) 195 - #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) 196 - #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) 197 - #define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010) 198 - #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014) 199 - #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018) 200 - #define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040) 201 - #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048) 202 - #define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050) 203 - #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054) 204 - #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058) 205 - #define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080) 206 - #define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0) 207 - #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100) 208 - #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104) 209 - #define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C) 210 - #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120) 211 - #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124) 212 - #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C) 213 - #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130) 214 - #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134) 215 - #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138) 216 - #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140) 217 - #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144) 218 - #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148) 219 - #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C) 220 - #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150) 221 - #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154) 222 - #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164) 223 - #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170) 224 - #define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180) 225 - #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184) 226 - #define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188) 227 - #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190) 228 - #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194) 229 - #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198) 230 - #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0) 231 - #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4) 232 - #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0) 233 - #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4) 234 - #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0) 235 - #define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8) 236 - #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC) 237 - #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0) 238 - #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4) 239 - #define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8) 240 - #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC) 241 - #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0) 242 - #define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4) 243 - #define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8) 244 - #define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC) 245 - #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4) 246 - #define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC) 247 - #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200) 248 - #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204) 249 - #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208) 250 - #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) 251 - #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224) 252 - #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228) 253 - #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C) 254 - #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230) 255 - #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234) 256 - #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238) 257 - #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C) 258 - #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240) 259 - #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250) 260 - #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260) 261 - #define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280) 262 - #define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284) 263 - #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0) 264 - #define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300) 265 - #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320) 266 - #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340) 267 - #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344) 268 - #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348) 269 - #define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400) 270 - #define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404) 271 - #define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408) 272 - #define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C) 273 - #define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) 274 - #define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418) 275 - #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480) 276 - #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484) 277 - #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488) 278 - #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C) 279 - #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494) 280 - #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498) 281 - #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0) 282 - #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4) 283 - #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8) 284 - #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC) 285 - #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4) 286 - #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8) 287 - #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580) 288 - #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584) 289 - #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588) 290 - #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C) 291 - #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594) 292 - #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598) 192 + #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 193 + #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 194 + #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 195 + #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 196 + #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 197 + #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 198 + #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 199 + #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 200 + #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 201 + #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 202 + #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 203 + #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 204 + #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 205 + #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 206 + #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 207 + #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C 208 + #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 209 + #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 210 + #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C 211 + #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 212 + #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 213 + #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 214 + #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 215 + #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 216 + #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 217 + #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C 218 + #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 219 + #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 220 + #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 221 + #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 222 + #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 223 + #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 224 + #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 225 + #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 226 + #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 227 + #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 228 + #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 229 + #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 230 + #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 231 + #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 232 + #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 233 + #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 234 + #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC 235 + #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 236 + #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 237 + #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 238 + #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC 239 + #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 240 + #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 241 + #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 242 + #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC 243 + #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 244 + #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC 245 + #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 246 + #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 247 + #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208 248 + #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 249 + #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 250 + #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 251 + #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C 252 + #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 253 + #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 254 + #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 255 + #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C 256 + #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 257 + #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 258 + #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 259 + #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 260 + #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 261 + #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 262 + #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 263 + #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 264 + #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 265 + #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 266 + #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 267 + #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 268 + #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 269 + #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 270 + #define EXYNOS5_G3D_SYS_PWR_REG 0x140C 271 + #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 272 + #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 273 + #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 274 + #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 275 + #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 276 + #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C 277 + #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 278 + #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 279 + #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 280 + #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 281 + #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 282 + #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC 283 + #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 284 + #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 285 + #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 286 + #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 287 + #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 288 + #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C 289 + #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 290 + #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 293 291 294 - #define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008) 295 - #define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088) 296 - #define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) 297 - #define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) 298 - #define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) 299 - #define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) 300 - #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) 301 - #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) 302 - #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) 303 - #define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) 304 - #define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) 305 - #define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) 306 - #define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) 307 - #define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) 308 - #define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) 292 + #define EXYNOS5_ARM_CORE0_OPTION 0x2008 293 + #define EXYNOS5_ARM_CORE1_OPTION 0x2088 294 + #define EXYNOS5_FSYS_ARM_OPTION 0x2208 295 + #define EXYNOS5_ISP_ARM_OPTION 0x2288 296 + #define EXYNOS5_ARM_COMMON_OPTION 0x2408 297 + #define EXYNOS5_ARM_L2_OPTION 0x2608 298 + #define EXYNOS5_TOP_PWR_OPTION 0x2C48 299 + #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 300 + #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 301 + #define EXYNOS5_GSCL_OPTION 0x4008 302 + #define EXYNOS5_ISP_OPTION 0x4028 303 + #define EXYNOS5_MFC_OPTION 0x4048 304 + #define EXYNOS5_G3D_OPTION 0x4068 305 + #define EXYNOS5_DISP1_OPTION 0x40A8 306 + #define EXYNOS5_MAU_OPTION 0x40C8 309 307 310 308 #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 311 309 #define EXYNOS5_USE_SC_COUNTER (1 << 0)

-1

arch/arm/plat-samsung/include/plat/map-s5p.h

··· 15 15 16 16 #define S5P_VA_CHIPID S3C_ADDR(0x02000000) 17 17 #define S5P_VA_CMU S3C_ADDR(0x02100000) 18 - #define S5P_VA_PMU S3C_ADDR(0x02180000) 19 18 #define S5P_VA_GPIO S3C_ADDR(0x02200000) 20 19 #define S5P_VA_GPIO1 S5P_VA_GPIO 21 20 #define S5P_VA_GPIO2 S3C_ADDR(0x02240000)