Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller

Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by
Bjorn Andersson
8df29649 48d2c6de

+118 -3
+8 -3
Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
··· 8 8 9 9 maintainers: 10 10 - Konrad Dybcio <konradybcio@kernel.org> 11 + - Taniya Das <quic_tdas@quicinc.com> 11 12 12 13 description: | 13 14 Qualcomm camera clock control module provides the clocks, resets and power 14 - domains on SM6350. 15 + domains on SM6350 and QCS615 SoC. 15 16 16 - See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h 17 + See also: 18 + include/dt-bindings/clock/qcom,qcs615-camcc.h 19 + include/dt-bindings/clock/qcom,sm6350-camcc.h 17 20 18 21 properties: 19 22 compatible: 20 - const: qcom,sm6350-camcc 23 + enum: 24 + - qcom,qcs615-camcc 25 + - qcom,sm6350-camcc 21 26 22 27 clocks: 23 28 items:
+110
include/dt-bindings/clock/qcom,qcs615-camcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H 7 + #define _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H 8 + 9 + /* CAM_CC clocks */ 10 + #define CAM_CC_BPS_AHB_CLK 0 11 + #define CAM_CC_BPS_AREG_CLK 1 12 + #define CAM_CC_BPS_AXI_CLK 2 13 + #define CAM_CC_BPS_CLK 3 14 + #define CAM_CC_BPS_CLK_SRC 4 15 + #define CAM_CC_CAMNOC_ATB_CLK 5 16 + #define CAM_CC_CAMNOC_AXI_CLK 6 17 + #define CAM_CC_CCI_CLK 7 18 + #define CAM_CC_CCI_CLK_SRC 8 19 + #define CAM_CC_CORE_AHB_CLK 9 20 + #define CAM_CC_CPAS_AHB_CLK 10 21 + #define CAM_CC_CPHY_RX_CLK_SRC 11 22 + #define CAM_CC_CSI0PHYTIMER_CLK 12 23 + #define CAM_CC_CSI0PHYTIMER_CLK_SRC 13 24 + #define CAM_CC_CSI1PHYTIMER_CLK 14 25 + #define CAM_CC_CSI1PHYTIMER_CLK_SRC 15 26 + #define CAM_CC_CSI2PHYTIMER_CLK 16 27 + #define CAM_CC_CSI2PHYTIMER_CLK_SRC 17 28 + #define CAM_CC_CSIPHY0_CLK 18 29 + #define CAM_CC_CSIPHY1_CLK 19 30 + #define CAM_CC_CSIPHY2_CLK 20 31 + #define CAM_CC_FAST_AHB_CLK_SRC 21 32 + #define CAM_CC_ICP_ATB_CLK 22 33 + #define CAM_CC_ICP_CLK 23 34 + #define CAM_CC_ICP_CLK_SRC 24 35 + #define CAM_CC_ICP_CTI_CLK 25 36 + #define CAM_CC_ICP_TS_CLK 26 37 + #define CAM_CC_IFE_0_AXI_CLK 27 38 + #define CAM_CC_IFE_0_CLK 28 39 + #define CAM_CC_IFE_0_CLK_SRC 29 40 + #define CAM_CC_IFE_0_CPHY_RX_CLK 30 41 + #define CAM_CC_IFE_0_CSID_CLK 31 42 + #define CAM_CC_IFE_0_CSID_CLK_SRC 32 43 + #define CAM_CC_IFE_0_DSP_CLK 33 44 + #define CAM_CC_IFE_1_AXI_CLK 34 45 + #define CAM_CC_IFE_1_CLK 35 46 + #define CAM_CC_IFE_1_CLK_SRC 36 47 + #define CAM_CC_IFE_1_CPHY_RX_CLK 37 48 + #define CAM_CC_IFE_1_CSID_CLK 38 49 + #define CAM_CC_IFE_1_CSID_CLK_SRC 39 50 + #define CAM_CC_IFE_1_DSP_CLK 40 51 + #define CAM_CC_IFE_LITE_CLK 41 52 + #define CAM_CC_IFE_LITE_CLK_SRC 42 53 + #define CAM_CC_IFE_LITE_CPHY_RX_CLK 43 54 + #define CAM_CC_IFE_LITE_CSID_CLK 44 55 + #define CAM_CC_IFE_LITE_CSID_CLK_SRC 45 56 + #define CAM_CC_IPE_0_AHB_CLK 46 57 + #define CAM_CC_IPE_0_AREG_CLK 47 58 + #define CAM_CC_IPE_0_AXI_CLK 48 59 + #define CAM_CC_IPE_0_CLK 49 60 + #define CAM_CC_IPE_0_CLK_SRC 50 61 + #define CAM_CC_JPEG_CLK 51 62 + #define CAM_CC_JPEG_CLK_SRC 52 63 + #define CAM_CC_LRME_CLK 53 64 + #define CAM_CC_LRME_CLK_SRC 54 65 + #define CAM_CC_MCLK0_CLK 55 66 + #define CAM_CC_MCLK0_CLK_SRC 56 67 + #define CAM_CC_MCLK1_CLK 57 68 + #define CAM_CC_MCLK1_CLK_SRC 58 69 + #define CAM_CC_MCLK2_CLK 59 70 + #define CAM_CC_MCLK2_CLK_SRC 60 71 + #define CAM_CC_MCLK3_CLK 61 72 + #define CAM_CC_MCLK3_CLK_SRC 62 73 + #define CAM_CC_PLL0 63 74 + #define CAM_CC_PLL1 64 75 + #define CAM_CC_PLL2 65 76 + #define CAM_CC_PLL2_OUT_AUX2 66 77 + #define CAM_CC_PLL3 67 78 + #define CAM_CC_SLOW_AHB_CLK_SRC 68 79 + #define CAM_CC_SOC_AHB_CLK 69 80 + #define CAM_CC_SYS_TMR_CLK 70 81 + 82 + /* CAM_CC power domains */ 83 + #define BPS_GDSC 0 84 + #define IFE_0_GDSC 1 85 + #define IFE_1_GDSC 2 86 + #define IPE_0_GDSC 3 87 + #define TITAN_TOP_GDSC 4 88 + 89 + /* CAM_CC resets */ 90 + #define CAM_CC_BPS_BCR 0 91 + #define CAM_CC_CAMNOC_BCR 1 92 + #define CAM_CC_CCI_BCR 2 93 + #define CAM_CC_CPAS_BCR 3 94 + #define CAM_CC_CSI0PHY_BCR 4 95 + #define CAM_CC_CSI1PHY_BCR 5 96 + #define CAM_CC_CSI2PHY_BCR 6 97 + #define CAM_CC_ICP_BCR 7 98 + #define CAM_CC_IFE_0_BCR 8 99 + #define CAM_CC_IFE_1_BCR 9 100 + #define CAM_CC_IFE_LITE_BCR 10 101 + #define CAM_CC_IPE_0_BCR 11 102 + #define CAM_CC_JPEG_BCR 12 103 + #define CAM_CC_LRME_BCR 13 104 + #define CAM_CC_MCLK0_BCR 14 105 + #define CAM_CC_MCLK1_BCR 15 106 + #define CAM_CC_MCLK2_BCR 16 107 + #define CAM_CC_MCLK3_BCR 17 108 + #define CAM_CC_TITAN_TOP_BCR 18 109 + 110 + #endif