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media: dt-bindings: Add qcom,sa8775p-camss compatible
Add the compatible string "qcom,sa8775p-camss" to support the
Camera Subsystem (CAMSS) on the Qualcomm lemans platform.
The Lemans(SA8775P) platform provides:
- 2 x VFE (version 690), each with 3 RDI
- 5 x VFE Lite (version 690), each with 6 RDI
- 2 x CSID (version 690)
- 5 x CSID Lite (version 690)
- 4 x CSIPHY (version 690)
- 3 x TPG
Lemans is the first Qualcomm SoC to introduce a CSIPHY-based
Test Pattern Generator (TPG).
Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
authored by
Vikram Sharma
and committed by
Mauro Carvalho Chehab
8dd22e90
a3dce6e3
+361
+361
Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
+361
Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SA8775P CAMSS ISP
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maintainers:
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- Vikram Sharma <quic_vikramsa@quicinc.com>
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description:
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sa8775p-camss
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reg:
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maxItems: 22
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reg-names:
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items:
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- const: csid_wrapper
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- const: csid0
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- const: csid1
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- const: csid_lite0
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- const: csid_lite1
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- const: csid_lite2
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- const: csid_lite3
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- const: csid_lite4
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: tpg0
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- const: tpg1
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- const: tpg2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite0
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- const: vfe_lite1
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- const: vfe_lite2
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- const: vfe_lite3
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- const: vfe_lite4
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+
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clocks:
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maxItems: 28
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clock-names:
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items:
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- const: camnoc_axi
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- const: core_ahb
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- const: cpas_ahb
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- const: cpas_fast_ahb_clk
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- const: cpas_vfe_lite
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- const: cpas_vfe0
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- const: cpas_vfe1
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- const: csid
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: csiphy3
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- const: csiphy3_timer
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- const: csiphy_rx
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- const: gcc_axi_hf
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- const: gcc_axi_sf
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- const: icp_ahb
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- const: vfe0
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- const: vfe0_fast_ahb
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- const: vfe1
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- const: vfe1_fast_ahb
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- const: vfe_lite
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- const: vfe_lite_ahb
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- const: vfe_lite_cphy_rx
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- const: vfe_lite_csid
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+
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interrupts:
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maxItems: 21
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid_lite0
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- const: csid_lite1
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- const: csid_lite2
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- const: csid_lite3
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- const: csid_lite4
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: tpg0
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- const: tpg1
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- const: tpg2
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- const: vfe0
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- const: vfe1
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- const: vfe_lite0
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- const: vfe_lite1
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- const: vfe_lite2
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- const: vfe_lite3
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- const: vfe_lite4
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+
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interconnects:
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maxItems: 2
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+
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interconnect-names:
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items:
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- const: ahb
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- const: hf_0
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+
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iommus:
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maxItems: 1
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power-domains:
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items:
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- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: top
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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vdda-pll-supply:
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description:
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Phandle to 1.8V regulator supply to PHY refclk pll block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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patternProperties:
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"^port@[0-3]+$":
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data on CSIPHY 0-3.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- interconnects
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- interconnect-names
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- iommus
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- power-domains
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- power-domain-names
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- vdda-phy-supply
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- vdda-pll-supply
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- ports
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+
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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isp@ac78000 {
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compatible = "qcom,sa8775p-camss";
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reg = <0x0 0xac78000 0x0 0x1000>,
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<0x0 0xac7a000 0x0 0x0f00>,
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<0x0 0xac7c000 0x0 0x0f00>,
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<0x0 0xac84000 0x0 0x0f00>,
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<0x0 0xac88000 0x0 0x0f00>,
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<0x0 0xac8c000 0x0 0x0f00>,
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<0x0 0xac90000 0x0 0x0f00>,
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<0x0 0xac94000 0x0 0x0f00>,
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<0x0 0xac9c000 0x0 0x2000>,
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<0x0 0xac9e000 0x0 0x2000>,
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<0x0 0xaca0000 0x0 0x2000>,
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<0x0 0xaca2000 0x0 0x2000>,
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<0x0 0xacac000 0x0 0x0400>,
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<0x0 0xacad000 0x0 0x0400>,
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<0x0 0xacae000 0x0 0x0400>,
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<0x0 0xac4d000 0x0 0xd000>,
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<0x0 0xac5a000 0x0 0xd000>,
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<0x0 0xac85000 0x0 0x0d00>,
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<0x0 0xac89000 0x0 0x0d00>,
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<0x0 0xac8d000 0x0 0x0d00>,
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<0x0 0xac91000 0x0 0x0d00>,
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<0x0 0xac95000 0x0 0x0d00>;
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reg-names = "csid_wrapper",
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"csid0",
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"csid1",
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"csid_lite0",
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"csid_lite1",
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"csid_lite2",
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"csid_lite3",
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"csid_lite4",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"tpg0",
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"tpg1",
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"tpg2",
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"vfe0",
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"vfe1",
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"vfe_lite0",
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"vfe_lite1",
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"vfe_lite2",
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"vfe_lite3",
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"vfe_lite4";
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+
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CORE_AHB_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
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<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
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<&camcc CAM_CC_CPAS_IFE_0_CLK>,
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<&camcc CAM_CC_CPAS_IFE_1_CLK>,
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<&camcc CAM_CC_CSID_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
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<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
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<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&gcc GCC_CAMERA_SF_AXI_CLK>,
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<&camcc CAM_CC_ICP_AHB_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_LITE_CLK>,
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<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
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clock-names = "camnoc_axi",
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"core_ahb",
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"cpas_ahb",
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"cpas_fast_ahb_clk",
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"cpas_vfe_lite",
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"cpas_vfe0",
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"cpas_vfe1",
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"csid",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"csiphy3",
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"csiphy3_timer",
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"csiphy_rx",
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"gcc_axi_hf",
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"gcc_axi_sf",
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"icp_ahb",
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"vfe0",
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"vfe0_fast_ahb",
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"vfe1",
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"vfe1_fast_ahb",
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"vfe_lite",
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"vfe_lite_ahb",
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"vfe_lite_cphy_rx",
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"vfe_lite_csid";
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interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csid0",
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"csid1",
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"csid_lite0",
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"csid_lite1",
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"csid_lite2",
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"csid_lite3",
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"csid_lite4",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"tpg0",
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"tpg1",
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"tpg2",
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"vfe0",
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"vfe1",
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"vfe_lite0",
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"vfe_lite1",
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"vfe_lite2",
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"vfe_lite3",
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"vfe_lite4";
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "ahb",
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"hf_0";
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iommus = <&apps_smmu 0x3400 0x20>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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power-domain-names = "top";
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vdda-phy-supply = <&vreg_l4a_0p88>;
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vdda-pll-supply = <&vreg_l1c_1p2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};