ASoC: mediatek: Add support for MT8188 SoC

+208

Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek AFE PCM controller for mt8188 8 + 9 + maintainers: 10 + - Trevor Wu <trevor.wu@mediatek.com> 11 + 12 + properties: 13 + compatible: 14 + const: mediatek,mt8188-afe 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + interrupts: 20 + maxItems: 1 21 + 22 + resets: 23 + maxItems: 1 24 + 25 + reset-names: 26 + const: audiosys 27 + 28 + mediatek,topckgen: 29 + $ref: /schemas/types.yaml#/definitions/phandle 30 + description: The phandle of the mediatek topckgen controller 31 + 32 + power-domains: 33 + maxItems: 1 34 + 35 + clocks: 36 + items: 37 + - description: 26M clock 38 + - description: audio pll1 clock 39 + - description: audio pll2 clock 40 + - description: clock divider for i2si1_mck 41 + - description: clock divider for i2si2_mck 42 + - description: clock divider for i2so1_mck 43 + - description: clock divider for i2so2_mck 44 + - description: clock divider for dptx_mck 45 + - description: a1sys hoping clock 46 + - description: audio intbus clock 47 + - description: audio hires clock 48 + - description: audio local bus clock 49 + - description: mux for dptx_mck 50 + - description: mux for i2so1_mck 51 + - description: mux for i2so2_mck 52 + - description: mux for i2si1_mck 53 + - description: mux for i2si2_mck 54 + - description: audio 26m clock 55 + 56 + clock-names: 57 + items: 58 + - const: clk26m 59 + - const: apll1 60 + - const: apll2 61 + - const: apll12_div0 62 + - const: apll12_div1 63 + - const: apll12_div2 64 + - const: apll12_div3 65 + - const: apll12_div9 66 + - const: a1sys_hp_sel 67 + - const: aud_intbus_sel 68 + - const: audio_h_sel 69 + - const: audio_local_bus_sel 70 + - const: dptx_m_sel 71 + - const: i2so1_m_sel 72 + - const: i2so2_m_sel 73 + - const: i2si1_m_sel 74 + - const: i2si2_m_sel 75 + - const: adsp_audio_26m 76 + 77 + mediatek,etdm-in1-cowork-source: 78 + $ref: /schemas/types.yaml#/definitions/uint32 79 + description: 80 + etdm modules can share the same external clock pin. Specify 81 + which etdm clock source is required by this etdm in module. 82 + enum: 83 + - 1 # etdm2_in 84 + - 2 # etdm1_out 85 + - 3 # etdm2_out 86 + 87 + mediatek,etdm-in2-cowork-source: 88 + $ref: /schemas/types.yaml#/definitions/uint32 89 + description: 90 + etdm modules can share the same external clock pin. Specify 91 + which etdm clock source is required by this etdm in module. 92 + enum: 93 + - 0 # etdm1_in 94 + - 2 # etdm1_out 95 + - 3 # etdm2_out 96 + 97 + mediatek,etdm-out1-cowork-source: 98 + $ref: /schemas/types.yaml#/definitions/uint32 99 + description: 100 + etdm modules can share the same external clock pin. Specify 101 + which etdm clock source is required by this etdm out module. 102 + enum: 103 + - 0 # etdm1_in 104 + - 1 # etdm2_in 105 + - 3 # etdm2_out 106 + 107 + mediatek,etdm-out2-cowork-source: 108 + $ref: /schemas/types.yaml#/definitions/uint32 109 + description: 110 + etdm modules can share the same external clock pin. Specify 111 + which etdm clock source is required by this etdm out module. 112 + enum: 113 + - 0 # etdm1_in 114 + - 1 # etdm2_in 115 + - 2 # etdm1_out 116 + 117 + patternProperties: 118 + "^mediatek,etdm-in[1-2]-chn-disabled$": 119 + $ref: /schemas/types.yaml#/definitions/uint8-array 120 + minItems: 1 121 + maxItems: 16 122 + description: 123 + This is a list of channel IDs which should be disabled. 124 + By default, all data received from ETDM pins will be outputed to 125 + memory. etdm in supports disable_out in direct mode(w/o interconn), 126 + so user can disable the specified channels by the property. 127 + uniqueItems: true 128 + items: 129 + minimum: 0 130 + maximum: 15 131 + 132 + "^mediatek,etdm-in[1-2]-multi-pin-mode$": 133 + type: boolean 134 + description: if present, the etdm data mode is I2S. 135 + 136 + "^mediatek,etdm-out[1-3]-multi-pin-mode$": 137 + type: boolean 138 + description: if present, the etdm data mode is I2S. 139 + 140 + required: 141 + - compatible 142 + - reg 143 + - interrupts 144 + - resets 145 + - reset-names 146 + - mediatek,topckgen 147 + - power-domains 148 + - clocks 149 + - clock-names 150 + 151 + additionalProperties: false 152 + 153 + examples: 154 + - | 155 + #include <dt-bindings/interrupt-controller/arm-gic.h> 156 + #include <dt-bindings/interrupt-controller/irq.h> 157 + 158 + afe@10b10000 { 159 + compatible = "mediatek,mt8188-afe"; 160 + reg = <0x10b10000 0x10000>; 161 + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 162 + resets = <&watchdog 14>; 163 + reset-names = "audiosys"; 164 + mediatek,topckgen = <&topckgen>; 165 + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO 166 + mediatek,etdm-in2-cowork-source = <2>; 167 + mediatek,etdm-out2-cowork-source = <0>; 168 + mediatek,etdm-in1-multi-pin-mode; 169 + mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>; 170 + clocks = <&clk26m>, 171 + <&apmixedsys 9>, //CLK_APMIXED_APLL1 172 + <&apmixedsys 10>, //CLK_APMIXED_APLL2 173 + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 174 + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 175 + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 176 + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 177 + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 178 + <&topckgen 83>, //CLK_TOP_A1SYS_HP 179 + <&topckgen 31>, //CLK_TOP_AUD_INTBUS 180 + <&topckgen 32>, //CLK_TOP_AUDIO_H 181 + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS 182 + <&topckgen 81>, //CLK_TOP_DPTX 183 + <&topckgen 77>, //CLK_TOP_I2SO1 184 + <&topckgen 78>, //CLK_TOP_I2SO2 185 + <&topckgen 79>, //CLK_TOP_I2SI1 186 + <&topckgen 80>, //CLK_TOP_I2SI2 187 + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M 188 + clock-names = "clk26m", 189 + "apll1", 190 + "apll2", 191 + "apll12_div0", 192 + "apll12_div1", 193 + "apll12_div2", 194 + "apll12_div3", 195 + "apll12_div9", 196 + "a1sys_hp_sel", 197 + "aud_intbus_sel", 198 + "audio_h_sel", 199 + "audio_local_bus_sel", 200 + "dptx_m_sel", 201 + "i2so1_m_sel", 202 + "i2so2_m_sel", 203 + "i2si1_m_sel", 204 + "i2si2_m_sel", 205 + "adsp_audio_26m"; 206 + }; 207 + 208 + ...

+97

Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/sound/mediatek,mt8188-mt6359.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek MT8188 ASoC sound card 8 + 9 + maintainers: 10 + - Trevor Wu <trevor.wu@mediatek.com> 11 + 12 + properties: 13 + compatible: 14 + const: mediatek,mt8188-mt6359-evb 15 + 16 + model: 17 + $ref: /schemas/types.yaml#/definitions/string 18 + description: User specified audio sound card name 19 + 20 + audio-routing: 21 + $ref: /schemas/types.yaml#/definitions/non-unique-string-array 22 + description: 23 + A list of the connections between audio components. Each entry is a 24 + sink/source pair of strings. Valid names could be the input or output 25 + widgets of audio components, power supplies, MicBias of codec and the 26 + software switch. 27 + 28 + mediatek,platform: 29 + $ref: /schemas/types.yaml#/definitions/phandle 30 + description: The phandle of MT8188 ASoC platform. 31 + 32 + patternProperties: 33 + "^dai-link-[0-9]+$": 34 + type: object 35 + description: 36 + Container for dai-link level properties and CODEC sub-nodes. 37 + 38 + properties: 39 + link-name: 40 + description: 41 + This property corresponds to the name of the BE dai-link to which 42 + we are going to update parameters in this node. 43 + items: 44 + enum: 45 + - ADDA_BE 46 + - DPTX_BE 47 + - ETDM1_IN_BE 48 + - ETDM2_IN_BE 49 + - ETDM1_OUT_BE 50 + - ETDM2_OUT_BE 51 + - ETDM3_OUT_BE 52 + - PCM1_BE 53 + 54 + codec: 55 + description: Holds subnode which indicates codec dai. 56 + type: object 57 + additionalProperties: false 58 + properties: 59 + sound-dai: 60 + minItems: 1 61 + maxItems: 2 62 + required: 63 + - sound-dai 64 + 65 + additionalProperties: false 66 + 67 + required: 68 + - link-name 69 + - codec 70 + 71 + additionalProperties: false 72 + 73 + required: 74 + - compatible 75 + - mediatek,platform 76 + 77 + examples: 78 + - | 79 + sound { 80 + compatible = "mediatek,mt8188-mt6359-evb"; 81 + mediatek,platform = <&afe>; 82 + pinctrl-names = "default"; 83 + pinctrl-0 = <&aud_pins_default>; 84 + audio-routing = 85 + "Headphone", "Headphone L", 86 + "Headphone", "Headphone R", 87 + "AIN1", "Headset Mic"; 88 + dai-link-0 { 89 + link-name = "ETDM3_OUT_BE"; 90 + 91 + codec { 92 + sound-dai = <&hdmi0>; 93 + }; 94 + }; 95 + }; 96 + 97 + ...

+23

sound/soc/mediatek/Kconfig

··· 208 208 Select Y if you have such device. 209 209 If unsure select "N". 210 210 211 + config SND_SOC_MT8188 212 + tristate "ASoC support for MediaTek MT8188 chip" 213 + depends on ARCH_MEDIATEK || COMPILE_TEST 214 + depends on COMMON_CLK 215 + select SND_SOC_MEDIATEK 216 + select MFD_SYSCON if SND_SOC_MT6359 217 + help 218 + This adds ASoC platform driver support for MediaTek MT8188 chip 219 + that can be used with other codecs. 220 + Select Y if you have such device. 221 + If unsure select "N". 222 + 223 + config SND_SOC_MT8188_MT6359 224 + tristate "ASoC Audio driver for MT8188 with MT6359 and I2S codecs" 225 + depends on SND_SOC_MT8188 && MTK_PMIC_WRAP 226 + select SND_SOC_MT6359 227 + select SND_SOC_HDMI_CODEC 228 + help 229 + This adds support for ASoC machine driver for MediaTek MT8188 230 + boards with the MT6359 and other I2S audio codecs. 231 + Select Y if you have such device. 232 + If unsure select "N". 233 + 211 234 config SND_SOC_MT8192 212 235 tristate "ASoC support for Mediatek MT8192 chip" 213 236 depends on ARCH_MEDIATEK

+1

sound/soc/mediatek/Makefile

··· 5 5 obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ 6 6 obj-$(CONFIG_SND_SOC_MT8183) += mt8183/ 7 7 obj-$(CONFIG_SND_SOC_MT8186) += mt8186/ 8 + obj-$(CONFIG_SND_SOC_MT8188) += mt8188/ 8 9 obj-$(CONFIG_SND_SOC_MT8192) += mt8192/ 9 10 obj-$(CONFIG_SND_SOC_MT8195) += mt8195/

+1 -1

sound/soc/mediatek/common/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 # platform driver 3 - snd-soc-mtk-common-objs := mtk-afe-platform-driver.o mtk-afe-fe-dai.o mtk-dsp-sof-common.o 3 + snd-soc-mtk-common-objs := mtk-afe-platform-driver.o mtk-afe-fe-dai.o mtk-dsp-sof-common.o mtk-soundcard-driver.o 4 4 obj-$(CONFIG_SND_SOC_MEDIATEK) += snd-soc-mtk-common.o 5 5 6 6 obj-$(CONFIG_SND_SOC_MTK_BTCVSD) += mtk-btcvsd.o

+19

sound/soc/mediatek/common/mtk-base-afe.h

··· 9 9 #ifndef _MTK_BASE_AFE_H_ 10 10 #define _MTK_BASE_AFE_H_ 11 11 12 + #include <linux/soc/mediatek/mtk_sip_svc.h> 13 + 12 14 #define MTK_STREAM_NUM (SNDRV_PCM_STREAM_LAST + 1) 15 + #define MTK_SIP_AUDIO_CONTROL MTK_SIP_SMC_CMD(0x517) 16 + 17 + /* SMC CALL Operations */ 18 + enum mtk_audio_smc_call_op { 19 + MTK_AUDIO_SMC_OP_INIT = 0, 20 + MTK_AUDIO_SMC_OP_DRAM_REQUEST, 21 + MTK_AUDIO_SMC_OP_DRAM_RELEASE, 22 + MTK_AUDIO_SMC_OP_SRAM_REQUEST, 23 + MTK_AUDIO_SMC_OP_SRAM_RELEASE, 24 + MTK_AUDIO_SMC_OP_ADSP_REQUEST, 25 + MTK_AUDIO_SMC_OP_ADSP_RELEASE, 26 + MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS, 27 + MTK_AUDIO_SMC_OP_BTCVSD_WRITE, 28 + MTK_AUDIO_SMC_OP_BTCVSD_UPDATE_CTRL_CLEAR, 29 + MTK_AUDIO_SMC_OP_BTCVSD_UPDATE_CTRL_UNDERFLOW, 30 + MTK_AUDIO_SMC_OP_NUM 31 + }; 13 32 14 33 struct mtk_base_memif_data { 15 34 int id;

+79

sound/soc/mediatek/common/mtk-soundcard-driver.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * mtk-soundcard-driver.c -- MediaTek soundcard driver common 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Trevor Wu <trevor.wu@mediatek.com> 7 + */ 8 + 9 + #include <linux/module.h> 10 + #include <linux/of.h> 11 + #include <sound/soc.h> 12 + 13 + #include "mtk-soundcard-driver.h" 14 + 15 + static int set_card_codec_info(struct snd_soc_card *card, 16 + struct device_node *sub_node, 17 + struct snd_soc_dai_link *dai_link) 18 + { 19 + struct device *dev = card->dev; 20 + struct device_node *codec_node; 21 + int ret; 22 + 23 + codec_node = of_get_child_by_name(sub_node, "codec"); 24 + if (!codec_node) 25 + return -EINVAL; 26 + 27 + /* set card codec info */ 28 + ret = snd_soc_of_get_dai_link_codecs(dev, codec_node, dai_link); 29 + 30 + of_node_put(codec_node); 31 + 32 + if (ret < 0) 33 + return dev_err_probe(dev, ret, "%s: codec dai not found\n", 34 + dai_link->name); 35 + 36 + return 0; 37 + } 38 + 39 + int parse_dai_link_info(struct snd_soc_card *card) 40 + { 41 + struct device *dev = card->dev; 42 + struct device_node *sub_node; 43 + struct snd_soc_dai_link *dai_link; 44 + const char *dai_link_name; 45 + int ret, i; 46 + 47 + /* Loop over all the dai link sub nodes */ 48 + for_each_available_child_of_node(dev->of_node, sub_node) { 49 + if (of_property_read_string(sub_node, "link-name", 50 + &dai_link_name)) 51 + return -EINVAL; 52 + 53 + for_each_card_prelinks(card, i, dai_link) { 54 + if (!strcmp(dai_link_name, dai_link->name)) 55 + break; 56 + } 57 + 58 + if (i >= card->num_links) 59 + return -EINVAL; 60 + 61 + ret = set_card_codec_info(card, sub_node, dai_link); 62 + if (ret < 0) 63 + return ret; 64 + } 65 + 66 + return 0; 67 + } 68 + EXPORT_SYMBOL_GPL(parse_dai_link_info); 69 + 70 + void clean_card_reference(struct snd_soc_card *card) 71 + { 72 + struct snd_soc_dai_link *dai_link; 73 + int i; 74 + 75 + /* release codec reference gotten by set_card_codec_info */ 76 + for_each_card_prelinks(card, i, dai_link) 77 + snd_soc_of_put_dai_link_codecs(dai_link); 78 + } 79 + EXPORT_SYMBOL_GPL(clean_card_reference);

+14

sound/soc/mediatek/common/mtk-soundcard-driver.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mtk-soundcard-driver.h -- MediaTek soundcard driver common definition 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Trevor Wu <trevor.wu@mediatek.com> 7 + */ 8 + 9 + #ifndef _MTK_SOUNDCARD_DRIVER_H_ 10 + #define _MTK_SOUNDCARD_DRIVER_H_ 11 + 12 + int parse_dai_link_info(struct snd_soc_card *card); 13 + void clean_card_reference(struct snd_soc_card *card); 14 + #endif

+15

sound/soc/mediatek/mt8188/Makefile

··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + 3 + # platform driver 4 + snd-soc-mt8188-afe-objs := \ 5 + mt8188-afe-clk.o \ 6 + mt8188-afe-pcm.o \ 7 + mt8188-audsys-clk.o \ 8 + mt8188-dai-adda.o \ 9 + mt8188-dai-etdm.o \ 10 + mt8188-dai-pcm.o 11 + 12 + obj-$(CONFIG_SND_SOC_MT8188) += snd-soc-mt8188-afe.o 13 + 14 + # machine driver 15 + obj-$(CONFIG_SND_SOC_MT8188_MT6359) += mt8188-mt6359.o

+658

sound/soc/mediatek/mt8188/mt8188-afe-clk.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #include <linux/clk.h> 12 + 13 + #include "mt8188-afe-common.h" 14 + #include "mt8188-afe-clk.h" 15 + #include "mt8188-audsys-clk.h" 16 + #include "mt8188-reg.h" 17 + 18 + static const char *aud_clks[MT8188_CLK_NUM] = { 19 + /* xtal */ 20 + [MT8188_CLK_XTAL_26M] = "clk26m", 21 + 22 + /* pll */ 23 + [MT8188_CLK_APMIXED_APLL1] = "apll1", 24 + [MT8188_CLK_APMIXED_APLL2] = "apll2", 25 + 26 + /* divider */ 27 + [MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0", 28 + [MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1", 29 + [MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2", 30 + [MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3", 31 + [MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9", 32 + 33 + /* mux */ 34 + [MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp", 35 + [MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus", 36 + [MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h", 37 + [MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus", 38 + [MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx", 39 + [MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1", 40 + [MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2", 41 + [MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1", 42 + [MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2", 43 + 44 + /* clock gate */ 45 + [MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m", 46 + /* afe clock gate */ 47 + [MT8188_CLK_AUD_AFE] = "aud_afe", 48 + [MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", 49 + [MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", 50 + [MT8188_CLK_AUD_APLL] = "aud_apll", 51 + [MT8188_CLK_AUD_APLL2] = "aud_apll2", 52 + [MT8188_CLK_AUD_DAC] = "aud_dac", 53 + [MT8188_CLK_AUD_ADC] = "aud_adc", 54 + [MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires", 55 + [MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", 56 + [MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires", 57 + [MT8188_CLK_AUD_I2SIN] = "aud_i2sin", 58 + [MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in", 59 + [MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out", 60 + [MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out", 61 + [MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", 62 + [MT8188_CLK_AUD_ASRC11] = "aud_asrc11", 63 + [MT8188_CLK_AUD_ASRC12] = "aud_asrc12", 64 + [MT8188_CLK_AUD_A1SYS] = "aud_a1sys", 65 + [MT8188_CLK_AUD_A2SYS] = "aud_a2sys", 66 + [MT8188_CLK_AUD_PCMIF] = "aud_pcmif", 67 + [MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", 68 + [MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", 69 + [MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", 70 + [MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", 71 + [MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", 72 + [MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", 73 + [MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", 74 + [MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", 75 + [MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", 76 + [MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", 77 + [MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", 78 + [MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", 79 + [MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", 80 + [MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", 81 + [MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", 82 + [MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", 83 + }; 84 + 85 + struct mt8188_afe_tuner_cfg { 86 + unsigned int id; 87 + int apll_div_reg; 88 + unsigned int apll_div_shift; 89 + unsigned int apll_div_maskbit; 90 + unsigned int apll_div_default; 91 + int ref_ck_sel_reg; 92 + unsigned int ref_ck_sel_shift; 93 + unsigned int ref_ck_sel_maskbit; 94 + unsigned int ref_ck_sel_default; 95 + int tuner_en_reg; 96 + unsigned int tuner_en_shift; 97 + unsigned int tuner_en_maskbit; 98 + int upper_bound_reg; 99 + unsigned int upper_bound_shift; 100 + unsigned int upper_bound_maskbit; 101 + unsigned int upper_bound_default; 102 + spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/ 103 + int ref_cnt; 104 + }; 105 + 106 + static struct mt8188_afe_tuner_cfg 107 + mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = { 108 + [MT8188_AUD_PLL1] = { 109 + .id = MT8188_AUD_PLL1, 110 + .apll_div_reg = AFE_APLL_TUNER_CFG, 111 + .apll_div_shift = 4, 112 + .apll_div_maskbit = 0xf, 113 + .apll_div_default = 0x7, 114 + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG, 115 + .ref_ck_sel_shift = 1, 116 + .ref_ck_sel_maskbit = 0x3, 117 + .ref_ck_sel_default = 0x2, 118 + .tuner_en_reg = AFE_APLL_TUNER_CFG, 119 + .tuner_en_shift = 0, 120 + .tuner_en_maskbit = 0x1, 121 + .upper_bound_reg = AFE_APLL_TUNER_CFG, 122 + .upper_bound_shift = 8, 123 + .upper_bound_maskbit = 0xff, 124 + .upper_bound_default = 0x3, 125 + }, 126 + [MT8188_AUD_PLL2] = { 127 + .id = MT8188_AUD_PLL2, 128 + .apll_div_reg = AFE_APLL_TUNER_CFG1, 129 + .apll_div_shift = 4, 130 + .apll_div_maskbit = 0xf, 131 + .apll_div_default = 0x7, 132 + .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1, 133 + .ref_ck_sel_shift = 1, 134 + .ref_ck_sel_maskbit = 0x3, 135 + .ref_ck_sel_default = 0x1, 136 + .tuner_en_reg = AFE_APLL_TUNER_CFG1, 137 + .tuner_en_shift = 0, 138 + .tuner_en_maskbit = 0x1, 139 + .upper_bound_reg = AFE_APLL_TUNER_CFG1, 140 + .upper_bound_shift = 8, 141 + .upper_bound_maskbit = 0xff, 142 + .upper_bound_default = 0x3, 143 + }, 144 + [MT8188_AUD_PLL3] = { 145 + .id = MT8188_AUD_PLL3, 146 + .apll_div_reg = AFE_EARC_APLL_TUNER_CFG, 147 + .apll_div_shift = 4, 148 + .apll_div_maskbit = 0x3f, 149 + .apll_div_default = 0x3, 150 + .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG, 151 + .ref_ck_sel_shift = 24, 152 + .ref_ck_sel_maskbit = 0x3, 153 + .ref_ck_sel_default = 0x0, 154 + .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG, 155 + .tuner_en_shift = 0, 156 + .tuner_en_maskbit = 0x1, 157 + .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG, 158 + .upper_bound_shift = 12, 159 + .upper_bound_maskbit = 0xff, 160 + .upper_bound_default = 0x4, 161 + }, 162 + [MT8188_AUD_PLL4] = { 163 + .id = MT8188_AUD_PLL4, 164 + .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 165 + .apll_div_shift = 4, 166 + .apll_div_maskbit = 0x3f, 167 + .apll_div_default = 0x7, 168 + .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1, 169 + .ref_ck_sel_shift = 8, 170 + .ref_ck_sel_maskbit = 0x1, 171 + .ref_ck_sel_default = 0, 172 + .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 173 + .tuner_en_shift = 0, 174 + .tuner_en_maskbit = 0x1, 175 + .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 176 + .upper_bound_shift = 12, 177 + .upper_bound_maskbit = 0xff, 178 + .upper_bound_default = 0x4, 179 + }, 180 + [MT8188_AUD_PLL5] = { 181 + .id = MT8188_AUD_PLL5, 182 + .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG, 183 + .apll_div_shift = 4, 184 + .apll_div_maskbit = 0x3f, 185 + .apll_div_default = 0x3, 186 + .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG, 187 + .ref_ck_sel_shift = 24, 188 + .ref_ck_sel_maskbit = 0x1, 189 + .ref_ck_sel_default = 0, 190 + .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG, 191 + .tuner_en_shift = 0, 192 + .tuner_en_maskbit = 0x1, 193 + .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG, 194 + .upper_bound_shift = 12, 195 + .upper_bound_maskbit = 0xff, 196 + .upper_bound_default = 0x4, 197 + }, 198 + }; 199 + 200 + static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id) 201 + { 202 + if (id >= MT8188_AUD_PLL_NUM) 203 + return NULL; 204 + 205 + return &mt8188_afe_tuner_cfgs[id]; 206 + } 207 + 208 + static int mt8188_afe_init_apll_tuner(unsigned int id) 209 + { 210 + struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 211 + 212 + if (!cfg) 213 + return -EINVAL; 214 + 215 + cfg->ref_cnt = 0; 216 + spin_lock_init(&cfg->ctrl_lock); 217 + 218 + return 0; 219 + } 220 + 221 + static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 222 + { 223 + const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 224 + 225 + if (!cfg) 226 + return -EINVAL; 227 + 228 + regmap_update_bits(afe->regmap, 229 + cfg->apll_div_reg, 230 + cfg->apll_div_maskbit << cfg->apll_div_shift, 231 + cfg->apll_div_default << cfg->apll_div_shift); 232 + 233 + regmap_update_bits(afe->regmap, 234 + cfg->ref_ck_sel_reg, 235 + cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, 236 + cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); 237 + 238 + regmap_update_bits(afe->regmap, 239 + cfg->upper_bound_reg, 240 + cfg->upper_bound_maskbit << cfg->upper_bound_shift, 241 + cfg->upper_bound_default << cfg->upper_bound_shift); 242 + 243 + return 0; 244 + } 245 + 246 + static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe, 247 + unsigned int id) 248 + { 249 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 250 + 251 + switch (id) { 252 + case MT8188_AUD_PLL1: 253 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]); 254 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]); 255 + break; 256 + case MT8188_AUD_PLL2: 257 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]); 258 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]); 259 + break; 260 + default: 261 + return -EINVAL; 262 + } 263 + 264 + return 0; 265 + } 266 + 267 + static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe, 268 + unsigned int id) 269 + { 270 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 271 + 272 + switch (id) { 273 + case MT8188_AUD_PLL1: 274 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]); 275 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]); 276 + break; 277 + case MT8188_AUD_PLL2: 278 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]); 279 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]); 280 + break; 281 + default: 282 + return -EINVAL; 283 + } 284 + 285 + return 0; 286 + } 287 + 288 + static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 289 + { 290 + struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 291 + unsigned long flags; 292 + int ret; 293 + 294 + if (!cfg) 295 + return -EINVAL; 296 + 297 + ret = mt8188_afe_setup_apll_tuner(afe, id); 298 + if (ret) 299 + return ret; 300 + 301 + ret = mt8188_afe_enable_tuner_clk(afe, id); 302 + if (ret) 303 + return ret; 304 + 305 + spin_lock_irqsave(&cfg->ctrl_lock, flags); 306 + 307 + cfg->ref_cnt++; 308 + if (cfg->ref_cnt == 1) 309 + regmap_update_bits(afe->regmap, 310 + cfg->tuner_en_reg, 311 + cfg->tuner_en_maskbit << cfg->tuner_en_shift, 312 + BIT(cfg->tuner_en_shift)); 313 + 314 + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 315 + 316 + return 0; 317 + } 318 + 319 + static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 320 + { 321 + struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 322 + unsigned long flags; 323 + int ret; 324 + 325 + if (!cfg) 326 + return -EINVAL; 327 + 328 + spin_lock_irqsave(&cfg->ctrl_lock, flags); 329 + 330 + cfg->ref_cnt--; 331 + if (cfg->ref_cnt == 0) 332 + regmap_update_bits(afe->regmap, 333 + cfg->tuner_en_reg, 334 + cfg->tuner_en_maskbit << cfg->tuner_en_shift, 335 + 0 << cfg->tuner_en_shift); 336 + else if (cfg->ref_cnt < 0) 337 + cfg->ref_cnt = 0; 338 + 339 + spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 340 + 341 + ret = mt8188_afe_disable_tuner_clk(afe, id); 342 + if (ret) 343 + return ret; 344 + 345 + return 0; 346 + } 347 + 348 + int mt8188_afe_get_mclk_source_clk_id(int sel) 349 + { 350 + switch (sel) { 351 + case MT8188_MCK_SEL_26M: 352 + return MT8188_CLK_XTAL_26M; 353 + case MT8188_MCK_SEL_APLL1: 354 + return MT8188_CLK_APMIXED_APLL1; 355 + case MT8188_MCK_SEL_APLL2: 356 + return MT8188_CLK_APMIXED_APLL2; 357 + default: 358 + return -EINVAL; 359 + } 360 + } 361 + 362 + int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) 363 + { 364 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 365 + int clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 366 + 367 + if (clk_id < 0) { 368 + dev_dbg(afe->dev, "invalid clk id\n"); 369 + return 0; 370 + } 371 + 372 + return clk_get_rate(afe_priv->clk[clk_id]); 373 + } 374 + 375 + int mt8188_afe_get_default_mclk_source_by_rate(int rate) 376 + { 377 + return ((rate % 8000) == 0) ? 378 + MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2; 379 + } 380 + 381 + int mt8188_afe_init_clock(struct mtk_base_afe *afe) 382 + { 383 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 384 + int i, ret; 385 + 386 + ret = mt8188_audsys_clk_register(afe); 387 + if (ret) { 388 + dev_err(afe->dev, "register audsys clk fail %d\n", ret); 389 + return ret; 390 + } 391 + 392 + afe_priv->clk = 393 + devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk), 394 + GFP_KERNEL); 395 + if (!afe_priv->clk) 396 + return -ENOMEM; 397 + 398 + for (i = 0; i < MT8188_CLK_NUM; i++) { 399 + afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 400 + if (IS_ERR(afe_priv->clk[i])) { 401 + dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", 402 + __func__, aud_clks[i], 403 + PTR_ERR(afe_priv->clk[i])); 404 + return PTR_ERR(afe_priv->clk[i]); 405 + } 406 + } 407 + 408 + /* initial tuner */ 409 + for (i = 0; i < MT8188_AUD_PLL_NUM; i++) { 410 + ret = mt8188_afe_init_apll_tuner(i); 411 + if (ret) { 412 + dev_info(afe->dev, "%s(), init apll_tuner%d failed", 413 + __func__, (i + 1)); 414 + return -EINVAL; 415 + } 416 + } 417 + 418 + return 0; 419 + } 420 + 421 + void mt8188_afe_deinit_clock(void *priv) 422 + { 423 + struct mtk_base_afe *afe = priv; 424 + 425 + mt8188_audsys_clk_unregister(afe); 426 + } 427 + 428 + int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) 429 + { 430 + int ret; 431 + 432 + if (clk) { 433 + ret = clk_prepare_enable(clk); 434 + if (ret) { 435 + dev_dbg(afe->dev, "%s(), failed to enable clk\n", 436 + __func__); 437 + return ret; 438 + } 439 + } else { 440 + dev_dbg(afe->dev, "NULL clk\n"); 441 + } 442 + return 0; 443 + } 444 + EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk); 445 + 446 + void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) 447 + { 448 + if (clk) 449 + clk_disable_unprepare(clk); 450 + else 451 + dev_dbg(afe->dev, "NULL clk\n"); 452 + } 453 + EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk); 454 + 455 + int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 456 + unsigned int rate) 457 + { 458 + int ret; 459 + 460 + if (clk) { 461 + ret = clk_set_rate(clk, rate); 462 + if (ret) { 463 + dev_dbg(afe->dev, "%s(), failed to set clk rate\n", 464 + __func__); 465 + return ret; 466 + } 467 + } 468 + 469 + return 0; 470 + } 471 + 472 + int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 473 + struct clk *parent) 474 + { 475 + int ret; 476 + 477 + if (clk && parent) { 478 + ret = clk_set_parent(clk, parent); 479 + if (ret) { 480 + dev_dbg(afe->dev, "%s(), failed to set clk parent\n", 481 + __func__); 482 + return ret; 483 + } 484 + } 485 + 486 + return 0; 487 + } 488 + 489 + static unsigned int get_top_cg_reg(unsigned int cg_type) 490 + { 491 + switch (cg_type) { 492 + case MT8188_TOP_CG_A1SYS_TIMING: 493 + case MT8188_TOP_CG_A2SYS_TIMING: 494 + case MT8188_TOP_CG_26M_TIMING: 495 + return ASYS_TOP_CON; 496 + default: 497 + return 0; 498 + } 499 + } 500 + 501 + static unsigned int get_top_cg_mask(unsigned int cg_type) 502 + { 503 + switch (cg_type) { 504 + case MT8188_TOP_CG_A1SYS_TIMING: 505 + return ASYS_TOP_CON_A1SYS_TIMING_ON; 506 + case MT8188_TOP_CG_A2SYS_TIMING: 507 + return ASYS_TOP_CON_A2SYS_TIMING_ON; 508 + case MT8188_TOP_CG_26M_TIMING: 509 + return ASYS_TOP_CON_26M_TIMING_ON; 510 + default: 511 + return 0; 512 + } 513 + } 514 + 515 + static unsigned int get_top_cg_on_val(unsigned int cg_type) 516 + { 517 + switch (cg_type) { 518 + case MT8188_TOP_CG_A1SYS_TIMING: 519 + case MT8188_TOP_CG_A2SYS_TIMING: 520 + case MT8188_TOP_CG_26M_TIMING: 521 + return get_top_cg_mask(cg_type); 522 + default: 523 + return 0; 524 + } 525 + } 526 + 527 + static unsigned int get_top_cg_off_val(unsigned int cg_type) 528 + { 529 + switch (cg_type) { 530 + case MT8188_TOP_CG_A1SYS_TIMING: 531 + case MT8188_TOP_CG_A2SYS_TIMING: 532 + case MT8188_TOP_CG_26M_TIMING: 533 + return 0; 534 + default: 535 + return get_top_cg_mask(cg_type); 536 + } 537 + } 538 + 539 + static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 540 + { 541 + unsigned int reg = get_top_cg_reg(cg_type); 542 + unsigned int mask = get_top_cg_mask(cg_type); 543 + unsigned int val = get_top_cg_on_val(cg_type); 544 + 545 + regmap_update_bits(afe->regmap, reg, mask, val); 546 + 547 + return 0; 548 + } 549 + 550 + static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 551 + { 552 + unsigned int reg = get_top_cg_reg(cg_type); 553 + unsigned int mask = get_top_cg_mask(cg_type); 554 + unsigned int val = get_top_cg_off_val(cg_type); 555 + 556 + regmap_update_bits(afe->regmap, reg, mask, val); 557 + 558 + return 0; 559 + } 560 + 561 + int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) 562 + { 563 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 564 + 565 + /* bus clock for AFE external access, like DRAM */ 566 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]); 567 + 568 + /* bus clock for AFE internal access, like AFE SRAM */ 569 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]); 570 + 571 + /* audio 26m clock source */ 572 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]); 573 + 574 + /* AFE hw clock */ 575 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]); 576 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); 577 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 578 + 579 + return 0; 580 + } 581 + 582 + int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) 583 + { 584 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 585 + 586 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 587 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); 588 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]); 589 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]); 590 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]); 591 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]); 592 + 593 + return 0; 594 + } 595 + 596 + static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe) 597 + { 598 + regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 599 + return 0; 600 + } 601 + 602 + static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe) 603 + { 604 + regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 605 + return 0; 606 + } 607 + 608 + static int mt8188_afe_enable_timing_sys(struct mtk_base_afe *afe) 609 + { 610 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 611 + 612 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 613 + mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 614 + 615 + mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 616 + mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 617 + mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 618 + 619 + return 0; 620 + } 621 + 622 + static int mt8188_afe_disable_timing_sys(struct mtk_base_afe *afe) 623 + { 624 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 625 + 626 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 627 + mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 628 + 629 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 630 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 631 + mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 632 + 633 + return 0; 634 + } 635 + 636 + int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe) 637 + { 638 + mt8188_afe_enable_timing_sys(afe); 639 + 640 + mt8188_afe_enable_afe_on(afe); 641 + 642 + mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1); 643 + mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2); 644 + 645 + return 0; 646 + } 647 + 648 + int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe) 649 + { 650 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 651 + mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 652 + 653 + mt8188_afe_disable_afe_on(afe); 654 + 655 + mt8188_afe_disable_timing_sys(afe); 656 + 657 + return 0; 658 + }

+115

sound/soc/mediatek/mt8188/mt8188-afe-clk.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #ifndef _MT8188_AFE_CLK_H_ 12 + #define _MT8188_AFE_CLK_H_ 13 + 14 + enum { 15 + /* xtal */ 16 + MT8188_CLK_XTAL_26M, 17 + /* pll */ 18 + MT8188_CLK_APMIXED_APLL1, 19 + MT8188_CLK_APMIXED_APLL2, 20 + /* divider */ 21 + MT8188_CLK_TOP_APLL12_DIV0, 22 + MT8188_CLK_TOP_APLL12_DIV1, 23 + MT8188_CLK_TOP_APLL12_DIV2, 24 + MT8188_CLK_TOP_APLL12_DIV3, 25 + MT8188_CLK_TOP_APLL12_DIV9, 26 + /* mux */ 27 + MT8188_CLK_TOP_A1SYS_HP_SEL, 28 + MT8188_CLK_TOP_AUD_INTBUS_SEL, 29 + MT8188_CLK_TOP_AUDIO_H_SEL, 30 + MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 31 + MT8188_CLK_TOP_DPTX_M_SEL, 32 + MT8188_CLK_TOP_I2SO1_M_SEL, 33 + MT8188_CLK_TOP_I2SO2_M_SEL, 34 + MT8188_CLK_TOP_I2SI1_M_SEL, 35 + MT8188_CLK_TOP_I2SI2_M_SEL, 36 + /* clock gate */ 37 + MT8188_CLK_ADSP_AUDIO_26M, 38 + MT8188_CLK_AUD_AFE, 39 + MT8188_CLK_AUD_APLL1_TUNER, 40 + MT8188_CLK_AUD_APLL2_TUNER, 41 + MT8188_CLK_AUD_TOP0_SPDF, 42 + MT8188_CLK_AUD_APLL, 43 + MT8188_CLK_AUD_APLL2, 44 + MT8188_CLK_AUD_DAC, 45 + MT8188_CLK_AUD_ADC, 46 + MT8188_CLK_AUD_DAC_HIRES, 47 + MT8188_CLK_AUD_A1SYS_HP, 48 + MT8188_CLK_AUD_ADC_HIRES, 49 + MT8188_CLK_AUD_I2SIN, 50 + MT8188_CLK_AUD_TDM_IN, 51 + MT8188_CLK_AUD_I2S_OUT, 52 + MT8188_CLK_AUD_TDM_OUT, 53 + MT8188_CLK_AUD_HDMI_OUT, 54 + MT8188_CLK_AUD_ASRC11, 55 + MT8188_CLK_AUD_ASRC12, 56 + MT8188_CLK_AUD_A1SYS, 57 + MT8188_CLK_AUD_A2SYS, 58 + MT8188_CLK_AUD_PCMIF, 59 + MT8188_CLK_AUD_MEMIF_UL1, 60 + MT8188_CLK_AUD_MEMIF_UL2, 61 + MT8188_CLK_AUD_MEMIF_UL3, 62 + MT8188_CLK_AUD_MEMIF_UL4, 63 + MT8188_CLK_AUD_MEMIF_UL5, 64 + MT8188_CLK_AUD_MEMIF_UL6, 65 + MT8188_CLK_AUD_MEMIF_UL8, 66 + MT8188_CLK_AUD_MEMIF_UL9, 67 + MT8188_CLK_AUD_MEMIF_UL10, 68 + MT8188_CLK_AUD_MEMIF_DL2, 69 + MT8188_CLK_AUD_MEMIF_DL3, 70 + MT8188_CLK_AUD_MEMIF_DL6, 71 + MT8188_CLK_AUD_MEMIF_DL7, 72 + MT8188_CLK_AUD_MEMIF_DL8, 73 + MT8188_CLK_AUD_MEMIF_DL10, 74 + MT8188_CLK_AUD_MEMIF_DL11, 75 + MT8188_CLK_NUM, 76 + }; 77 + 78 + enum { 79 + MT8188_AUD_PLL1, 80 + MT8188_AUD_PLL2, 81 + MT8188_AUD_PLL3, 82 + MT8188_AUD_PLL4, 83 + MT8188_AUD_PLL5, 84 + MT8188_AUD_PLL_NUM, 85 + }; 86 + 87 + enum { 88 + MT8188_MCK_SEL_26M, 89 + MT8188_MCK_SEL_APLL1, 90 + MT8188_MCK_SEL_APLL2, 91 + MT8188_MCK_SEL_APLL3, 92 + MT8188_MCK_SEL_APLL4, 93 + MT8188_MCK_SEL_APLL5, 94 + MT8188_MCK_SEL_NUM, 95 + }; 96 + 97 + struct mtk_base_afe; 98 + 99 + int mt8188_afe_get_mclk_source_clk_id(int sel); 100 + int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 101 + int mt8188_afe_get_default_mclk_source_by_rate(int rate); 102 + int mt8188_afe_init_clock(struct mtk_base_afe *afe); 103 + void mt8188_afe_deinit_clock(void *priv); 104 + int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 105 + void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 106 + int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 107 + unsigned int rate); 108 + int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 109 + struct clk *parent); 110 + int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 111 + int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 112 + int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 113 + int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 114 + 115 + #endif

+151

sound/soc/mediatek/mt8188/mt8188-afe-common.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mt8188-afe-common.h -- MediaTek 8188 audio driver definitions 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #ifndef _MT_8188_AFE_COMMON_H_ 12 + #define _MT_8188_AFE_COMMON_H_ 13 + 14 + #include <linux/list.h> 15 + #include <linux/regmap.h> 16 + #include <sound/soc.h> 17 + #include "../common/mtk-base-afe.h" 18 + 19 + enum { 20 + MT8188_DAI_START, 21 + MT8188_AFE_MEMIF_START = MT8188_DAI_START, 22 + MT8188_AFE_MEMIF_DL2 = MT8188_AFE_MEMIF_START, 23 + MT8188_AFE_MEMIF_DL3, 24 + MT8188_AFE_MEMIF_DL6, 25 + MT8188_AFE_MEMIF_DL7, 26 + MT8188_AFE_MEMIF_DL8, 27 + MT8188_AFE_MEMIF_DL10, 28 + MT8188_AFE_MEMIF_DL11, 29 + MT8188_AFE_MEMIF_UL_START, 30 + MT8188_AFE_MEMIF_UL1 = MT8188_AFE_MEMIF_UL_START, 31 + MT8188_AFE_MEMIF_UL2, 32 + MT8188_AFE_MEMIF_UL3, 33 + MT8188_AFE_MEMIF_UL4, 34 + MT8188_AFE_MEMIF_UL5, 35 + MT8188_AFE_MEMIF_UL6, 36 + MT8188_AFE_MEMIF_UL8, 37 + MT8188_AFE_MEMIF_UL9, 38 + MT8188_AFE_MEMIF_UL10, 39 + MT8188_AFE_MEMIF_END, 40 + MT8188_AFE_MEMIF_NUM = (MT8188_AFE_MEMIF_END - MT8188_AFE_MEMIF_START), 41 + MT8188_AFE_IO_START = MT8188_AFE_MEMIF_END, 42 + MT8188_AFE_IO_ADDA = MT8188_AFE_IO_START, 43 + MT8188_AFE_IO_DMIC_IN, 44 + MT8188_AFE_IO_DPTX, 45 + MT8188_AFE_IO_ETDM_START, 46 + MT8188_AFE_IO_ETDM1_IN = MT8188_AFE_IO_ETDM_START, 47 + MT8188_AFE_IO_ETDM2_IN, 48 + MT8188_AFE_IO_ETDM1_OUT, 49 + MT8188_AFE_IO_ETDM2_OUT, 50 + MT8188_AFE_IO_ETDM3_OUT, 51 + MT8188_AFE_IO_ETDM_END, 52 + MT8188_AFE_IO_ETDM_NUM = 53 + (MT8188_AFE_IO_ETDM_END - MT8188_AFE_IO_ETDM_START), 54 + MT8188_AFE_IO_PCM = MT8188_AFE_IO_ETDM_END, 55 + MT8188_AFE_IO_END, 56 + MT8188_AFE_IO_NUM = (MT8188_AFE_IO_END - MT8188_AFE_IO_START), 57 + MT8188_DAI_END = MT8188_AFE_IO_END, 58 + MT8188_DAI_NUM = (MT8188_DAI_END - MT8188_DAI_START), 59 + }; 60 + 61 + enum { 62 + MT8188_TOP_CG_A1SYS_TIMING, 63 + MT8188_TOP_CG_A2SYS_TIMING, 64 + MT8188_TOP_CG_26M_TIMING, 65 + MT8188_TOP_CG_NUM, 66 + }; 67 + 68 + enum { 69 + MT8188_AFE_IRQ_1, 70 + MT8188_AFE_IRQ_2, 71 + MT8188_AFE_IRQ_3, 72 + MT8188_AFE_IRQ_8, 73 + MT8188_AFE_IRQ_9, 74 + MT8188_AFE_IRQ_10, 75 + MT8188_AFE_IRQ_13, 76 + MT8188_AFE_IRQ_14, 77 + MT8188_AFE_IRQ_15, 78 + MT8188_AFE_IRQ_16, 79 + MT8188_AFE_IRQ_17, 80 + MT8188_AFE_IRQ_18, 81 + MT8188_AFE_IRQ_19, 82 + MT8188_AFE_IRQ_20, 83 + MT8188_AFE_IRQ_21, 84 + MT8188_AFE_IRQ_22, 85 + MT8188_AFE_IRQ_23, 86 + MT8188_AFE_IRQ_24, 87 + MT8188_AFE_IRQ_25, 88 + MT8188_AFE_IRQ_26, 89 + MT8188_AFE_IRQ_27, 90 + MT8188_AFE_IRQ_28, 91 + MT8188_AFE_IRQ_NUM, 92 + }; 93 + 94 + enum { 95 + MT8188_ETDM_OUT1_1X_EN = 9, 96 + MT8188_ETDM_OUT2_1X_EN = 10, 97 + MT8188_ETDM_OUT3_1X_EN = 11, 98 + MT8188_ETDM_IN1_1X_EN = 12, 99 + MT8188_ETDM_IN2_1X_EN = 13, 100 + MT8188_ETDM_IN1_NX_EN = 25, 101 + MT8188_ETDM_IN2_NX_EN = 26, 102 + }; 103 + 104 + enum { 105 + MT8188_MTKAIF_MISO_0, 106 + MT8188_MTKAIF_MISO_1, 107 + MT8188_MTKAIF_MISO_NUM, 108 + }; 109 + 110 + struct mtk_dai_memif_irq_priv { 111 + unsigned int asys_timing_sel; 112 + }; 113 + 114 + struct mtkaif_param { 115 + bool mtkaif_calibration_ok; 116 + int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM]; 117 + int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM]; 118 + int mtkaif_dmic_on; 119 + }; 120 + 121 + struct clk; 122 + 123 + struct mt8188_afe_private { 124 + struct clk **clk; 125 + struct clk_lookup **lookup; 126 + struct regmap *topckgen; 127 + int pm_runtime_bypass_reg_ctl; 128 + spinlock_t afe_ctrl_lock; /* Lock for afe control */ 129 + struct mtk_dai_memif_irq_priv irq_priv[MT8188_AFE_IRQ_NUM]; 130 + struct mtkaif_param mtkaif_params; 131 + 132 + /* dai */ 133 + void *dai_priv[MT8188_DAI_NUM]; 134 + }; 135 + 136 + int mt8188_afe_fs_timing(unsigned int rate); 137 + /* dai register */ 138 + int mt8188_dai_adda_register(struct mtk_base_afe *afe); 139 + int mt8188_dai_etdm_register(struct mtk_base_afe *afe); 140 + int mt8188_dai_pcm_register(struct mtk_base_afe *afe); 141 + 142 + #define MT8188_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \ 143 + { \ 144 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 145 + .info = snd_soc_info_enum_double, \ 146 + .get = xhandler_get, .put = xhandler_put, \ 147 + .device = id, \ 148 + .private_value = (unsigned long)&(xenum), \ 149 + } 150 + 151 + #endif

+3359

sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * MediaTek ALSA SoC AFE platform driver for 8188 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #include <linux/arm-smccc.h> 12 + #include <linux/delay.h> 13 + #include <linux/dma-mapping.h> 14 + #include <linux/module.h> 15 + #include <linux/mfd/syscon.h> 16 + #include <linux/of.h> 17 + #include <linux/of_address.h> 18 + #include <linux/of_platform.h> 19 + #include <linux/pm_runtime.h> 20 + #include <linux/reset.h> 21 + #include <sound/pcm_params.h> 22 + #include "mt8188-afe-common.h" 23 + #include "mt8188-afe-clk.h" 24 + #include "mt8188-reg.h" 25 + #include "../common/mtk-afe-platform-driver.h" 26 + #include "../common/mtk-afe-fe-dai.h" 27 + 28 + #define MT8188_MEMIF_BUFFER_BYTES_ALIGN (0x40) 29 + #define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff) 30 + 31 + #define MEMIF_AXI_MINLEN 9 /* register default value */ 32 + 33 + struct mtk_dai_memif_priv { 34 + unsigned int asys_timing_sel; 35 + unsigned int fs_timing; 36 + }; 37 + 38 + static const struct snd_pcm_hardware mt8188_afe_hardware = { 39 + .info = SNDRV_PCM_INFO_MMAP | 40 + SNDRV_PCM_INFO_INTERLEAVED | 41 + SNDRV_PCM_INFO_MMAP_VALID, 42 + .formats = SNDRV_PCM_FMTBIT_S16_LE | 43 + SNDRV_PCM_FMTBIT_S24_LE | 44 + SNDRV_PCM_FMTBIT_S32_LE, 45 + .period_bytes_min = 64, 46 + .period_bytes_max = 256 * 1024, 47 + .periods_min = 2, 48 + .periods_max = 256, 49 + .buffer_bytes_max = 256 * 2 * 1024, 50 + }; 51 + 52 + struct mt8188_afe_rate { 53 + unsigned int rate; 54 + unsigned int reg_value; 55 + }; 56 + 57 + static const struct mt8188_afe_rate mt8188_afe_rates[] = { 58 + { .rate = 8000, .reg_value = 0, }, 59 + { .rate = 12000, .reg_value = 1, }, 60 + { .rate = 16000, .reg_value = 2, }, 61 + { .rate = 24000, .reg_value = 3, }, 62 + { .rate = 32000, .reg_value = 4, }, 63 + { .rate = 48000, .reg_value = 5, }, 64 + { .rate = 96000, .reg_value = 6, }, 65 + { .rate = 192000, .reg_value = 7, }, 66 + { .rate = 384000, .reg_value = 8, }, 67 + { .rate = 7350, .reg_value = 16, }, 68 + { .rate = 11025, .reg_value = 17, }, 69 + { .rate = 14700, .reg_value = 18, }, 70 + { .rate = 22050, .reg_value = 19, }, 71 + { .rate = 29400, .reg_value = 20, }, 72 + { .rate = 44100, .reg_value = 21, }, 73 + { .rate = 88200, .reg_value = 22, }, 74 + { .rate = 176400, .reg_value = 23, }, 75 + { .rate = 352800, .reg_value = 24, }, 76 + }; 77 + 78 + int mt8188_afe_fs_timing(unsigned int rate) 79 + { 80 + int i; 81 + 82 + for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++) 83 + if (mt8188_afe_rates[i].rate == rate) 84 + return mt8188_afe_rates[i].reg_value; 85 + 86 + return -EINVAL; 87 + } 88 + 89 + static int mt8188_memif_fs(struct snd_pcm_substream *substream, 90 + unsigned int rate) 91 + { 92 + struct snd_soc_pcm_runtime *rtd = substream->private_data; 93 + struct snd_soc_component *component = NULL; 94 + struct mtk_base_afe *afe = NULL; 95 + struct mt8188_afe_private *afe_priv = NULL; 96 + struct mtk_base_afe_memif *memif = NULL; 97 + struct mtk_dai_memif_priv *memif_priv = NULL; 98 + int fs = mt8188_afe_fs_timing(rate); 99 + int id = asoc_rtd_to_cpu(rtd, 0)->id; 100 + 101 + if (id < 0) 102 + return -EINVAL; 103 + 104 + component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 105 + if (!component) 106 + return -EINVAL; 107 + 108 + afe = snd_soc_component_get_drvdata(component); 109 + memif = &afe->memif[id]; 110 + 111 + switch (memif->data->id) { 112 + case MT8188_AFE_MEMIF_DL10: 113 + fs = MT8188_ETDM_OUT3_1X_EN; 114 + break; 115 + case MT8188_AFE_MEMIF_UL8: 116 + fs = MT8188_ETDM_IN1_NX_EN; 117 + break; 118 + case MT8188_AFE_MEMIF_UL3: 119 + fs = MT8188_ETDM_IN2_NX_EN; 120 + break; 121 + default: 122 + afe_priv = afe->platform_priv; 123 + memif_priv = afe_priv->dai_priv[id]; 124 + if (memif_priv->fs_timing) 125 + fs = memif_priv->fs_timing; 126 + break; 127 + } 128 + 129 + return fs; 130 + } 131 + 132 + static int mt8188_irq_fs(struct snd_pcm_substream *substream, 133 + unsigned int rate) 134 + { 135 + int fs = mt8188_memif_fs(substream, rate); 136 + 137 + switch (fs) { 138 + case MT8188_ETDM_IN1_NX_EN: 139 + fs = MT8188_ETDM_IN1_1X_EN; 140 + break; 141 + case MT8188_ETDM_IN2_NX_EN: 142 + fs = MT8188_ETDM_IN2_1X_EN; 143 + break; 144 + default: 145 + break; 146 + } 147 + 148 + return fs; 149 + } 150 + 151 + enum { 152 + MT8188_AFE_CM0, 153 + MT8188_AFE_CM1, 154 + MT8188_AFE_CM2, 155 + MT8188_AFE_CM_NUM, 156 + }; 157 + 158 + struct mt8188_afe_channel_merge { 159 + int id; 160 + int reg; 161 + unsigned int sel_shift; 162 + unsigned int sel_maskbit; 163 + unsigned int sel_default; 164 + unsigned int ch_num_shift; 165 + unsigned int ch_num_maskbit; 166 + unsigned int en_shift; 167 + unsigned int en_maskbit; 168 + unsigned int update_cnt_shift; 169 + unsigned int update_cnt_maskbit; 170 + unsigned int update_cnt_default; 171 + }; 172 + 173 + static const struct mt8188_afe_channel_merge 174 + mt8188_afe_cm[MT8188_AFE_CM_NUM] = { 175 + [MT8188_AFE_CM0] = { 176 + .id = MT8188_AFE_CM0, 177 + .reg = AFE_CM0_CON, 178 + .sel_shift = 30, 179 + .sel_maskbit = 0x1, 180 + .sel_default = 1, 181 + .ch_num_shift = 2, 182 + .ch_num_maskbit = 0x3f, 183 + .en_shift = 0, 184 + .en_maskbit = 0x1, 185 + .update_cnt_shift = 16, 186 + .update_cnt_maskbit = 0x1fff, 187 + .update_cnt_default = 0x3, 188 + }, 189 + [MT8188_AFE_CM1] = { 190 + .id = MT8188_AFE_CM1, 191 + .reg = AFE_CM1_CON, 192 + .sel_shift = 30, 193 + .sel_maskbit = 0x1, 194 + .sel_default = 1, 195 + .ch_num_shift = 2, 196 + .ch_num_maskbit = 0x1f, 197 + .en_shift = 0, 198 + .en_maskbit = 0x1, 199 + .update_cnt_shift = 16, 200 + .update_cnt_maskbit = 0x1fff, 201 + .update_cnt_default = 0x3, 202 + }, 203 + [MT8188_AFE_CM2] = { 204 + .id = MT8188_AFE_CM2, 205 + .reg = AFE_CM2_CON, 206 + .sel_shift = 30, 207 + .sel_maskbit = 0x1, 208 + .sel_default = 1, 209 + .ch_num_shift = 2, 210 + .ch_num_maskbit = 0x1f, 211 + .en_shift = 0, 212 + .en_maskbit = 0x1, 213 + .update_cnt_shift = 16, 214 + .update_cnt_maskbit = 0x1fff, 215 + .update_cnt_default = 0x3, 216 + }, 217 + }; 218 + 219 + static int mt8188_afe_memif_is_ul(int id) 220 + { 221 + if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END) 222 + return 1; 223 + else 224 + return 0; 225 + } 226 + 227 + static const struct mt8188_afe_channel_merge * 228 + mt8188_afe_found_cm(struct snd_soc_dai *dai) 229 + { 230 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 231 + int id = -EINVAL; 232 + 233 + if (mt8188_afe_memif_is_ul(dai->id) == 0) 234 + return NULL; 235 + 236 + switch (dai->id) { 237 + case MT8188_AFE_MEMIF_UL9: 238 + id = MT8188_AFE_CM0; 239 + break; 240 + case MT8188_AFE_MEMIF_UL2: 241 + id = MT8188_AFE_CM1; 242 + break; 243 + case MT8188_AFE_MEMIF_UL10: 244 + id = MT8188_AFE_CM2; 245 + break; 246 + default: 247 + break; 248 + } 249 + 250 + if (id < 0) { 251 + dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id); 252 + return NULL; 253 + } 254 + 255 + return &mt8188_afe_cm[id]; 256 + } 257 + 258 + static int mt8188_afe_config_cm(struct mtk_base_afe *afe, 259 + const struct mt8188_afe_channel_merge *cm, 260 + unsigned int channels) 261 + { 262 + if (!cm) 263 + return -EINVAL; 264 + 265 + regmap_update_bits(afe->regmap, 266 + cm->reg, 267 + cm->sel_maskbit << cm->sel_shift, 268 + cm->sel_default << cm->sel_shift); 269 + 270 + regmap_update_bits(afe->regmap, 271 + cm->reg, 272 + cm->ch_num_maskbit << cm->ch_num_shift, 273 + (channels - 1) << cm->ch_num_shift); 274 + 275 + regmap_update_bits(afe->regmap, 276 + cm->reg, 277 + cm->update_cnt_maskbit << cm->update_cnt_shift, 278 + cm->update_cnt_default << cm->update_cnt_shift); 279 + 280 + return 0; 281 + } 282 + 283 + static int mt8188_afe_enable_cm(struct mtk_base_afe *afe, 284 + const struct mt8188_afe_channel_merge *cm, 285 + bool enable) 286 + { 287 + if (!cm) 288 + return -EINVAL; 289 + 290 + regmap_update_bits(afe->regmap, 291 + cm->reg, 292 + cm->en_maskbit << cm->en_shift, 293 + enable << cm->en_shift); 294 + 295 + return 0; 296 + } 297 + 298 + static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream, 299 + struct snd_soc_dai *dai) 300 + { 301 + struct snd_soc_pcm_runtime *rtd = substream->private_data; 302 + struct snd_pcm_runtime *runtime = substream->runtime; 303 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 304 + int id = asoc_rtd_to_cpu(rtd, 0)->id; 305 + int ret; 306 + 307 + ret = mtk_afe_fe_startup(substream, dai); 308 + 309 + snd_pcm_hw_constraint_step(runtime, 0, 310 + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 311 + MT8188_MEMIF_BUFFER_BYTES_ALIGN); 312 + 313 + if (id != MT8188_AFE_MEMIF_DL7) 314 + goto out; 315 + 316 + ret = snd_pcm_hw_constraint_minmax(runtime, 317 + SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1, 318 + MT8188_MEMIF_DL7_MAX_PERIOD_SIZE); 319 + if (ret < 0) 320 + dev_dbg(afe->dev, "hw_constraint_minmax failed\n"); 321 + out: 322 + return ret; 323 + } 324 + 325 + static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream, 326 + struct snd_soc_dai *dai) 327 + { 328 + mtk_afe_fe_shutdown(substream, dai); 329 + } 330 + 331 + static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream, 332 + struct snd_pcm_hw_params *params, 333 + struct snd_soc_dai *dai) 334 + { 335 + struct snd_soc_pcm_runtime *rtd = substream->private_data; 336 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 337 + int id = asoc_rtd_to_cpu(rtd, 0)->id; 338 + struct mtk_base_afe_memif *memif = &afe->memif[id]; 339 + const struct mtk_base_memif_data *data = memif->data; 340 + const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 341 + unsigned int channels = params_channels(params); 342 + 343 + mt8188_afe_config_cm(afe, cm, channels); 344 + 345 + if (data->ch_num_reg >= 0) { 346 + regmap_update_bits(afe->regmap, data->ch_num_reg, 347 + data->ch_num_maskbit << data->ch_num_shift, 348 + channels << data->ch_num_shift); 349 + } 350 + 351 + return mtk_afe_fe_hw_params(substream, params, dai); 352 + } 353 + 354 + static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 355 + struct snd_soc_dai *dai) 356 + { 357 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 358 + const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 359 + struct snd_soc_pcm_runtime *rtd = substream->private_data; 360 + struct snd_pcm_runtime * const runtime = substream->runtime; 361 + int id = asoc_rtd_to_cpu(rtd, 0)->id; 362 + struct mtk_base_afe_memif *memif = &afe->memif[id]; 363 + struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage]; 364 + const struct mtk_base_irq_data *irq_data = irqs->irq_data; 365 + unsigned int counter = runtime->period_size; 366 + int fs; 367 + int ret; 368 + 369 + switch (cmd) { 370 + case SNDRV_PCM_TRIGGER_START: 371 + case SNDRV_PCM_TRIGGER_RESUME: 372 + mt8188_afe_enable_cm(afe, cm, true); 373 + 374 + ret = mtk_memif_set_enable(afe, id); 375 + if (ret) { 376 + dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 377 + __func__, id, ret); 378 + return ret; 379 + } 380 + 381 + /* set irq counter */ 382 + regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 383 + irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift, 384 + counter << irq_data->irq_cnt_shift); 385 + 386 + /* set irq fs */ 387 + fs = afe->irq_fs(substream, runtime->rate); 388 + 389 + if (fs < 0) 390 + return -EINVAL; 391 + 392 + if (irq_data->irq_fs_reg >= 0) 393 + regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 394 + irq_data->irq_fs_maskbit << irq_data->irq_fs_shift, 395 + fs << irq_data->irq_fs_shift); 396 + 397 + /* delay for uplink */ 398 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 399 + u32 sample_delay; 400 + 401 + sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 + 402 + (runtime->channels * runtime->sample_bits - 1)) / 403 + (runtime->channels * runtime->sample_bits) + 1; 404 + 405 + udelay(sample_delay * 1000000 / runtime->rate); 406 + } 407 + 408 + /* enable interrupt */ 409 + regmap_set_bits(afe->regmap, irq_data->irq_en_reg, 410 + BIT(irq_data->irq_en_shift)); 411 + return 0; 412 + case SNDRV_PCM_TRIGGER_STOP: 413 + case SNDRV_PCM_TRIGGER_SUSPEND: 414 + mt8188_afe_enable_cm(afe, cm, false); 415 + 416 + ret = mtk_memif_set_disable(afe, id); 417 + if (ret) 418 + dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 419 + __func__, id, ret); 420 + 421 + /* disable interrupt */ 422 + 423 + regmap_clear_bits(afe->regmap, irq_data->irq_en_reg, 424 + BIT(irq_data->irq_en_shift)); 425 + /* and clear pending IRQ */ 426 + regmap_write(afe->regmap, irq_data->irq_clr_reg, 427 + BIT(irq_data->irq_clr_shift)); 428 + return ret; 429 + default: 430 + return -EINVAL; 431 + } 432 + } 433 + 434 + static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = { 435 + .startup = mt8188_afe_fe_startup, 436 + .shutdown = mt8188_afe_fe_shutdown, 437 + .hw_params = mt8188_afe_fe_hw_params, 438 + .hw_free = mtk_afe_fe_hw_free, 439 + .prepare = mtk_afe_fe_prepare, 440 + .trigger = mt8188_afe_fe_trigger, 441 + }; 442 + 443 + #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 444 + SNDRV_PCM_RATE_88200 |\ 445 + SNDRV_PCM_RATE_96000 |\ 446 + SNDRV_PCM_RATE_176400 |\ 447 + SNDRV_PCM_RATE_192000 |\ 448 + SNDRV_PCM_RATE_352800 |\ 449 + SNDRV_PCM_RATE_384000) 450 + 451 + #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 452 + SNDRV_PCM_FMTBIT_S24_LE |\ 453 + SNDRV_PCM_FMTBIT_S32_LE) 454 + 455 + static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = { 456 + /* FE DAIs: memory intefaces to CPU */ 457 + { 458 + .name = "DL2", 459 + .id = MT8188_AFE_MEMIF_DL2, 460 + .playback = { 461 + .stream_name = "DL2", 462 + .channels_min = 1, 463 + .channels_max = 2, 464 + .rates = MTK_PCM_RATES, 465 + .formats = MTK_PCM_FORMATS, 466 + }, 467 + .ops = &mt8188_afe_fe_dai_ops, 468 + }, 469 + { 470 + .name = "DL3", 471 + .id = MT8188_AFE_MEMIF_DL3, 472 + .playback = { 473 + .stream_name = "DL3", 474 + .channels_min = 1, 475 + .channels_max = 2, 476 + .rates = MTK_PCM_RATES, 477 + .formats = MTK_PCM_FORMATS, 478 + }, 479 + .ops = &mt8188_afe_fe_dai_ops, 480 + }, 481 + { 482 + .name = "DL6", 483 + .id = MT8188_AFE_MEMIF_DL6, 484 + .playback = { 485 + .stream_name = "DL6", 486 + .channels_min = 1, 487 + .channels_max = 2, 488 + .rates = MTK_PCM_RATES, 489 + .formats = MTK_PCM_FORMATS, 490 + }, 491 + .ops = &mt8188_afe_fe_dai_ops, 492 + }, 493 + { 494 + .name = "DL7", 495 + .id = MT8188_AFE_MEMIF_DL7, 496 + .playback = { 497 + .stream_name = "DL7", 498 + .channels_min = 1, 499 + .channels_max = 2, 500 + .rates = MTK_PCM_RATES, 501 + .formats = MTK_PCM_FORMATS, 502 + }, 503 + .ops = &mt8188_afe_fe_dai_ops, 504 + }, 505 + { 506 + .name = "DL8", 507 + .id = MT8188_AFE_MEMIF_DL8, 508 + .playback = { 509 + .stream_name = "DL8", 510 + .channels_min = 1, 511 + .channels_max = 16, 512 + .rates = MTK_PCM_RATES, 513 + .formats = MTK_PCM_FORMATS, 514 + }, 515 + .ops = &mt8188_afe_fe_dai_ops, 516 + }, 517 + { 518 + .name = "DL10", 519 + .id = MT8188_AFE_MEMIF_DL10, 520 + .playback = { 521 + .stream_name = "DL10", 522 + .channels_min = 1, 523 + .channels_max = 8, 524 + .rates = MTK_PCM_RATES, 525 + .formats = MTK_PCM_FORMATS, 526 + }, 527 + .ops = &mt8188_afe_fe_dai_ops, 528 + }, 529 + { 530 + .name = "DL11", 531 + .id = MT8188_AFE_MEMIF_DL11, 532 + .playback = { 533 + .stream_name = "DL11", 534 + .channels_min = 1, 535 + .channels_max = 32, 536 + .rates = MTK_PCM_RATES, 537 + .formats = MTK_PCM_FORMATS, 538 + }, 539 + .ops = &mt8188_afe_fe_dai_ops, 540 + }, 541 + { 542 + .name = "UL1", 543 + .id = MT8188_AFE_MEMIF_UL1, 544 + .capture = { 545 + .stream_name = "UL1", 546 + .channels_min = 1, 547 + .channels_max = 8, 548 + .rates = MTK_PCM_RATES, 549 + .formats = MTK_PCM_FORMATS, 550 + }, 551 + .ops = &mt8188_afe_fe_dai_ops, 552 + }, 553 + { 554 + .name = "UL2", 555 + .id = MT8188_AFE_MEMIF_UL2, 556 + .capture = { 557 + .stream_name = "UL2", 558 + .channels_min = 1, 559 + .channels_max = 8, 560 + .rates = MTK_PCM_RATES, 561 + .formats = MTK_PCM_FORMATS, 562 + }, 563 + .ops = &mt8188_afe_fe_dai_ops, 564 + }, 565 + { 566 + .name = "UL3", 567 + .id = MT8188_AFE_MEMIF_UL3, 568 + .capture = { 569 + .stream_name = "UL3", 570 + .channels_min = 1, 571 + .channels_max = 16, 572 + .rates = MTK_PCM_RATES, 573 + .formats = MTK_PCM_FORMATS, 574 + }, 575 + .ops = &mt8188_afe_fe_dai_ops, 576 + }, 577 + { 578 + .name = "UL4", 579 + .id = MT8188_AFE_MEMIF_UL4, 580 + .capture = { 581 + .stream_name = "UL4", 582 + .channels_min = 1, 583 + .channels_max = 2, 584 + .rates = MTK_PCM_RATES, 585 + .formats = MTK_PCM_FORMATS, 586 + }, 587 + .ops = &mt8188_afe_fe_dai_ops, 588 + }, 589 + { 590 + .name = "UL5", 591 + .id = MT8188_AFE_MEMIF_UL5, 592 + .capture = { 593 + .stream_name = "UL5", 594 + .channels_min = 1, 595 + .channels_max = 2, 596 + .rates = MTK_PCM_RATES, 597 + .formats = MTK_PCM_FORMATS, 598 + }, 599 + .ops = &mt8188_afe_fe_dai_ops, 600 + }, 601 + { 602 + .name = "UL6", 603 + .id = MT8188_AFE_MEMIF_UL6, 604 + .capture = { 605 + .stream_name = "UL6", 606 + .channels_min = 1, 607 + .channels_max = 8, 608 + .rates = MTK_PCM_RATES, 609 + .formats = MTK_PCM_FORMATS, 610 + }, 611 + .ops = &mt8188_afe_fe_dai_ops, 612 + }, 613 + { 614 + .name = "UL8", 615 + .id = MT8188_AFE_MEMIF_UL8, 616 + .capture = { 617 + .stream_name = "UL8", 618 + .channels_min = 1, 619 + .channels_max = 24, 620 + .rates = MTK_PCM_RATES, 621 + .formats = MTK_PCM_FORMATS, 622 + }, 623 + .ops = &mt8188_afe_fe_dai_ops, 624 + }, 625 + { 626 + .name = "UL9", 627 + .id = MT8188_AFE_MEMIF_UL9, 628 + .capture = { 629 + .stream_name = "UL9", 630 + .channels_min = 1, 631 + .channels_max = 32, 632 + .rates = MTK_PCM_RATES, 633 + .formats = MTK_PCM_FORMATS, 634 + }, 635 + .ops = &mt8188_afe_fe_dai_ops, 636 + }, 637 + { 638 + .name = "UL10", 639 + .id = MT8188_AFE_MEMIF_UL10, 640 + .capture = { 641 + .stream_name = "UL10", 642 + .channels_min = 1, 643 + .channels_max = 4, 644 + .rates = MTK_PCM_RATES, 645 + .formats = MTK_PCM_FORMATS, 646 + }, 647 + .ops = &mt8188_afe_fe_dai_ops, 648 + }, 649 + }; 650 + 651 + static const struct snd_kcontrol_new o002_mix[] = { 652 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0), 653 + SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0), 654 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0), 655 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0), 656 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0), 657 + SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0), 658 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0), 659 + }; 660 + 661 + static const struct snd_kcontrol_new o003_mix[] = { 662 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0), 663 + SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0), 664 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0), 665 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0), 666 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0), 667 + SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0), 668 + SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0), 669 + }; 670 + 671 + static const struct snd_kcontrol_new o004_mix[] = { 672 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0), 673 + SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0), 674 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0), 675 + SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0), 676 + }; 677 + 678 + static const struct snd_kcontrol_new o005_mix[] = { 679 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0), 680 + SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0), 681 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0), 682 + SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0), 683 + }; 684 + 685 + static const struct snd_kcontrol_new o006_mix[] = { 686 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0), 687 + SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0), 688 + SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0), 689 + SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0), 690 + }; 691 + 692 + static const struct snd_kcontrol_new o007_mix[] = { 693 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0), 694 + SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0), 695 + SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0), 696 + SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0), 697 + }; 698 + 699 + static const struct snd_kcontrol_new o008_mix[] = { 700 + SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0), 701 + SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0), 702 + SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0), 703 + }; 704 + 705 + static const struct snd_kcontrol_new o009_mix[] = { 706 + SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0), 707 + SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0), 708 + SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0), 709 + }; 710 + 711 + static const struct snd_kcontrol_new o010_mix[] = { 712 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0), 713 + SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0), 714 + SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0), 715 + SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0), 716 + SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0), 717 + SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0), 718 + }; 719 + 720 + static const struct snd_kcontrol_new o011_mix[] = { 721 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0), 722 + SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0), 723 + SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0), 724 + SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0), 725 + SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0), 726 + SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0), 727 + }; 728 + 729 + static const struct snd_kcontrol_new o012_mix[] = { 730 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0), 731 + SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0), 732 + SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0), 733 + SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0), 734 + SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0), 735 + SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0), 736 + }; 737 + 738 + static const struct snd_kcontrol_new o013_mix[] = { 739 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0), 740 + SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0), 741 + SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0), 742 + SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0), 743 + SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0), 744 + SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0), 745 + }; 746 + 747 + static const struct snd_kcontrol_new o014_mix[] = { 748 + SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0), 749 + SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0), 750 + SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0), 751 + SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0), 752 + SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0), 753 + SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0), 754 + }; 755 + 756 + static const struct snd_kcontrol_new o015_mix[] = { 757 + SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0), 758 + SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0), 759 + SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0), 760 + SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0), 761 + SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0), 762 + SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0), 763 + }; 764 + 765 + static const struct snd_kcontrol_new o016_mix[] = { 766 + SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0), 767 + SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0), 768 + SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0), 769 + SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0), 770 + SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0), 771 + SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0), 772 + }; 773 + 774 + static const struct snd_kcontrol_new o017_mix[] = { 775 + SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0), 776 + SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0), 777 + SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0), 778 + SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0), 779 + SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0), 780 + SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0), 781 + }; 782 + 783 + static const struct snd_kcontrol_new o018_mix[] = { 784 + SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0), 785 + }; 786 + 787 + static const struct snd_kcontrol_new o019_mix[] = { 788 + SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0), 789 + }; 790 + 791 + static const struct snd_kcontrol_new o020_mix[] = { 792 + SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0), 793 + }; 794 + 795 + static const struct snd_kcontrol_new o021_mix[] = { 796 + SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0), 797 + }; 798 + 799 + static const struct snd_kcontrol_new o022_mix[] = { 800 + SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0), 801 + }; 802 + 803 + static const struct snd_kcontrol_new o023_mix[] = { 804 + SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0), 805 + }; 806 + 807 + static const struct snd_kcontrol_new o024_mix[] = { 808 + SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0), 809 + }; 810 + 811 + static const struct snd_kcontrol_new o025_mix[] = { 812 + SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0), 813 + }; 814 + 815 + static const struct snd_kcontrol_new o026_mix[] = { 816 + SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0), 817 + }; 818 + 819 + static const struct snd_kcontrol_new o027_mix[] = { 820 + SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0), 821 + }; 822 + 823 + static const struct snd_kcontrol_new o028_mix[] = { 824 + SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0), 825 + }; 826 + 827 + static const struct snd_kcontrol_new o029_mix[] = { 828 + SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0), 829 + }; 830 + 831 + static const struct snd_kcontrol_new o030_mix[] = { 832 + SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0), 833 + }; 834 + 835 + static const struct snd_kcontrol_new o031_mix[] = { 836 + SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0), 837 + }; 838 + 839 + static const struct snd_kcontrol_new o032_mix[] = { 840 + SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0), 841 + }; 842 + 843 + static const struct snd_kcontrol_new o033_mix[] = { 844 + SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0), 845 + }; 846 + 847 + static const struct snd_kcontrol_new o034_mix[] = { 848 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0), 849 + SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0), 850 + SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0), 851 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0), 852 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0), 853 + SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0), 854 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0), 855 + }; 856 + 857 + static const struct snd_kcontrol_new o035_mix[] = { 858 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0), 859 + SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0), 860 + SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0), 861 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0), 862 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0), 863 + SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0), 864 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0), 865 + SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0), 866 + }; 867 + 868 + static const struct snd_kcontrol_new o036_mix[] = { 869 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0), 870 + SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0), 871 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0), 872 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0), 873 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0), 874 + }; 875 + 876 + static const struct snd_kcontrol_new o037_mix[] = { 877 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0), 878 + SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0), 879 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0), 880 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0), 881 + SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0), 882 + }; 883 + 884 + static const struct snd_kcontrol_new o038_mix[] = { 885 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0), 886 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0), 887 + }; 888 + 889 + static const struct snd_kcontrol_new o039_mix[] = { 890 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0), 891 + SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0), 892 + }; 893 + 894 + static const struct snd_kcontrol_new o040_mix[] = { 895 + SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0), 896 + SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0), 897 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0), 898 + SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0), 899 + }; 900 + 901 + static const struct snd_kcontrol_new o041_mix[] = { 902 + SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0), 903 + SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0), 904 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0), 905 + SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0), 906 + }; 907 + 908 + static const struct snd_kcontrol_new o042_mix[] = { 909 + SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0), 910 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0), 911 + }; 912 + 913 + static const struct snd_kcontrol_new o043_mix[] = { 914 + SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0), 915 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0), 916 + }; 917 + 918 + static const struct snd_kcontrol_new o044_mix[] = { 919 + SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0), 920 + SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0), 921 + }; 922 + 923 + static const struct snd_kcontrol_new o045_mix[] = { 924 + SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0), 925 + SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0), 926 + }; 927 + 928 + static const struct snd_kcontrol_new o046_mix[] = { 929 + SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0), 930 + SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0), 931 + }; 932 + 933 + static const struct snd_kcontrol_new o047_mix[] = { 934 + SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0), 935 + SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0), 936 + }; 937 + 938 + static const struct snd_kcontrol_new o182_mix[] = { 939 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0), 940 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0), 941 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0), 942 + }; 943 + 944 + static const struct snd_kcontrol_new o183_mix[] = { 945 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0), 946 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0), 947 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0), 948 + }; 949 + 950 + static const char * const dl8_dl11_data_sel_mux_text[] = { 951 + "dl8", "dl11", 952 + }; 953 + 954 + static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, 955 + AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); 956 + 957 + static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = 958 + SOC_DAPM_ENUM("DL8_DL11 Sink", 959 + dl8_dl11_data_sel_mux_enum); 960 + 961 + static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = { 962 + /* DL6 */ 963 + SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0), 964 + SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0), 965 + 966 + /* DL3 */ 967 + SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0), 968 + SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0), 969 + 970 + /* DL11 */ 971 + SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0), 972 + SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0), 973 + SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0), 974 + SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0), 975 + SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0), 976 + SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0), 977 + SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0), 978 + SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0), 979 + SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0), 980 + SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0), 981 + SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), 982 + SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), 983 + SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0), 984 + SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0), 985 + SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0), 986 + SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0), 987 + 988 + /* DL11/DL8 */ 989 + SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0), 990 + SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0), 991 + SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0), 992 + SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0), 993 + SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0), 994 + SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0), 995 + SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0), 996 + SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0), 997 + SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0), 998 + SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0), 999 + SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 + SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0), 1001 + SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0), 1002 + SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0), 1003 + SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0), 1004 + SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0), 1005 + 1006 + /* DL2 */ 1007 + SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0), 1008 + SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0), 1009 + 1010 + SND_SOC_DAPM_MUX("DL8_DL11 Mux", 1011 + SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux), 1012 + 1013 + /* UL9 */ 1014 + SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0, 1015 + o002_mix, ARRAY_SIZE(o002_mix)), 1016 + SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0, 1017 + o003_mix, ARRAY_SIZE(o003_mix)), 1018 + SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0, 1019 + o004_mix, ARRAY_SIZE(o004_mix)), 1020 + SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0, 1021 + o005_mix, ARRAY_SIZE(o005_mix)), 1022 + SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0, 1023 + o006_mix, ARRAY_SIZE(o006_mix)), 1024 + SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0, 1025 + o007_mix, ARRAY_SIZE(o007_mix)), 1026 + SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0, 1027 + o008_mix, ARRAY_SIZE(o008_mix)), 1028 + SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0, 1029 + o009_mix, ARRAY_SIZE(o009_mix)), 1030 + SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0, 1031 + o010_mix, ARRAY_SIZE(o010_mix)), 1032 + SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0, 1033 + o011_mix, ARRAY_SIZE(o011_mix)), 1034 + SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0, 1035 + o012_mix, ARRAY_SIZE(o012_mix)), 1036 + SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0, 1037 + o013_mix, ARRAY_SIZE(o013_mix)), 1038 + SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0, 1039 + o014_mix, ARRAY_SIZE(o014_mix)), 1040 + SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0, 1041 + o015_mix, ARRAY_SIZE(o015_mix)), 1042 + SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0, 1043 + o016_mix, ARRAY_SIZE(o016_mix)), 1044 + SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0, 1045 + o017_mix, ARRAY_SIZE(o017_mix)), 1046 + SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, 1047 + o018_mix, ARRAY_SIZE(o018_mix)), 1048 + SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, 1049 + o019_mix, ARRAY_SIZE(o019_mix)), 1050 + SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0, 1051 + o020_mix, ARRAY_SIZE(o020_mix)), 1052 + SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0, 1053 + o021_mix, ARRAY_SIZE(o021_mix)), 1054 + SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0, 1055 + o022_mix, ARRAY_SIZE(o022_mix)), 1056 + SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0, 1057 + o023_mix, ARRAY_SIZE(o023_mix)), 1058 + SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0, 1059 + o024_mix, ARRAY_SIZE(o024_mix)), 1060 + SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0, 1061 + o025_mix, ARRAY_SIZE(o025_mix)), 1062 + SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0, 1063 + o026_mix, ARRAY_SIZE(o026_mix)), 1064 + SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0, 1065 + o027_mix, ARRAY_SIZE(o027_mix)), 1066 + SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0, 1067 + o028_mix, ARRAY_SIZE(o028_mix)), 1068 + SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0, 1069 + o029_mix, ARRAY_SIZE(o029_mix)), 1070 + SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0, 1071 + o030_mix, ARRAY_SIZE(o030_mix)), 1072 + SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0, 1073 + o031_mix, ARRAY_SIZE(o031_mix)), 1074 + SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0, 1075 + o032_mix, ARRAY_SIZE(o032_mix)), 1076 + SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0, 1077 + o033_mix, ARRAY_SIZE(o033_mix)), 1078 + 1079 + /* UL4 */ 1080 + SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0, 1081 + o034_mix, ARRAY_SIZE(o034_mix)), 1082 + SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0, 1083 + o035_mix, ARRAY_SIZE(o035_mix)), 1084 + 1085 + /* UL5 */ 1086 + SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0, 1087 + o036_mix, ARRAY_SIZE(o036_mix)), 1088 + SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0, 1089 + o037_mix, ARRAY_SIZE(o037_mix)), 1090 + 1091 + /* UL10 */ 1092 + SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0, 1093 + o038_mix, ARRAY_SIZE(o038_mix)), 1094 + SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0, 1095 + o039_mix, ARRAY_SIZE(o039_mix)), 1096 + SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0, 1097 + o182_mix, ARRAY_SIZE(o182_mix)), 1098 + SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0, 1099 + o183_mix, ARRAY_SIZE(o183_mix)), 1100 + 1101 + /* UL2 */ 1102 + SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0, 1103 + o040_mix, ARRAY_SIZE(o040_mix)), 1104 + SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0, 1105 + o041_mix, ARRAY_SIZE(o041_mix)), 1106 + SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0, 1107 + o042_mix, ARRAY_SIZE(o042_mix)), 1108 + SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0, 1109 + o043_mix, ARRAY_SIZE(o043_mix)), 1110 + SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0, 1111 + o044_mix, ARRAY_SIZE(o044_mix)), 1112 + SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0, 1113 + o045_mix, ARRAY_SIZE(o045_mix)), 1114 + SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0, 1115 + o046_mix, ARRAY_SIZE(o046_mix)), 1116 + SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0, 1117 + o047_mix, ARRAY_SIZE(o047_mix)), 1118 + }; 1119 + 1120 + static const struct snd_soc_dapm_route mt8188_memif_routes[] = { 1121 + {"I000", NULL, "DL6"}, 1122 + {"I001", NULL, "DL6"}, 1123 + 1124 + {"I020", NULL, "DL3"}, 1125 + {"I021", NULL, "DL3"}, 1126 + 1127 + {"I022", NULL, "DL11"}, 1128 + {"I023", NULL, "DL11"}, 1129 + {"I024", NULL, "DL11"}, 1130 + {"I025", NULL, "DL11"}, 1131 + {"I026", NULL, "DL11"}, 1132 + {"I027", NULL, "DL11"}, 1133 + {"I028", NULL, "DL11"}, 1134 + {"I029", NULL, "DL11"}, 1135 + {"I030", NULL, "DL11"}, 1136 + {"I031", NULL, "DL11"}, 1137 + {"I032", NULL, "DL11"}, 1138 + {"I033", NULL, "DL11"}, 1139 + {"I034", NULL, "DL11"}, 1140 + {"I035", NULL, "DL11"}, 1141 + {"I036", NULL, "DL11"}, 1142 + {"I037", NULL, "DL11"}, 1143 + 1144 + {"DL8_DL11 Mux", "dl8", "DL8"}, 1145 + {"DL8_DL11 Mux", "dl11", "DL11"}, 1146 + 1147 + {"I046", NULL, "DL8_DL11 Mux"}, 1148 + {"I047", NULL, "DL8_DL11 Mux"}, 1149 + {"I048", NULL, "DL8_DL11 Mux"}, 1150 + {"I049", NULL, "DL8_DL11 Mux"}, 1151 + {"I050", NULL, "DL8_DL11 Mux"}, 1152 + {"I051", NULL, "DL8_DL11 Mux"}, 1153 + {"I052", NULL, "DL8_DL11 Mux"}, 1154 + {"I053", NULL, "DL8_DL11 Mux"}, 1155 + {"I054", NULL, "DL8_DL11 Mux"}, 1156 + {"I055", NULL, "DL8_DL11 Mux"}, 1157 + {"I056", NULL, "DL8_DL11 Mux"}, 1158 + {"I057", NULL, "DL8_DL11 Mux"}, 1159 + {"I058", NULL, "DL8_DL11 Mux"}, 1160 + {"I059", NULL, "DL8_DL11 Mux"}, 1161 + {"I060", NULL, "DL8_DL11 Mux"}, 1162 + {"I061", NULL, "DL8_DL11 Mux"}, 1163 + 1164 + {"I070", NULL, "DL2"}, 1165 + {"I071", NULL, "DL2"}, 1166 + 1167 + {"UL9", NULL, "O002"}, 1168 + {"UL9", NULL, "O003"}, 1169 + {"UL9", NULL, "O004"}, 1170 + {"UL9", NULL, "O005"}, 1171 + {"UL9", NULL, "O006"}, 1172 + {"UL9", NULL, "O007"}, 1173 + {"UL9", NULL, "O008"}, 1174 + {"UL9", NULL, "O009"}, 1175 + {"UL9", NULL, "O010"}, 1176 + {"UL9", NULL, "O011"}, 1177 + {"UL9", NULL, "O012"}, 1178 + {"UL9", NULL, "O013"}, 1179 + {"UL9", NULL, "O014"}, 1180 + {"UL9", NULL, "O015"}, 1181 + {"UL9", NULL, "O016"}, 1182 + {"UL9", NULL, "O017"}, 1183 + {"UL9", NULL, "O018"}, 1184 + {"UL9", NULL, "O019"}, 1185 + {"UL9", NULL, "O020"}, 1186 + {"UL9", NULL, "O021"}, 1187 + {"UL9", NULL, "O022"}, 1188 + {"UL9", NULL, "O023"}, 1189 + {"UL9", NULL, "O024"}, 1190 + {"UL9", NULL, "O025"}, 1191 + {"UL9", NULL, "O026"}, 1192 + {"UL9", NULL, "O027"}, 1193 + {"UL9", NULL, "O028"}, 1194 + {"UL9", NULL, "O029"}, 1195 + {"UL9", NULL, "O030"}, 1196 + {"UL9", NULL, "O031"}, 1197 + {"UL9", NULL, "O032"}, 1198 + {"UL9", NULL, "O033"}, 1199 + 1200 + {"UL4", NULL, "O034"}, 1201 + {"UL4", NULL, "O035"}, 1202 + 1203 + {"UL5", NULL, "O036"}, 1204 + {"UL5", NULL, "O037"}, 1205 + 1206 + {"UL10", NULL, "O038"}, 1207 + {"UL10", NULL, "O039"}, 1208 + {"UL10", NULL, "O182"}, 1209 + {"UL10", NULL, "O183"}, 1210 + 1211 + {"UL2", NULL, "O040"}, 1212 + {"UL2", NULL, "O041"}, 1213 + {"UL2", NULL, "O042"}, 1214 + {"UL2", NULL, "O043"}, 1215 + {"UL2", NULL, "O044"}, 1216 + {"UL2", NULL, "O045"}, 1217 + {"UL2", NULL, "O046"}, 1218 + {"UL2", NULL, "O047"}, 1219 + 1220 + {"O004", "I000 Switch", "I000"}, 1221 + {"O005", "I001 Switch", "I001"}, 1222 + 1223 + {"O006", "I000 Switch", "I000"}, 1224 + {"O007", "I001 Switch", "I001"}, 1225 + 1226 + {"O010", "I022 Switch", "I022"}, 1227 + {"O011", "I023 Switch", "I023"}, 1228 + {"O012", "I024 Switch", "I024"}, 1229 + {"O013", "I025 Switch", "I025"}, 1230 + {"O014", "I026 Switch", "I026"}, 1231 + {"O015", "I027 Switch", "I027"}, 1232 + {"O016", "I028 Switch", "I028"}, 1233 + {"O017", "I029 Switch", "I029"}, 1234 + 1235 + {"O010", "I046 Switch", "I046"}, 1236 + {"O011", "I047 Switch", "I047"}, 1237 + {"O012", "I048 Switch", "I048"}, 1238 + {"O013", "I049 Switch", "I049"}, 1239 + {"O014", "I050 Switch", "I050"}, 1240 + {"O015", "I051 Switch", "I051"}, 1241 + {"O016", "I052 Switch", "I052"}, 1242 + {"O017", "I053 Switch", "I053"}, 1243 + 1244 + {"O002", "I022 Switch", "I022"}, 1245 + {"O003", "I023 Switch", "I023"}, 1246 + {"O004", "I024 Switch", "I024"}, 1247 + {"O005", "I025 Switch", "I025"}, 1248 + {"O006", "I026 Switch", "I026"}, 1249 + {"O007", "I027 Switch", "I027"}, 1250 + {"O008", "I028 Switch", "I028"}, 1251 + {"O009", "I029 Switch", "I029"}, 1252 + {"O010", "I030 Switch", "I030"}, 1253 + {"O011", "I031 Switch", "I031"}, 1254 + {"O012", "I032 Switch", "I032"}, 1255 + {"O013", "I033 Switch", "I033"}, 1256 + {"O014", "I034 Switch", "I034"}, 1257 + {"O015", "I035 Switch", "I035"}, 1258 + {"O016", "I036 Switch", "I036"}, 1259 + {"O017", "I037 Switch", "I037"}, 1260 + {"O026", "I046 Switch", "I046"}, 1261 + {"O027", "I047 Switch", "I047"}, 1262 + {"O028", "I048 Switch", "I048"}, 1263 + {"O029", "I049 Switch", "I049"}, 1264 + {"O030", "I050 Switch", "I050"}, 1265 + {"O031", "I051 Switch", "I051"}, 1266 + {"O032", "I052 Switch", "I052"}, 1267 + {"O033", "I053 Switch", "I053"}, 1268 + 1269 + {"O002", "I000 Switch", "I000"}, 1270 + {"O003", "I001 Switch", "I001"}, 1271 + {"O002", "I020 Switch", "I020"}, 1272 + {"O003", "I021 Switch", "I021"}, 1273 + {"O002", "I070 Switch", "I070"}, 1274 + {"O003", "I071 Switch", "I071"}, 1275 + 1276 + {"O034", "I000 Switch", "I000"}, 1277 + {"O035", "I001 Switch", "I001"}, 1278 + {"O034", "I002 Switch", "I002"}, 1279 + {"O035", "I003 Switch", "I003"}, 1280 + {"O034", "I012 Switch", "I012"}, 1281 + {"O035", "I013 Switch", "I013"}, 1282 + {"O034", "I020 Switch", "I020"}, 1283 + {"O035", "I021 Switch", "I021"}, 1284 + {"O034", "I070 Switch", "I070"}, 1285 + {"O035", "I071 Switch", "I071"}, 1286 + {"O034", "I072 Switch", "I072"}, 1287 + {"O035", "I073 Switch", "I073"}, 1288 + 1289 + {"O036", "I000 Switch", "I000"}, 1290 + {"O037", "I001 Switch", "I001"}, 1291 + {"O036", "I012 Switch", "I012"}, 1292 + {"O037", "I013 Switch", "I013"}, 1293 + {"O036", "I020 Switch", "I020"}, 1294 + {"O037", "I021 Switch", "I021"}, 1295 + {"O036", "I070 Switch", "I070"}, 1296 + {"O037", "I071 Switch", "I071"}, 1297 + {"O036", "I168 Switch", "I168"}, 1298 + {"O037", "I169 Switch", "I169"}, 1299 + 1300 + {"O038", "I022 Switch", "I022"}, 1301 + {"O039", "I023 Switch", "I023"}, 1302 + {"O182", "I024 Switch", "I024"}, 1303 + {"O183", "I025 Switch", "I025"}, 1304 + 1305 + {"O038", "I168 Switch", "I168"}, 1306 + {"O039", "I169 Switch", "I169"}, 1307 + 1308 + {"O182", "I020 Switch", "I020"}, 1309 + {"O183", "I021 Switch", "I021"}, 1310 + 1311 + {"O182", "I022 Switch", "I022"}, 1312 + {"O183", "I023 Switch", "I023"}, 1313 + 1314 + {"O040", "I022 Switch", "I022"}, 1315 + {"O041", "I023 Switch", "I023"}, 1316 + {"O042", "I024 Switch", "I024"}, 1317 + {"O043", "I025 Switch", "I025"}, 1318 + {"O044", "I026 Switch", "I026"}, 1319 + {"O045", "I027 Switch", "I027"}, 1320 + {"O046", "I028 Switch", "I028"}, 1321 + {"O047", "I029 Switch", "I029"}, 1322 + 1323 + {"O040", "I002 Switch", "I002"}, 1324 + {"O041", "I003 Switch", "I003"}, 1325 + 1326 + {"O002", "I012 Switch", "I012"}, 1327 + {"O003", "I013 Switch", "I013"}, 1328 + {"O004", "I014 Switch", "I014"}, 1329 + {"O005", "I015 Switch", "I015"}, 1330 + {"O006", "I016 Switch", "I016"}, 1331 + {"O007", "I017 Switch", "I017"}, 1332 + {"O008", "I018 Switch", "I018"}, 1333 + {"O009", "I019 Switch", "I019"}, 1334 + {"O010", "I188 Switch", "I188"}, 1335 + {"O011", "I189 Switch", "I189"}, 1336 + {"O012", "I190 Switch", "I190"}, 1337 + {"O013", "I191 Switch", "I191"}, 1338 + {"O014", "I192 Switch", "I192"}, 1339 + {"O015", "I193 Switch", "I193"}, 1340 + {"O016", "I194 Switch", "I194"}, 1341 + {"O017", "I195 Switch", "I195"}, 1342 + 1343 + {"O040", "I012 Switch", "I012"}, 1344 + {"O041", "I013 Switch", "I013"}, 1345 + {"O042", "I014 Switch", "I014"}, 1346 + {"O043", "I015 Switch", "I015"}, 1347 + {"O044", "I016 Switch", "I016"}, 1348 + {"O045", "I017 Switch", "I017"}, 1349 + {"O046", "I018 Switch", "I018"}, 1350 + {"O047", "I019 Switch", "I019"}, 1351 + 1352 + {"O002", "I072 Switch", "I072"}, 1353 + {"O003", "I073 Switch", "I073"}, 1354 + {"O004", "I074 Switch", "I074"}, 1355 + {"O005", "I075 Switch", "I075"}, 1356 + {"O006", "I076 Switch", "I076"}, 1357 + {"O007", "I077 Switch", "I077"}, 1358 + {"O008", "I078 Switch", "I078"}, 1359 + {"O009", "I079 Switch", "I079"}, 1360 + {"O010", "I080 Switch", "I080"}, 1361 + {"O011", "I081 Switch", "I081"}, 1362 + {"O012", "I082 Switch", "I082"}, 1363 + {"O013", "I083 Switch", "I083"}, 1364 + {"O014", "I084 Switch", "I084"}, 1365 + {"O015", "I085 Switch", "I085"}, 1366 + {"O016", "I086 Switch", "I086"}, 1367 + {"O017", "I087 Switch", "I087"}, 1368 + 1369 + {"O010", "I072 Switch", "I072"}, 1370 + {"O011", "I073 Switch", "I073"}, 1371 + {"O012", "I074 Switch", "I074"}, 1372 + {"O013", "I075 Switch", "I075"}, 1373 + {"O014", "I076 Switch", "I076"}, 1374 + {"O015", "I077 Switch", "I077"}, 1375 + {"O016", "I078 Switch", "I078"}, 1376 + {"O017", "I079 Switch", "I079"}, 1377 + {"O018", "I080 Switch", "I080"}, 1378 + {"O019", "I081 Switch", "I081"}, 1379 + {"O020", "I082 Switch", "I082"}, 1380 + {"O021", "I083 Switch", "I083"}, 1381 + {"O022", "I084 Switch", "I084"}, 1382 + {"O023", "I085 Switch", "I085"}, 1383 + {"O024", "I086 Switch", "I086"}, 1384 + {"O025", "I087 Switch", "I087"}, 1385 + 1386 + {"O002", "I168 Switch", "I168"}, 1387 + {"O003", "I169 Switch", "I169"}, 1388 + 1389 + {"O034", "I168 Switch", "I168"}, 1390 + {"O035", "I168 Switch", "I168"}, 1391 + {"O035", "I169 Switch", "I169"}, 1392 + 1393 + {"O040", "I168 Switch", "I168"}, 1394 + {"O041", "I169 Switch", "I169"}, 1395 + }; 1396 + 1397 + static const char * const mt8188_afe_1x_en_sel_text[] = { 1398 + "a1sys_a2sys", "a3sys", "a4sys", 1399 + }; 1400 + 1401 + static const unsigned int mt8188_afe_1x_en_sel_values[] = { 1402 + 0, 1, 2, 1403 + }; 1404 + 1405 + static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, 1406 + A3_A4_TIMING_SEL1, 18, 0x3, 1407 + mt8188_afe_1x_en_sel_text, 1408 + mt8188_afe_1x_en_sel_values); 1409 + static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, 1410 + A3_A4_TIMING_SEL1, 20, 0x3, 1411 + mt8188_afe_1x_en_sel_text, 1412 + mt8188_afe_1x_en_sel_values); 1413 + static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, 1414 + A3_A4_TIMING_SEL1, 22, 0x3, 1415 + mt8188_afe_1x_en_sel_text, 1416 + mt8188_afe_1x_en_sel_values); 1417 + static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, 1418 + A3_A4_TIMING_SEL1, 24, 0x3, 1419 + mt8188_afe_1x_en_sel_text, 1420 + mt8188_afe_1x_en_sel_values); 1421 + static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, 1422 + A3_A4_TIMING_SEL1, 26, 0x3, 1423 + mt8188_afe_1x_en_sel_text, 1424 + mt8188_afe_1x_en_sel_values); 1425 + static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, 1426 + A3_A4_TIMING_SEL1, 28, 0x3, 1427 + mt8188_afe_1x_en_sel_text, 1428 + mt8188_afe_1x_en_sel_values); 1429 + static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, 1430 + A3_A4_TIMING_SEL1, 30, 0x3, 1431 + mt8188_afe_1x_en_sel_text, 1432 + mt8188_afe_1x_en_sel_values); 1433 + static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, 1434 + A3_A4_TIMING_SEL1, 0, 0x3, 1435 + mt8188_afe_1x_en_sel_text, 1436 + mt8188_afe_1x_en_sel_values); 1437 + static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, 1438 + A3_A4_TIMING_SEL1, 2, 0x3, 1439 + mt8188_afe_1x_en_sel_text, 1440 + mt8188_afe_1x_en_sel_values); 1441 + static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, 1442 + A3_A4_TIMING_SEL1, 4, 0x3, 1443 + mt8188_afe_1x_en_sel_text, 1444 + mt8188_afe_1x_en_sel_values); 1445 + static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, 1446 + A3_A4_TIMING_SEL1, 6, 0x3, 1447 + mt8188_afe_1x_en_sel_text, 1448 + mt8188_afe_1x_en_sel_values); 1449 + static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, 1450 + A3_A4_TIMING_SEL1, 8, 0x3, 1451 + mt8188_afe_1x_en_sel_text, 1452 + mt8188_afe_1x_en_sel_values); 1453 + static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, 1454 + A3_A4_TIMING_SEL1, 10, 0x3, 1455 + mt8188_afe_1x_en_sel_text, 1456 + mt8188_afe_1x_en_sel_values); 1457 + static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, 1458 + A3_A4_TIMING_SEL1, 12, 0x3, 1459 + mt8188_afe_1x_en_sel_text, 1460 + mt8188_afe_1x_en_sel_values); 1461 + static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, 1462 + A3_A4_TIMING_SEL1, 14, 0x3, 1463 + mt8188_afe_1x_en_sel_text, 1464 + mt8188_afe_1x_en_sel_values); 1465 + static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, 1466 + A3_A4_TIMING_SEL1, 16, 0x3, 1467 + mt8188_afe_1x_en_sel_text, 1468 + mt8188_afe_1x_en_sel_values); 1469 + 1470 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, 1471 + A3_A4_TIMING_SEL6, 0, 0x3, 1472 + mt8188_afe_1x_en_sel_text, 1473 + mt8188_afe_1x_en_sel_values); 1474 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, 1475 + A3_A4_TIMING_SEL6, 2, 0x3, 1476 + mt8188_afe_1x_en_sel_text, 1477 + mt8188_afe_1x_en_sel_values); 1478 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, 1479 + A3_A4_TIMING_SEL6, 4, 0x3, 1480 + mt8188_afe_1x_en_sel_text, 1481 + mt8188_afe_1x_en_sel_values); 1482 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, 1483 + A3_A4_TIMING_SEL6, 6, 0x3, 1484 + mt8188_afe_1x_en_sel_text, 1485 + mt8188_afe_1x_en_sel_values); 1486 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, 1487 + A3_A4_TIMING_SEL6, 8, 0x3, 1488 + mt8188_afe_1x_en_sel_text, 1489 + mt8188_afe_1x_en_sel_values); 1490 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, 1491 + A3_A4_TIMING_SEL6, 10, 0x3, 1492 + mt8188_afe_1x_en_sel_text, 1493 + mt8188_afe_1x_en_sel_values); 1494 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, 1495 + A3_A4_TIMING_SEL6, 12, 0x3, 1496 + mt8188_afe_1x_en_sel_text, 1497 + mt8188_afe_1x_en_sel_values); 1498 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, 1499 + A3_A4_TIMING_SEL6, 14, 0x3, 1500 + mt8188_afe_1x_en_sel_text, 1501 + mt8188_afe_1x_en_sel_values); 1502 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, 1503 + A3_A4_TIMING_SEL6, 16, 0x3, 1504 + mt8188_afe_1x_en_sel_text, 1505 + mt8188_afe_1x_en_sel_values); 1506 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, 1507 + A3_A4_TIMING_SEL6, 18, 0x3, 1508 + mt8188_afe_1x_en_sel_text, 1509 + mt8188_afe_1x_en_sel_values); 1510 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, 1511 + A3_A4_TIMING_SEL6, 20, 0x3, 1512 + mt8188_afe_1x_en_sel_text, 1513 + mt8188_afe_1x_en_sel_values); 1514 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, 1515 + A3_A4_TIMING_SEL6, 22, 0x3, 1516 + mt8188_afe_1x_en_sel_text, 1517 + mt8188_afe_1x_en_sel_values); 1518 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, 1519 + A3_A4_TIMING_SEL6, 24, 0x3, 1520 + mt8188_afe_1x_en_sel_text, 1521 + mt8188_afe_1x_en_sel_values); 1522 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, 1523 + A3_A4_TIMING_SEL6, 26, 0x3, 1524 + mt8188_afe_1x_en_sel_text, 1525 + mt8188_afe_1x_en_sel_values); 1526 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, 1527 + A3_A4_TIMING_SEL6, 28, 0x3, 1528 + mt8188_afe_1x_en_sel_text, 1529 + mt8188_afe_1x_en_sel_values); 1530 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, 1531 + A3_A4_TIMING_SEL6, 30, 0x3, 1532 + mt8188_afe_1x_en_sel_text, 1533 + mt8188_afe_1x_en_sel_values); 1534 + 1535 + static const char * const mt8188_afe_fs_timing_sel_text[] = { 1536 + "asys", 1537 + "etdmout1_1x_en", 1538 + "etdmout2_1x_en", 1539 + "etdmout3_1x_en", 1540 + "etdmin1_1x_en", 1541 + "etdmin2_1x_en", 1542 + "etdmin1_nx_en", 1543 + "etdmin2_nx_en", 1544 + }; 1545 + 1546 + static const unsigned int mt8188_afe_fs_timing_sel_values[] = { 1547 + 0, 1548 + MT8188_ETDM_OUT1_1X_EN, 1549 + MT8188_ETDM_OUT2_1X_EN, 1550 + MT8188_ETDM_OUT3_1X_EN, 1551 + MT8188_ETDM_IN1_1X_EN, 1552 + MT8188_ETDM_IN2_1X_EN, 1553 + MT8188_ETDM_IN1_NX_EN, 1554 + MT8188_ETDM_IN2_NX_EN, 1555 + }; 1556 + 1557 + static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum, 1558 + SND_SOC_NOPM, 0, 0, 1559 + mt8188_afe_fs_timing_sel_text, 1560 + mt8188_afe_fs_timing_sel_values); 1561 + static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum, 1562 + SND_SOC_NOPM, 0, 0, 1563 + mt8188_afe_fs_timing_sel_text, 1564 + mt8188_afe_fs_timing_sel_values); 1565 + static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum, 1566 + SND_SOC_NOPM, 0, 0, 1567 + mt8188_afe_fs_timing_sel_text, 1568 + mt8188_afe_fs_timing_sel_values); 1569 + static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum, 1570 + SND_SOC_NOPM, 0, 0, 1571 + mt8188_afe_fs_timing_sel_text, 1572 + mt8188_afe_fs_timing_sel_values); 1573 + static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum, 1574 + SND_SOC_NOPM, 0, 0, 1575 + mt8188_afe_fs_timing_sel_text, 1576 + mt8188_afe_fs_timing_sel_values); 1577 + static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum, 1578 + SND_SOC_NOPM, 0, 0, 1579 + mt8188_afe_fs_timing_sel_text, 1580 + mt8188_afe_fs_timing_sel_values); 1581 + static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum, 1582 + SND_SOC_NOPM, 0, 0, 1583 + mt8188_afe_fs_timing_sel_text, 1584 + mt8188_afe_fs_timing_sel_values); 1585 + static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum, 1586 + SND_SOC_NOPM, 0, 0, 1587 + mt8188_afe_fs_timing_sel_text, 1588 + mt8188_afe_fs_timing_sel_values); 1589 + static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum, 1590 + SND_SOC_NOPM, 0, 0, 1591 + mt8188_afe_fs_timing_sel_text, 1592 + mt8188_afe_fs_timing_sel_values); 1593 + static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum, 1594 + SND_SOC_NOPM, 0, 0, 1595 + mt8188_afe_fs_timing_sel_text, 1596 + mt8188_afe_fs_timing_sel_values); 1597 + 1598 + static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1599 + struct snd_ctl_elem_value *ucontrol) 1600 + { 1601 + struct snd_soc_component *component = 1602 + snd_soc_kcontrol_component(kcontrol); 1603 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1604 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1605 + struct mtk_dai_memif_priv *memif_priv; 1606 + unsigned int dai_id = kcontrol->id.device; 1607 + long val = ucontrol->value.integer.value[0]; 1608 + int ret = 0; 1609 + 1610 + memif_priv = afe_priv->dai_priv[dai_id]; 1611 + 1612 + if (val == memif_priv->asys_timing_sel) 1613 + return 0; 1614 + 1615 + ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1616 + 1617 + memif_priv->asys_timing_sel = val; 1618 + 1619 + return ret; 1620 + } 1621 + 1622 + static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1623 + struct snd_ctl_elem_value *ucontrol) 1624 + { 1625 + struct snd_soc_component *component = 1626 + snd_soc_kcontrol_component(kcontrol); 1627 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1628 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1629 + unsigned int id = kcontrol->id.device; 1630 + long val = ucontrol->value.integer.value[0]; 1631 + int ret = 0; 1632 + 1633 + if (val == afe_priv->irq_priv[id].asys_timing_sel) 1634 + return 0; 1635 + 1636 + ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1637 + 1638 + afe_priv->irq_priv[id].asys_timing_sel = val; 1639 + 1640 + return ret; 1641 + } 1642 + 1643 + static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol, 1644 + struct snd_ctl_elem_value *ucontrol) 1645 + { 1646 + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1647 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1648 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1649 + struct mtk_dai_memif_priv *memif_priv; 1650 + unsigned int dai_id = kcontrol->id.device; 1651 + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1652 + 1653 + memif_priv = afe_priv->dai_priv[dai_id]; 1654 + 1655 + ucontrol->value.enumerated.item[0] = 1656 + snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1657 + 1658 + return 0; 1659 + } 1660 + 1661 + static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol, 1662 + struct snd_ctl_elem_value *ucontrol) 1663 + { 1664 + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1665 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1666 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1667 + struct mtk_dai_memif_priv *memif_priv; 1668 + unsigned int dai_id = kcontrol->id.device; 1669 + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1670 + unsigned int *item = ucontrol->value.enumerated.item; 1671 + unsigned int prev_item = 0; 1672 + 1673 + if (item[0] >= e->items) 1674 + return -EINVAL; 1675 + 1676 + memif_priv = afe_priv->dai_priv[dai_id]; 1677 + 1678 + prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1679 + 1680 + if (item[0] == prev_item) 1681 + return 0; 1682 + 1683 + memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]); 1684 + 1685 + return 1; 1686 + } 1687 + 1688 + static const struct snd_kcontrol_new mt8188_memif_controls[] = { 1689 + MT8188_SOC_ENUM_EXT("dl2_1x_en_sel", 1690 + dl2_1x_en_sel_enum, 1691 + snd_soc_get_enum_double, 1692 + mt8188_memif_1x_en_sel_put, 1693 + MT8188_AFE_MEMIF_DL2), 1694 + MT8188_SOC_ENUM_EXT("dl3_1x_en_sel", 1695 + dl3_1x_en_sel_enum, 1696 + snd_soc_get_enum_double, 1697 + mt8188_memif_1x_en_sel_put, 1698 + MT8188_AFE_MEMIF_DL3), 1699 + MT8188_SOC_ENUM_EXT("dl6_1x_en_sel", 1700 + dl6_1x_en_sel_enum, 1701 + snd_soc_get_enum_double, 1702 + mt8188_memif_1x_en_sel_put, 1703 + MT8188_AFE_MEMIF_DL6), 1704 + MT8188_SOC_ENUM_EXT("dl7_1x_en_sel", 1705 + dl7_1x_en_sel_enum, 1706 + snd_soc_get_enum_double, 1707 + mt8188_memif_1x_en_sel_put, 1708 + MT8188_AFE_MEMIF_DL7), 1709 + MT8188_SOC_ENUM_EXT("dl8_1x_en_sel", 1710 + dl8_1x_en_sel_enum, 1711 + snd_soc_get_enum_double, 1712 + mt8188_memif_1x_en_sel_put, 1713 + MT8188_AFE_MEMIF_DL8), 1714 + MT8188_SOC_ENUM_EXT("dl10_1x_en_sel", 1715 + dl10_1x_en_sel_enum, 1716 + snd_soc_get_enum_double, 1717 + mt8188_memif_1x_en_sel_put, 1718 + MT8188_AFE_MEMIF_DL10), 1719 + MT8188_SOC_ENUM_EXT("dl11_1x_en_sel", 1720 + dl11_1x_en_sel_enum, 1721 + snd_soc_get_enum_double, 1722 + mt8188_memif_1x_en_sel_put, 1723 + MT8188_AFE_MEMIF_DL11), 1724 + MT8188_SOC_ENUM_EXT("ul1_1x_en_sel", 1725 + ul1_1x_en_sel_enum, 1726 + snd_soc_get_enum_double, 1727 + mt8188_memif_1x_en_sel_put, 1728 + MT8188_AFE_MEMIF_UL1), 1729 + MT8188_SOC_ENUM_EXT("ul2_1x_en_sel", 1730 + ul2_1x_en_sel_enum, 1731 + snd_soc_get_enum_double, 1732 + mt8188_memif_1x_en_sel_put, 1733 + MT8188_AFE_MEMIF_UL2), 1734 + MT8188_SOC_ENUM_EXT("ul3_1x_en_sel", 1735 + ul3_1x_en_sel_enum, 1736 + snd_soc_get_enum_double, 1737 + mt8188_memif_1x_en_sel_put, 1738 + MT8188_AFE_MEMIF_UL3), 1739 + MT8188_SOC_ENUM_EXT("ul4_1x_en_sel", 1740 + ul4_1x_en_sel_enum, 1741 + snd_soc_get_enum_double, 1742 + mt8188_memif_1x_en_sel_put, 1743 + MT8188_AFE_MEMIF_UL4), 1744 + MT8188_SOC_ENUM_EXT("ul5_1x_en_sel", 1745 + ul5_1x_en_sel_enum, 1746 + snd_soc_get_enum_double, 1747 + mt8188_memif_1x_en_sel_put, 1748 + MT8188_AFE_MEMIF_UL5), 1749 + MT8188_SOC_ENUM_EXT("ul6_1x_en_sel", 1750 + ul6_1x_en_sel_enum, 1751 + snd_soc_get_enum_double, 1752 + mt8188_memif_1x_en_sel_put, 1753 + MT8188_AFE_MEMIF_UL6), 1754 + MT8188_SOC_ENUM_EXT("ul8_1x_en_sel", 1755 + ul8_1x_en_sel_enum, 1756 + snd_soc_get_enum_double, 1757 + mt8188_memif_1x_en_sel_put, 1758 + MT8188_AFE_MEMIF_UL8), 1759 + MT8188_SOC_ENUM_EXT("ul9_1x_en_sel", 1760 + ul9_1x_en_sel_enum, 1761 + snd_soc_get_enum_double, 1762 + mt8188_memif_1x_en_sel_put, 1763 + MT8188_AFE_MEMIF_UL9), 1764 + MT8188_SOC_ENUM_EXT("ul10_1x_en_sel", 1765 + ul10_1x_en_sel_enum, 1766 + snd_soc_get_enum_double, 1767 + mt8188_memif_1x_en_sel_put, 1768 + MT8188_AFE_MEMIF_UL10), 1769 + MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel", 1770 + asys_irq1_1x_en_sel_enum, 1771 + snd_soc_get_enum_double, 1772 + mt8188_asys_irq_1x_en_sel_put, 1773 + MT8188_AFE_IRQ_13), 1774 + MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel", 1775 + asys_irq2_1x_en_sel_enum, 1776 + snd_soc_get_enum_double, 1777 + mt8188_asys_irq_1x_en_sel_put, 1778 + MT8188_AFE_IRQ_14), 1779 + MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel", 1780 + asys_irq3_1x_en_sel_enum, 1781 + snd_soc_get_enum_double, 1782 + mt8188_asys_irq_1x_en_sel_put, 1783 + MT8188_AFE_IRQ_15), 1784 + MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel", 1785 + asys_irq4_1x_en_sel_enum, 1786 + snd_soc_get_enum_double, 1787 + mt8188_asys_irq_1x_en_sel_put, 1788 + MT8188_AFE_IRQ_16), 1789 + MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel", 1790 + asys_irq5_1x_en_sel_enum, 1791 + snd_soc_get_enum_double, 1792 + mt8188_asys_irq_1x_en_sel_put, 1793 + MT8188_AFE_IRQ_17), 1794 + MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel", 1795 + asys_irq6_1x_en_sel_enum, 1796 + snd_soc_get_enum_double, 1797 + mt8188_asys_irq_1x_en_sel_put, 1798 + MT8188_AFE_IRQ_18), 1799 + MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel", 1800 + asys_irq7_1x_en_sel_enum, 1801 + snd_soc_get_enum_double, 1802 + mt8188_asys_irq_1x_en_sel_put, 1803 + MT8188_AFE_IRQ_19), 1804 + MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel", 1805 + asys_irq8_1x_en_sel_enum, 1806 + snd_soc_get_enum_double, 1807 + mt8188_asys_irq_1x_en_sel_put, 1808 + MT8188_AFE_IRQ_20), 1809 + MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel", 1810 + asys_irq9_1x_en_sel_enum, 1811 + snd_soc_get_enum_double, 1812 + mt8188_asys_irq_1x_en_sel_put, 1813 + MT8188_AFE_IRQ_21), 1814 + MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel", 1815 + asys_irq10_1x_en_sel_enum, 1816 + snd_soc_get_enum_double, 1817 + mt8188_asys_irq_1x_en_sel_put, 1818 + MT8188_AFE_IRQ_22), 1819 + MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel", 1820 + asys_irq11_1x_en_sel_enum, 1821 + snd_soc_get_enum_double, 1822 + mt8188_asys_irq_1x_en_sel_put, 1823 + MT8188_AFE_IRQ_23), 1824 + MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel", 1825 + asys_irq12_1x_en_sel_enum, 1826 + snd_soc_get_enum_double, 1827 + mt8188_asys_irq_1x_en_sel_put, 1828 + MT8188_AFE_IRQ_24), 1829 + MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel", 1830 + asys_irq13_1x_en_sel_enum, 1831 + snd_soc_get_enum_double, 1832 + mt8188_asys_irq_1x_en_sel_put, 1833 + MT8188_AFE_IRQ_25), 1834 + MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel", 1835 + asys_irq14_1x_en_sel_enum, 1836 + snd_soc_get_enum_double, 1837 + mt8188_asys_irq_1x_en_sel_put, 1838 + MT8188_AFE_IRQ_26), 1839 + MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel", 1840 + asys_irq15_1x_en_sel_enum, 1841 + snd_soc_get_enum_double, 1842 + mt8188_asys_irq_1x_en_sel_put, 1843 + MT8188_AFE_IRQ_27), 1844 + MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel", 1845 + asys_irq16_1x_en_sel_enum, 1846 + snd_soc_get_enum_double, 1847 + mt8188_asys_irq_1x_en_sel_put, 1848 + MT8188_AFE_IRQ_28), 1849 + MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel", 1850 + dl2_fs_timing_sel_enum, 1851 + mt8188_memif_fs_timing_sel_get, 1852 + mt8188_memif_fs_timing_sel_put, 1853 + MT8188_AFE_MEMIF_DL2), 1854 + MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel", 1855 + dl3_fs_timing_sel_enum, 1856 + mt8188_memif_fs_timing_sel_get, 1857 + mt8188_memif_fs_timing_sel_put, 1858 + MT8188_AFE_MEMIF_DL3), 1859 + MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel", 1860 + dl6_fs_timing_sel_enum, 1861 + mt8188_memif_fs_timing_sel_get, 1862 + mt8188_memif_fs_timing_sel_put, 1863 + MT8188_AFE_MEMIF_DL6), 1864 + MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel", 1865 + dl8_fs_timing_sel_enum, 1866 + mt8188_memif_fs_timing_sel_get, 1867 + mt8188_memif_fs_timing_sel_put, 1868 + MT8188_AFE_MEMIF_DL8), 1869 + MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel", 1870 + dl11_fs_timing_sel_enum, 1871 + mt8188_memif_fs_timing_sel_get, 1872 + mt8188_memif_fs_timing_sel_put, 1873 + MT8188_AFE_MEMIF_DL11), 1874 + MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel", 1875 + ul2_fs_timing_sel_enum, 1876 + mt8188_memif_fs_timing_sel_get, 1877 + mt8188_memif_fs_timing_sel_put, 1878 + MT8188_AFE_MEMIF_UL2), 1879 + MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel", 1880 + ul4_fs_timing_sel_enum, 1881 + mt8188_memif_fs_timing_sel_get, 1882 + mt8188_memif_fs_timing_sel_put, 1883 + MT8188_AFE_MEMIF_UL4), 1884 + MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel", 1885 + ul5_fs_timing_sel_enum, 1886 + mt8188_memif_fs_timing_sel_get, 1887 + mt8188_memif_fs_timing_sel_put, 1888 + MT8188_AFE_MEMIF_UL5), 1889 + MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel", 1890 + ul9_fs_timing_sel_enum, 1891 + mt8188_memif_fs_timing_sel_get, 1892 + mt8188_memif_fs_timing_sel_put, 1893 + MT8188_AFE_MEMIF_UL9), 1894 + MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel", 1895 + ul10_fs_timing_sel_enum, 1896 + mt8188_memif_fs_timing_sel_get, 1897 + mt8188_memif_fs_timing_sel_put, 1898 + MT8188_AFE_MEMIF_UL10), 1899 + }; 1900 + 1901 + static const struct snd_soc_component_driver mt8188_afe_pcm_dai_component = { 1902 + .name = "mt8188-afe-pcm-dai", 1903 + }; 1904 + 1905 + static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = { 1906 + [MT8188_AFE_MEMIF_DL2] = { 1907 + .name = "DL2", 1908 + .id = MT8188_AFE_MEMIF_DL2, 1909 + .reg_ofs_base = AFE_DL2_BASE, 1910 + .reg_ofs_cur = AFE_DL2_CUR, 1911 + .reg_ofs_end = AFE_DL2_END, 1912 + .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1913 + .fs_shift = 10, 1914 + .fs_maskbit = 0x1f, 1915 + .mono_reg = -1, 1916 + .mono_shift = 0, 1917 + .int_odd_flag_reg = -1, 1918 + .int_odd_flag_shift = 0, 1919 + .enable_reg = AFE_DAC_CON0, 1920 + .enable_shift = 18, 1921 + .hd_reg = AFE_DL2_CON0, 1922 + .hd_shift = 5, 1923 + .agent_disable_reg = AUDIO_TOP_CON5, 1924 + .agent_disable_shift = 18, 1925 + .ch_num_reg = AFE_DL2_CON0, 1926 + .ch_num_shift = 0, 1927 + .ch_num_maskbit = 0x1f, 1928 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1929 + .msb_shift = 18, 1930 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1931 + .msb_end_shift = 18, 1932 + }, 1933 + [MT8188_AFE_MEMIF_DL3] = { 1934 + .name = "DL3", 1935 + .id = MT8188_AFE_MEMIF_DL3, 1936 + .reg_ofs_base = AFE_DL3_BASE, 1937 + .reg_ofs_cur = AFE_DL3_CUR, 1938 + .reg_ofs_end = AFE_DL3_END, 1939 + .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1940 + .fs_shift = 15, 1941 + .fs_maskbit = 0x1f, 1942 + .mono_reg = -1, 1943 + .mono_shift = 0, 1944 + .int_odd_flag_reg = -1, 1945 + .int_odd_flag_shift = 0, 1946 + .enable_reg = AFE_DAC_CON0, 1947 + .enable_shift = 19, 1948 + .hd_reg = AFE_DL3_CON0, 1949 + .hd_shift = 5, 1950 + .agent_disable_reg = AUDIO_TOP_CON5, 1951 + .agent_disable_shift = 19, 1952 + .ch_num_reg = AFE_DL3_CON0, 1953 + .ch_num_shift = 0, 1954 + .ch_num_maskbit = 0x1f, 1955 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1956 + .msb_shift = 19, 1957 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1958 + .msb_end_shift = 19, 1959 + }, 1960 + [MT8188_AFE_MEMIF_DL6] = { 1961 + .name = "DL6", 1962 + .id = MT8188_AFE_MEMIF_DL6, 1963 + .reg_ofs_base = AFE_DL6_BASE, 1964 + .reg_ofs_cur = AFE_DL6_CUR, 1965 + .reg_ofs_end = AFE_DL6_END, 1966 + .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1967 + .fs_shift = 0, 1968 + .fs_maskbit = 0x1f, 1969 + .mono_reg = -1, 1970 + .mono_shift = 0, 1971 + .int_odd_flag_reg = -1, 1972 + .int_odd_flag_shift = 0, 1973 + .enable_reg = AFE_DAC_CON0, 1974 + .enable_shift = 22, 1975 + .hd_reg = AFE_DL6_CON0, 1976 + .hd_shift = 5, 1977 + .agent_disable_reg = AUDIO_TOP_CON5, 1978 + .agent_disable_shift = 22, 1979 + .ch_num_reg = AFE_DL6_CON0, 1980 + .ch_num_shift = 0, 1981 + .ch_num_maskbit = 0x1f, 1982 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1983 + .msb_shift = 22, 1984 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1985 + .msb_end_shift = 22, 1986 + }, 1987 + [MT8188_AFE_MEMIF_DL7] = { 1988 + .name = "DL7", 1989 + .id = MT8188_AFE_MEMIF_DL7, 1990 + .reg_ofs_base = AFE_DL7_BASE, 1991 + .reg_ofs_cur = AFE_DL7_CUR, 1992 + .reg_ofs_end = AFE_DL7_END, 1993 + .fs_reg = -1, 1994 + .fs_shift = 0, 1995 + .fs_maskbit = 0, 1996 + .mono_reg = -1, 1997 + .mono_shift = 0, 1998 + .int_odd_flag_reg = -1, 1999 + .int_odd_flag_shift = 0, 2000 + .enable_reg = AFE_DAC_CON0, 2001 + .enable_shift = 23, 2002 + .hd_reg = AFE_DL7_CON0, 2003 + .hd_shift = 5, 2004 + .agent_disable_reg = AUDIO_TOP_CON5, 2005 + .agent_disable_shift = 23, 2006 + .ch_num_reg = AFE_DL7_CON0, 2007 + .ch_num_shift = 0, 2008 + .ch_num_maskbit = 0x1f, 2009 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2010 + .msb_shift = 23, 2011 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2012 + .msb_end_shift = 23, 2013 + }, 2014 + [MT8188_AFE_MEMIF_DL8] = { 2015 + .name = "DL8", 2016 + .id = MT8188_AFE_MEMIF_DL8, 2017 + .reg_ofs_base = AFE_DL8_BASE, 2018 + .reg_ofs_cur = AFE_DL8_CUR, 2019 + .reg_ofs_end = AFE_DL8_END, 2020 + .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2021 + .fs_shift = 10, 2022 + .fs_maskbit = 0x1f, 2023 + .mono_reg = -1, 2024 + .mono_shift = 0, 2025 + .int_odd_flag_reg = -1, 2026 + .int_odd_flag_shift = 0, 2027 + .enable_reg = AFE_DAC_CON0, 2028 + .enable_shift = 24, 2029 + .hd_reg = AFE_DL8_CON0, 2030 + .hd_shift = 6, 2031 + .agent_disable_reg = AUDIO_TOP_CON5, 2032 + .agent_disable_shift = 24, 2033 + .ch_num_reg = AFE_DL8_CON0, 2034 + .ch_num_shift = 0, 2035 + .ch_num_maskbit = 0x3f, 2036 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2037 + .msb_shift = 24, 2038 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2039 + .msb_end_shift = 24, 2040 + }, 2041 + [MT8188_AFE_MEMIF_DL10] = { 2042 + .name = "DL10", 2043 + .id = MT8188_AFE_MEMIF_DL10, 2044 + .reg_ofs_base = AFE_DL10_BASE, 2045 + .reg_ofs_cur = AFE_DL10_CUR, 2046 + .reg_ofs_end = AFE_DL10_END, 2047 + .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2048 + .fs_shift = 20, 2049 + .fs_maskbit = 0x1f, 2050 + .mono_reg = -1, 2051 + .mono_shift = 0, 2052 + .int_odd_flag_reg = -1, 2053 + .int_odd_flag_shift = 0, 2054 + .enable_reg = AFE_DAC_CON0, 2055 + .enable_shift = 26, 2056 + .hd_reg = AFE_DL10_CON0, 2057 + .hd_shift = 5, 2058 + .agent_disable_reg = AUDIO_TOP_CON5, 2059 + .agent_disable_shift = 26, 2060 + .ch_num_reg = AFE_DL10_CON0, 2061 + .ch_num_shift = 0, 2062 + .ch_num_maskbit = 0x1f, 2063 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2064 + .msb_shift = 26, 2065 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2066 + .msb_end_shift = 26, 2067 + }, 2068 + [MT8188_AFE_MEMIF_DL11] = { 2069 + .name = "DL11", 2070 + .id = MT8188_AFE_MEMIF_DL11, 2071 + .reg_ofs_base = AFE_DL11_BASE, 2072 + .reg_ofs_cur = AFE_DL11_CUR, 2073 + .reg_ofs_end = AFE_DL11_END, 2074 + .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2075 + .fs_shift = 25, 2076 + .fs_maskbit = 0x1f, 2077 + .mono_reg = -1, 2078 + .mono_shift = 0, 2079 + .int_odd_flag_reg = -1, 2080 + .int_odd_flag_shift = 0, 2081 + .enable_reg = AFE_DAC_CON0, 2082 + .enable_shift = 27, 2083 + .hd_reg = AFE_DL11_CON0, 2084 + .hd_shift = 7, 2085 + .agent_disable_reg = AUDIO_TOP_CON5, 2086 + .agent_disable_shift = 27, 2087 + .ch_num_reg = AFE_DL11_CON0, 2088 + .ch_num_shift = 0, 2089 + .ch_num_maskbit = 0x7f, 2090 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2091 + .msb_shift = 27, 2092 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2093 + .msb_end_shift = 27, 2094 + }, 2095 + [MT8188_AFE_MEMIF_UL1] = { 2096 + .name = "UL1", 2097 + .id = MT8188_AFE_MEMIF_UL1, 2098 + .reg_ofs_base = AFE_UL1_BASE, 2099 + .reg_ofs_cur = AFE_UL1_CUR, 2100 + .reg_ofs_end = AFE_UL1_END, 2101 + .fs_reg = -1, 2102 + .fs_shift = 0, 2103 + .fs_maskbit = 0, 2104 + .mono_reg = AFE_UL1_CON0, 2105 + .mono_shift = 1, 2106 + .int_odd_flag_reg = AFE_UL1_CON0, 2107 + .int_odd_flag_shift = 0, 2108 + .enable_reg = AFE_DAC_CON0, 2109 + .enable_shift = 1, 2110 + .hd_reg = AFE_UL1_CON0, 2111 + .hd_shift = 5, 2112 + .agent_disable_reg = AUDIO_TOP_CON5, 2113 + .agent_disable_shift = 0, 2114 + .ch_num_reg = -1, 2115 + .ch_num_shift = 0, 2116 + .ch_num_maskbit = 0, 2117 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2118 + .msb_shift = 0, 2119 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2120 + .msb_end_shift = 0, 2121 + }, 2122 + [MT8188_AFE_MEMIF_UL2] = { 2123 + .name = "UL2", 2124 + .id = MT8188_AFE_MEMIF_UL2, 2125 + .reg_ofs_base = AFE_UL2_BASE, 2126 + .reg_ofs_cur = AFE_UL2_CUR, 2127 + .reg_ofs_end = AFE_UL2_END, 2128 + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2129 + .fs_shift = 5, 2130 + .fs_maskbit = 0x1f, 2131 + .mono_reg = AFE_UL2_CON0, 2132 + .mono_shift = 1, 2133 + .int_odd_flag_reg = AFE_UL2_CON0, 2134 + .int_odd_flag_shift = 0, 2135 + .enable_reg = AFE_DAC_CON0, 2136 + .enable_shift = 2, 2137 + .hd_reg = AFE_UL2_CON0, 2138 + .hd_shift = 5, 2139 + .agent_disable_reg = AUDIO_TOP_CON5, 2140 + .agent_disable_shift = 1, 2141 + .ch_num_reg = -1, 2142 + .ch_num_shift = 0, 2143 + .ch_num_maskbit = 0, 2144 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2145 + .msb_shift = 1, 2146 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2147 + .msb_end_shift = 1, 2148 + }, 2149 + [MT8188_AFE_MEMIF_UL3] = { 2150 + .name = "UL3", 2151 + .id = MT8188_AFE_MEMIF_UL3, 2152 + .reg_ofs_base = AFE_UL3_BASE, 2153 + .reg_ofs_cur = AFE_UL3_CUR, 2154 + .reg_ofs_end = AFE_UL3_END, 2155 + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2156 + .fs_shift = 10, 2157 + .fs_maskbit = 0x1f, 2158 + .mono_reg = AFE_UL3_CON0, 2159 + .mono_shift = 1, 2160 + .int_odd_flag_reg = AFE_UL3_CON0, 2161 + .int_odd_flag_shift = 0, 2162 + .enable_reg = AFE_DAC_CON0, 2163 + .enable_shift = 3, 2164 + .hd_reg = AFE_UL3_CON0, 2165 + .hd_shift = 5, 2166 + .agent_disable_reg = AUDIO_TOP_CON5, 2167 + .agent_disable_shift = 2, 2168 + .ch_num_reg = -1, 2169 + .ch_num_shift = 0, 2170 + .ch_num_maskbit = 0, 2171 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2172 + .msb_shift = 2, 2173 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2174 + .msb_end_shift = 2, 2175 + }, 2176 + [MT8188_AFE_MEMIF_UL4] = { 2177 + .name = "UL4", 2178 + .id = MT8188_AFE_MEMIF_UL4, 2179 + .reg_ofs_base = AFE_UL4_BASE, 2180 + .reg_ofs_cur = AFE_UL4_CUR, 2181 + .reg_ofs_end = AFE_UL4_END, 2182 + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2183 + .fs_shift = 15, 2184 + .fs_maskbit = 0x1f, 2185 + .mono_reg = AFE_UL4_CON0, 2186 + .mono_shift = 1, 2187 + .int_odd_flag_reg = AFE_UL4_CON0, 2188 + .int_odd_flag_shift = 0, 2189 + .enable_reg = AFE_DAC_CON0, 2190 + .enable_shift = 4, 2191 + .hd_reg = AFE_UL4_CON0, 2192 + .hd_shift = 5, 2193 + .agent_disable_reg = AUDIO_TOP_CON5, 2194 + .agent_disable_shift = 3, 2195 + .ch_num_reg = -1, 2196 + .ch_num_shift = 0, 2197 + .ch_num_maskbit = 0, 2198 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2199 + .msb_shift = 3, 2200 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2201 + .msb_end_shift = 3, 2202 + }, 2203 + [MT8188_AFE_MEMIF_UL5] = { 2204 + .name = "UL5", 2205 + .id = MT8188_AFE_MEMIF_UL5, 2206 + .reg_ofs_base = AFE_UL5_BASE, 2207 + .reg_ofs_cur = AFE_UL5_CUR, 2208 + .reg_ofs_end = AFE_UL5_END, 2209 + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2210 + .fs_shift = 20, 2211 + .fs_maskbit = 0x1f, 2212 + .mono_reg = AFE_UL5_CON0, 2213 + .mono_shift = 1, 2214 + .int_odd_flag_reg = AFE_UL5_CON0, 2215 + .int_odd_flag_shift = 0, 2216 + .enable_reg = AFE_DAC_CON0, 2217 + .enable_shift = 5, 2218 + .hd_reg = AFE_UL5_CON0, 2219 + .hd_shift = 5, 2220 + .agent_disable_reg = AUDIO_TOP_CON5, 2221 + .agent_disable_shift = 4, 2222 + .ch_num_reg = -1, 2223 + .ch_num_shift = 0, 2224 + .ch_num_maskbit = 0, 2225 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2226 + .msb_shift = 4, 2227 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2228 + .msb_end_shift = 4, 2229 + }, 2230 + [MT8188_AFE_MEMIF_UL6] = { 2231 + .name = "UL6", 2232 + .id = MT8188_AFE_MEMIF_UL6, 2233 + .reg_ofs_base = AFE_UL6_BASE, 2234 + .reg_ofs_cur = AFE_UL6_CUR, 2235 + .reg_ofs_end = AFE_UL6_END, 2236 + .fs_reg = -1, 2237 + .fs_shift = 0, 2238 + .fs_maskbit = 0, 2239 + .mono_reg = AFE_UL6_CON0, 2240 + .mono_shift = 1, 2241 + .int_odd_flag_reg = AFE_UL6_CON0, 2242 + .int_odd_flag_shift = 0, 2243 + .enable_reg = AFE_DAC_CON0, 2244 + .enable_shift = 6, 2245 + .hd_reg = AFE_UL6_CON0, 2246 + .hd_shift = 5, 2247 + .agent_disable_reg = AUDIO_TOP_CON5, 2248 + .agent_disable_shift = 5, 2249 + .ch_num_reg = -1, 2250 + .ch_num_shift = 0, 2251 + .ch_num_maskbit = 0, 2252 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2253 + .msb_shift = 5, 2254 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2255 + .msb_end_shift = 5, 2256 + }, 2257 + [MT8188_AFE_MEMIF_UL8] = { 2258 + .name = "UL8", 2259 + .id = MT8188_AFE_MEMIF_UL8, 2260 + .reg_ofs_base = AFE_UL8_BASE, 2261 + .reg_ofs_cur = AFE_UL8_CUR, 2262 + .reg_ofs_end = AFE_UL8_END, 2263 + .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2264 + .fs_shift = 5, 2265 + .fs_maskbit = 0x1f, 2266 + .mono_reg = AFE_UL8_CON0, 2267 + .mono_shift = 1, 2268 + .int_odd_flag_reg = AFE_UL8_CON0, 2269 + .int_odd_flag_shift = 0, 2270 + .enable_reg = AFE_DAC_CON0, 2271 + .enable_shift = 8, 2272 + .hd_reg = AFE_UL8_CON0, 2273 + .hd_shift = 5, 2274 + .agent_disable_reg = AUDIO_TOP_CON5, 2275 + .agent_disable_shift = 7, 2276 + .ch_num_reg = -1, 2277 + .ch_num_shift = 0, 2278 + .ch_num_maskbit = 0, 2279 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2280 + .msb_shift = 7, 2281 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2282 + .msb_end_shift = 7, 2283 + }, 2284 + [MT8188_AFE_MEMIF_UL9] = { 2285 + .name = "UL9", 2286 + .id = MT8188_AFE_MEMIF_UL9, 2287 + .reg_ofs_base = AFE_UL9_BASE, 2288 + .reg_ofs_cur = AFE_UL9_CUR, 2289 + .reg_ofs_end = AFE_UL9_END, 2290 + .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2291 + .fs_shift = 10, 2292 + .fs_maskbit = 0x1f, 2293 + .mono_reg = AFE_UL9_CON0, 2294 + .mono_shift = 1, 2295 + .int_odd_flag_reg = AFE_UL9_CON0, 2296 + .int_odd_flag_shift = 0, 2297 + .enable_reg = AFE_DAC_CON0, 2298 + .enable_shift = 9, 2299 + .hd_reg = AFE_UL9_CON0, 2300 + .hd_shift = 5, 2301 + .agent_disable_reg = AUDIO_TOP_CON5, 2302 + .agent_disable_shift = 8, 2303 + .ch_num_reg = -1, 2304 + .ch_num_shift = 0, 2305 + .ch_num_maskbit = 0, 2306 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2307 + .msb_shift = 8, 2308 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2309 + .msb_end_shift = 8, 2310 + }, 2311 + [MT8188_AFE_MEMIF_UL10] = { 2312 + .name = "UL10", 2313 + .id = MT8188_AFE_MEMIF_UL10, 2314 + .reg_ofs_base = AFE_UL10_BASE, 2315 + .reg_ofs_cur = AFE_UL10_CUR, 2316 + .reg_ofs_end = AFE_UL10_END, 2317 + .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2318 + .fs_shift = 15, 2319 + .fs_maskbit = 0x1f, 2320 + .mono_reg = AFE_UL10_CON0, 2321 + .mono_shift = 1, 2322 + .int_odd_flag_reg = AFE_UL10_CON0, 2323 + .int_odd_flag_shift = 0, 2324 + .enable_reg = AFE_DAC_CON0, 2325 + .enable_shift = 10, 2326 + .hd_reg = AFE_UL10_CON0, 2327 + .hd_shift = 5, 2328 + .agent_disable_reg = AUDIO_TOP_CON5, 2329 + .agent_disable_shift = 9, 2330 + .ch_num_reg = -1, 2331 + .ch_num_shift = 0, 2332 + .ch_num_maskbit = 0, 2333 + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2334 + .msb_shift = 9, 2335 + .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2336 + .msb_end_shift = 9, 2337 + }, 2338 + }; 2339 + 2340 + static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = { 2341 + [MT8188_AFE_IRQ_1] = { 2342 + .id = MT8188_AFE_IRQ_1, 2343 + .irq_cnt_reg = -1, 2344 + .irq_cnt_shift = 0, 2345 + .irq_cnt_maskbit = 0, 2346 + .irq_fs_reg = -1, 2347 + .irq_fs_shift = 0, 2348 + .irq_fs_maskbit = 0, 2349 + .irq_en_reg = AFE_IRQ1_CON, 2350 + .irq_en_shift = 31, 2351 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2352 + .irq_clr_shift = 0, 2353 + .irq_status_shift = 16, 2354 + }, 2355 + [MT8188_AFE_IRQ_2] = { 2356 + .id = MT8188_AFE_IRQ_2, 2357 + .irq_cnt_reg = -1, 2358 + .irq_cnt_shift = 0, 2359 + .irq_cnt_maskbit = 0, 2360 + .irq_fs_reg = -1, 2361 + .irq_fs_shift = 0, 2362 + .irq_fs_maskbit = 0, 2363 + .irq_en_reg = AFE_IRQ2_CON, 2364 + .irq_en_shift = 31, 2365 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2366 + .irq_clr_shift = 1, 2367 + .irq_status_shift = 17, 2368 + }, 2369 + [MT8188_AFE_IRQ_3] = { 2370 + .id = MT8188_AFE_IRQ_3, 2371 + .irq_cnt_reg = AFE_IRQ3_CON, 2372 + .irq_cnt_shift = 0, 2373 + .irq_cnt_maskbit = 0xffffff, 2374 + .irq_fs_reg = -1, 2375 + .irq_fs_shift = 0, 2376 + .irq_fs_maskbit = 0, 2377 + .irq_en_reg = AFE_IRQ3_CON, 2378 + .irq_en_shift = 31, 2379 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2380 + .irq_clr_shift = 2, 2381 + .irq_status_shift = 18, 2382 + }, 2383 + [MT8188_AFE_IRQ_8] = { 2384 + .id = MT8188_AFE_IRQ_8, 2385 + .irq_cnt_reg = -1, 2386 + .irq_cnt_shift = 0, 2387 + .irq_cnt_maskbit = 0, 2388 + .irq_fs_reg = -1, 2389 + .irq_fs_shift = 0, 2390 + .irq_fs_maskbit = 0, 2391 + .irq_en_reg = AFE_IRQ8_CON, 2392 + .irq_en_shift = 31, 2393 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2394 + .irq_clr_shift = 7, 2395 + .irq_status_shift = 23, 2396 + }, 2397 + [MT8188_AFE_IRQ_9] = { 2398 + .id = MT8188_AFE_IRQ_9, 2399 + .irq_cnt_reg = AFE_IRQ9_CON, 2400 + .irq_cnt_shift = 0, 2401 + .irq_cnt_maskbit = 0xffffff, 2402 + .irq_fs_reg = -1, 2403 + .irq_fs_shift = 0, 2404 + .irq_fs_maskbit = 0, 2405 + .irq_en_reg = AFE_IRQ9_CON, 2406 + .irq_en_shift = 31, 2407 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2408 + .irq_clr_shift = 8, 2409 + .irq_status_shift = 24, 2410 + }, 2411 + [MT8188_AFE_IRQ_10] = { 2412 + .id = MT8188_AFE_IRQ_10, 2413 + .irq_cnt_reg = -1, 2414 + .irq_cnt_shift = 0, 2415 + .irq_cnt_maskbit = 0, 2416 + .irq_fs_reg = -1, 2417 + .irq_fs_shift = 0, 2418 + .irq_fs_maskbit = 0, 2419 + .irq_en_reg = AFE_IRQ10_CON, 2420 + .irq_en_shift = 31, 2421 + .irq_clr_reg = AFE_IRQ_MCU_CLR, 2422 + .irq_clr_shift = 9, 2423 + .irq_status_shift = 25, 2424 + }, 2425 + [MT8188_AFE_IRQ_13] = { 2426 + .id = MT8188_AFE_IRQ_13, 2427 + .irq_cnt_reg = ASYS_IRQ1_CON, 2428 + .irq_cnt_shift = 0, 2429 + .irq_cnt_maskbit = 0xffffff, 2430 + .irq_fs_reg = ASYS_IRQ1_CON, 2431 + .irq_fs_shift = 24, 2432 + .irq_fs_maskbit = 0x1ffff, 2433 + .irq_en_reg = ASYS_IRQ1_CON, 2434 + .irq_en_shift = 31, 2435 + .irq_clr_reg = ASYS_IRQ_CLR, 2436 + .irq_clr_shift = 0, 2437 + .irq_status_shift = 0, 2438 + }, 2439 + [MT8188_AFE_IRQ_14] = { 2440 + .id = MT8188_AFE_IRQ_14, 2441 + .irq_cnt_reg = ASYS_IRQ2_CON, 2442 + .irq_cnt_shift = 0, 2443 + .irq_cnt_maskbit = 0xffffff, 2444 + .irq_fs_reg = ASYS_IRQ2_CON, 2445 + .irq_fs_shift = 24, 2446 + .irq_fs_maskbit = 0x1ffff, 2447 + .irq_en_reg = ASYS_IRQ2_CON, 2448 + .irq_en_shift = 31, 2449 + .irq_clr_reg = ASYS_IRQ_CLR, 2450 + .irq_clr_shift = 1, 2451 + .irq_status_shift = 1, 2452 + }, 2453 + [MT8188_AFE_IRQ_15] = { 2454 + .id = MT8188_AFE_IRQ_15, 2455 + .irq_cnt_reg = ASYS_IRQ3_CON, 2456 + .irq_cnt_shift = 0, 2457 + .irq_cnt_maskbit = 0xffffff, 2458 + .irq_fs_reg = ASYS_IRQ3_CON, 2459 + .irq_fs_shift = 24, 2460 + .irq_fs_maskbit = 0x1ffff, 2461 + .irq_en_reg = ASYS_IRQ3_CON, 2462 + .irq_en_shift = 31, 2463 + .irq_clr_reg = ASYS_IRQ_CLR, 2464 + .irq_clr_shift = 2, 2465 + .irq_status_shift = 2, 2466 + }, 2467 + [MT8188_AFE_IRQ_16] = { 2468 + .id = MT8188_AFE_IRQ_16, 2469 + .irq_cnt_reg = ASYS_IRQ4_CON, 2470 + .irq_cnt_shift = 0, 2471 + .irq_cnt_maskbit = 0xffffff, 2472 + .irq_fs_reg = ASYS_IRQ4_CON, 2473 + .irq_fs_shift = 24, 2474 + .irq_fs_maskbit = 0x1ffff, 2475 + .irq_en_reg = ASYS_IRQ4_CON, 2476 + .irq_en_shift = 31, 2477 + .irq_clr_reg = ASYS_IRQ_CLR, 2478 + .irq_clr_shift = 3, 2479 + .irq_status_shift = 3, 2480 + }, 2481 + [MT8188_AFE_IRQ_17] = { 2482 + .id = MT8188_AFE_IRQ_17, 2483 + .irq_cnt_reg = ASYS_IRQ5_CON, 2484 + .irq_cnt_shift = 0, 2485 + .irq_cnt_maskbit = 0xffffff, 2486 + .irq_fs_reg = ASYS_IRQ5_CON, 2487 + .irq_fs_shift = 24, 2488 + .irq_fs_maskbit = 0x1ffff, 2489 + .irq_en_reg = ASYS_IRQ5_CON, 2490 + .irq_en_shift = 31, 2491 + .irq_clr_reg = ASYS_IRQ_CLR, 2492 + .irq_clr_shift = 4, 2493 + .irq_status_shift = 4, 2494 + }, 2495 + [MT8188_AFE_IRQ_18] = { 2496 + .id = MT8188_AFE_IRQ_18, 2497 + .irq_cnt_reg = ASYS_IRQ6_CON, 2498 + .irq_cnt_shift = 0, 2499 + .irq_cnt_maskbit = 0xffffff, 2500 + .irq_fs_reg = ASYS_IRQ6_CON, 2501 + .irq_fs_shift = 24, 2502 + .irq_fs_maskbit = 0x1ffff, 2503 + .irq_en_reg = ASYS_IRQ6_CON, 2504 + .irq_en_shift = 31, 2505 + .irq_clr_reg = ASYS_IRQ_CLR, 2506 + .irq_clr_shift = 5, 2507 + .irq_status_shift = 5, 2508 + }, 2509 + [MT8188_AFE_IRQ_19] = { 2510 + .id = MT8188_AFE_IRQ_19, 2511 + .irq_cnt_reg = ASYS_IRQ7_CON, 2512 + .irq_cnt_shift = 0, 2513 + .irq_cnt_maskbit = 0xffffff, 2514 + .irq_fs_reg = ASYS_IRQ7_CON, 2515 + .irq_fs_shift = 24, 2516 + .irq_fs_maskbit = 0x1ffff, 2517 + .irq_en_reg = ASYS_IRQ7_CON, 2518 + .irq_en_shift = 31, 2519 + .irq_clr_reg = ASYS_IRQ_CLR, 2520 + .irq_clr_shift = 6, 2521 + .irq_status_shift = 6, 2522 + }, 2523 + [MT8188_AFE_IRQ_20] = { 2524 + .id = MT8188_AFE_IRQ_20, 2525 + .irq_cnt_reg = ASYS_IRQ8_CON, 2526 + .irq_cnt_shift = 0, 2527 + .irq_cnt_maskbit = 0xffffff, 2528 + .irq_fs_reg = ASYS_IRQ8_CON, 2529 + .irq_fs_shift = 24, 2530 + .irq_fs_maskbit = 0x1ffff, 2531 + .irq_en_reg = ASYS_IRQ8_CON, 2532 + .irq_en_shift = 31, 2533 + .irq_clr_reg = ASYS_IRQ_CLR, 2534 + .irq_clr_shift = 7, 2535 + .irq_status_shift = 7, 2536 + }, 2537 + [MT8188_AFE_IRQ_21] = { 2538 + .id = MT8188_AFE_IRQ_21, 2539 + .irq_cnt_reg = ASYS_IRQ9_CON, 2540 + .irq_cnt_shift = 0, 2541 + .irq_cnt_maskbit = 0xffffff, 2542 + .irq_fs_reg = ASYS_IRQ9_CON, 2543 + .irq_fs_shift = 24, 2544 + .irq_fs_maskbit = 0x1ffff, 2545 + .irq_en_reg = ASYS_IRQ9_CON, 2546 + .irq_en_shift = 31, 2547 + .irq_clr_reg = ASYS_IRQ_CLR, 2548 + .irq_clr_shift = 8, 2549 + .irq_status_shift = 8, 2550 + }, 2551 + [MT8188_AFE_IRQ_22] = { 2552 + .id = MT8188_AFE_IRQ_22, 2553 + .irq_cnt_reg = ASYS_IRQ10_CON, 2554 + .irq_cnt_shift = 0, 2555 + .irq_cnt_maskbit = 0xffffff, 2556 + .irq_fs_reg = ASYS_IRQ10_CON, 2557 + .irq_fs_shift = 24, 2558 + .irq_fs_maskbit = 0x1ffff, 2559 + .irq_en_reg = ASYS_IRQ10_CON, 2560 + .irq_en_shift = 31, 2561 + .irq_clr_reg = ASYS_IRQ_CLR, 2562 + .irq_clr_shift = 9, 2563 + .irq_status_shift = 9, 2564 + }, 2565 + [MT8188_AFE_IRQ_23] = { 2566 + .id = MT8188_AFE_IRQ_23, 2567 + .irq_cnt_reg = ASYS_IRQ11_CON, 2568 + .irq_cnt_shift = 0, 2569 + .irq_cnt_maskbit = 0xffffff, 2570 + .irq_fs_reg = ASYS_IRQ11_CON, 2571 + .irq_fs_shift = 24, 2572 + .irq_fs_maskbit = 0x1ffff, 2573 + .irq_en_reg = ASYS_IRQ11_CON, 2574 + .irq_en_shift = 31, 2575 + .irq_clr_reg = ASYS_IRQ_CLR, 2576 + .irq_clr_shift = 10, 2577 + .irq_status_shift = 10, 2578 + }, 2579 + [MT8188_AFE_IRQ_24] = { 2580 + .id = MT8188_AFE_IRQ_24, 2581 + .irq_cnt_reg = ASYS_IRQ12_CON, 2582 + .irq_cnt_shift = 0, 2583 + .irq_cnt_maskbit = 0xffffff, 2584 + .irq_fs_reg = ASYS_IRQ12_CON, 2585 + .irq_fs_shift = 24, 2586 + .irq_fs_maskbit = 0x1ffff, 2587 + .irq_en_reg = ASYS_IRQ12_CON, 2588 + .irq_en_shift = 31, 2589 + .irq_clr_reg = ASYS_IRQ_CLR, 2590 + .irq_clr_shift = 11, 2591 + .irq_status_shift = 11, 2592 + }, 2593 + [MT8188_AFE_IRQ_25] = { 2594 + .id = MT8188_AFE_IRQ_25, 2595 + .irq_cnt_reg = ASYS_IRQ13_CON, 2596 + .irq_cnt_shift = 0, 2597 + .irq_cnt_maskbit = 0xffffff, 2598 + .irq_fs_reg = ASYS_IRQ13_CON, 2599 + .irq_fs_shift = 24, 2600 + .irq_fs_maskbit = 0x1ffff, 2601 + .irq_en_reg = ASYS_IRQ13_CON, 2602 + .irq_en_shift = 31, 2603 + .irq_clr_reg = ASYS_IRQ_CLR, 2604 + .irq_clr_shift = 12, 2605 + .irq_status_shift = 12, 2606 + }, 2607 + [MT8188_AFE_IRQ_26] = { 2608 + .id = MT8188_AFE_IRQ_26, 2609 + .irq_cnt_reg = ASYS_IRQ14_CON, 2610 + .irq_cnt_shift = 0, 2611 + .irq_cnt_maskbit = 0xffffff, 2612 + .irq_fs_reg = ASYS_IRQ14_CON, 2613 + .irq_fs_shift = 24, 2614 + .irq_fs_maskbit = 0x1ffff, 2615 + .irq_en_reg = ASYS_IRQ14_CON, 2616 + .irq_en_shift = 31, 2617 + .irq_clr_reg = ASYS_IRQ_CLR, 2618 + .irq_clr_shift = 13, 2619 + .irq_status_shift = 13, 2620 + }, 2621 + [MT8188_AFE_IRQ_27] = { 2622 + .id = MT8188_AFE_IRQ_27, 2623 + .irq_cnt_reg = ASYS_IRQ15_CON, 2624 + .irq_cnt_shift = 0, 2625 + .irq_cnt_maskbit = 0xffffff, 2626 + .irq_fs_reg = ASYS_IRQ15_CON, 2627 + .irq_fs_shift = 24, 2628 + .irq_fs_maskbit = 0x1ffff, 2629 + .irq_en_reg = ASYS_IRQ15_CON, 2630 + .irq_en_shift = 31, 2631 + .irq_clr_reg = ASYS_IRQ_CLR, 2632 + .irq_clr_shift = 14, 2633 + .irq_status_shift = 14, 2634 + }, 2635 + [MT8188_AFE_IRQ_28] = { 2636 + .id = MT8188_AFE_IRQ_28, 2637 + .irq_cnt_reg = ASYS_IRQ16_CON, 2638 + .irq_cnt_shift = 0, 2639 + .irq_cnt_maskbit = 0xffffff, 2640 + .irq_fs_reg = ASYS_IRQ16_CON, 2641 + .irq_fs_shift = 24, 2642 + .irq_fs_maskbit = 0x1ffff, 2643 + .irq_en_reg = ASYS_IRQ16_CON, 2644 + .irq_en_shift = 31, 2645 + .irq_clr_reg = ASYS_IRQ_CLR, 2646 + .irq_clr_shift = 15, 2647 + .irq_status_shift = 15, 2648 + }, 2649 + }; 2650 + 2651 + static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = { 2652 + [MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13, 2653 + [MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14, 2654 + [MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15, 2655 + [MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1, 2656 + [MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16, 2657 + [MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17, 2658 + [MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18, 2659 + [MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3, 2660 + [MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19, 2661 + [MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20, 2662 + [MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21, 2663 + [MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22, 2664 + [MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9, 2665 + [MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23, 2666 + [MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24, 2667 + [MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25, 2668 + }; 2669 + 2670 + static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg) 2671 + { 2672 + /* these auto-gen reg has read-only bit, so put it as volatile */ 2673 + /* volatile reg cannot be cached, so cannot be set when power off */ 2674 + switch (reg) { 2675 + case AUDIO_TOP_CON0: 2676 + case AUDIO_TOP_CON1: 2677 + case AUDIO_TOP_CON3: 2678 + case AUDIO_TOP_CON4: 2679 + case AUDIO_TOP_CON5: 2680 + case AUDIO_TOP_CON6: 2681 + case ASYS_IRQ_CLR: 2682 + case ASYS_IRQ_STATUS: 2683 + case ASYS_IRQ_MON1: 2684 + case ASYS_IRQ_MON2: 2685 + case AFE_IRQ_MCU_CLR: 2686 + case AFE_IRQ_STATUS: 2687 + case AFE_IRQ3_CON_MON: 2688 + case AFE_IRQ_MCU_MON2: 2689 + case ADSP_IRQ_STATUS: 2690 + case AUDIO_TOP_STA0: 2691 + case AUDIO_TOP_STA1: 2692 + case AFE_GAIN1_CUR: 2693 + case AFE_GAIN2_CUR: 2694 + case AFE_IEC_BURST_INFO: 2695 + case AFE_IEC_CHL_STAT0: 2696 + case AFE_IEC_CHL_STAT1: 2697 + case AFE_IEC_CHR_STAT0: 2698 + case AFE_IEC_CHR_STAT1: 2699 + case AFE_SPDIFIN_CHSTS1: 2700 + case AFE_SPDIFIN_CHSTS2: 2701 + case AFE_SPDIFIN_CHSTS3: 2702 + case AFE_SPDIFIN_CHSTS4: 2703 + case AFE_SPDIFIN_CHSTS5: 2704 + case AFE_SPDIFIN_CHSTS6: 2705 + case AFE_SPDIFIN_DEBUG1: 2706 + case AFE_SPDIFIN_DEBUG2: 2707 + case AFE_SPDIFIN_DEBUG3: 2708 + case AFE_SPDIFIN_DEBUG4: 2709 + case AFE_SPDIFIN_EC: 2710 + case AFE_SPDIFIN_CKLOCK_CFG: 2711 + case AFE_SPDIFIN_BR_DBG1: 2712 + case AFE_SPDIFIN_CKFBDIV: 2713 + case AFE_SPDIFIN_INT_EXT: 2714 + case AFE_SPDIFIN_INT_EXT2: 2715 + case SPDIFIN_FREQ_STATUS: 2716 + case SPDIFIN_USERCODE1: 2717 + case SPDIFIN_USERCODE2: 2718 + case SPDIFIN_USERCODE3: 2719 + case SPDIFIN_USERCODE4: 2720 + case SPDIFIN_USERCODE5: 2721 + case SPDIFIN_USERCODE6: 2722 + case SPDIFIN_USERCODE7: 2723 + case SPDIFIN_USERCODE8: 2724 + case SPDIFIN_USERCODE9: 2725 + case SPDIFIN_USERCODE10: 2726 + case SPDIFIN_USERCODE11: 2727 + case SPDIFIN_USERCODE12: 2728 + case AFE_LINEIN_APLL_TUNER_MON: 2729 + case AFE_EARC_APLL_TUNER_MON: 2730 + case AFE_CM0_MON: 2731 + case AFE_CM1_MON: 2732 + case AFE_CM2_MON: 2733 + case AFE_MPHONE_MULTI_DET_MON0: 2734 + case AFE_MPHONE_MULTI_DET_MON1: 2735 + case AFE_MPHONE_MULTI_DET_MON2: 2736 + case AFE_MPHONE_MULTI2_DET_MON0: 2737 + case AFE_MPHONE_MULTI2_DET_MON1: 2738 + case AFE_MPHONE_MULTI2_DET_MON2: 2739 + case AFE_ADDA_MTKAIF_MON0: 2740 + case AFE_ADDA_MTKAIF_MON1: 2741 + case AFE_AUD_PAD_TOP: 2742 + case AFE_ADDA6_MTKAIF_MON0: 2743 + case AFE_ADDA6_MTKAIF_MON1: 2744 + case AFE_ADDA6_SRC_DEBUG_MON0: 2745 + case AFE_ADDA6_UL_SRC_MON0: 2746 + case AFE_ADDA6_UL_SRC_MON1: 2747 + case AFE_ASRC11_NEW_CON8: 2748 + case AFE_ASRC11_NEW_CON9: 2749 + case AFE_ASRC12_NEW_CON8: 2750 + case AFE_ASRC12_NEW_CON9: 2751 + case AFE_LRCK_CNT: 2752 + case AFE_DAC_MON0: 2753 + case AFE_DL2_CUR: 2754 + case AFE_DL3_CUR: 2755 + case AFE_DL6_CUR: 2756 + case AFE_DL7_CUR: 2757 + case AFE_DL8_CUR: 2758 + case AFE_DL10_CUR: 2759 + case AFE_DL11_CUR: 2760 + case AFE_UL1_CUR: 2761 + case AFE_UL2_CUR: 2762 + case AFE_UL3_CUR: 2763 + case AFE_UL4_CUR: 2764 + case AFE_UL5_CUR: 2765 + case AFE_UL6_CUR: 2766 + case AFE_UL8_CUR: 2767 + case AFE_UL9_CUR: 2768 + case AFE_UL10_CUR: 2769 + case AFE_DL8_CHK_SUM1: 2770 + case AFE_DL8_CHK_SUM2: 2771 + case AFE_DL8_CHK_SUM3: 2772 + case AFE_DL8_CHK_SUM4: 2773 + case AFE_DL8_CHK_SUM5: 2774 + case AFE_DL8_CHK_SUM6: 2775 + case AFE_DL10_CHK_SUM1: 2776 + case AFE_DL10_CHK_SUM2: 2777 + case AFE_DL10_CHK_SUM3: 2778 + case AFE_DL10_CHK_SUM4: 2779 + case AFE_DL10_CHK_SUM5: 2780 + case AFE_DL10_CHK_SUM6: 2781 + case AFE_DL11_CHK_SUM1: 2782 + case AFE_DL11_CHK_SUM2: 2783 + case AFE_DL11_CHK_SUM3: 2784 + case AFE_DL11_CHK_SUM4: 2785 + case AFE_DL11_CHK_SUM5: 2786 + case AFE_DL11_CHK_SUM6: 2787 + case AFE_UL1_CHK_SUM1: 2788 + case AFE_UL1_CHK_SUM2: 2789 + case AFE_UL2_CHK_SUM1: 2790 + case AFE_UL2_CHK_SUM2: 2791 + case AFE_UL3_CHK_SUM1: 2792 + case AFE_UL3_CHK_SUM2: 2793 + case AFE_UL4_CHK_SUM1: 2794 + case AFE_UL4_CHK_SUM2: 2795 + case AFE_UL5_CHK_SUM1: 2796 + case AFE_UL5_CHK_SUM2: 2797 + case AFE_UL6_CHK_SUM1: 2798 + case AFE_UL6_CHK_SUM2: 2799 + case AFE_UL8_CHK_SUM1: 2800 + case AFE_UL8_CHK_SUM2: 2801 + case AFE_DL2_CHK_SUM1: 2802 + case AFE_DL2_CHK_SUM2: 2803 + case AFE_DL3_CHK_SUM1: 2804 + case AFE_DL3_CHK_SUM2: 2805 + case AFE_DL6_CHK_SUM1: 2806 + case AFE_DL6_CHK_SUM2: 2807 + case AFE_DL7_CHK_SUM1: 2808 + case AFE_DL7_CHK_SUM2: 2809 + case AFE_UL9_CHK_SUM1: 2810 + case AFE_UL9_CHK_SUM2: 2811 + case AFE_BUS_MON1: 2812 + case UL1_MOD2AGT_CNT_LAT: 2813 + case UL2_MOD2AGT_CNT_LAT: 2814 + case UL3_MOD2AGT_CNT_LAT: 2815 + case UL4_MOD2AGT_CNT_LAT: 2816 + case UL5_MOD2AGT_CNT_LAT: 2817 + case UL6_MOD2AGT_CNT_LAT: 2818 + case UL8_MOD2AGT_CNT_LAT: 2819 + case UL9_MOD2AGT_CNT_LAT: 2820 + case UL10_MOD2AGT_CNT_LAT: 2821 + case AFE_MEMIF_BUF_FULL_MON: 2822 + case AFE_MEMIF_BUF_MON1: 2823 + case AFE_MEMIF_BUF_MON3: 2824 + case AFE_MEMIF_BUF_MON4: 2825 + case AFE_MEMIF_BUF_MON5: 2826 + case AFE_MEMIF_BUF_MON6: 2827 + case AFE_MEMIF_BUF_MON7: 2828 + case AFE_MEMIF_BUF_MON8: 2829 + case AFE_MEMIF_BUF_MON9: 2830 + case AFE_MEMIF_BUF_MON10: 2831 + case DL2_AGENT2MODULE_CNT: 2832 + case DL3_AGENT2MODULE_CNT: 2833 + case DL6_AGENT2MODULE_CNT: 2834 + case DL7_AGENT2MODULE_CNT: 2835 + case DL8_AGENT2MODULE_CNT: 2836 + case DL10_AGENT2MODULE_CNT: 2837 + case DL11_AGENT2MODULE_CNT: 2838 + case UL1_MODULE2AGENT_CNT: 2839 + case UL2_MODULE2AGENT_CNT: 2840 + case UL3_MODULE2AGENT_CNT: 2841 + case UL4_MODULE2AGENT_CNT: 2842 + case UL5_MODULE2AGENT_CNT: 2843 + case UL6_MODULE2AGENT_CNT: 2844 + case UL8_MODULE2AGENT_CNT: 2845 + case UL9_MODULE2AGENT_CNT: 2846 + case UL10_MODULE2AGENT_CNT: 2847 + case AFE_DMIC0_SRC_DEBUG_MON0: 2848 + case AFE_DMIC0_UL_SRC_MON0: 2849 + case AFE_DMIC0_UL_SRC_MON1: 2850 + case AFE_DMIC1_SRC_DEBUG_MON0: 2851 + case AFE_DMIC1_UL_SRC_MON0: 2852 + case AFE_DMIC1_UL_SRC_MON1: 2853 + case AFE_DMIC2_SRC_DEBUG_MON0: 2854 + case AFE_DMIC2_UL_SRC_MON0: 2855 + case AFE_DMIC2_UL_SRC_MON1: 2856 + case AFE_DMIC3_SRC_DEBUG_MON0: 2857 + case AFE_DMIC3_UL_SRC_MON0: 2858 + case AFE_DMIC3_UL_SRC_MON1: 2859 + case DMIC_GAIN1_CUR: 2860 + case DMIC_GAIN2_CUR: 2861 + case DMIC_GAIN3_CUR: 2862 + case DMIC_GAIN4_CUR: 2863 + case ETDM_IN1_MONITOR: 2864 + case ETDM_IN2_MONITOR: 2865 + case ETDM_OUT1_MONITOR: 2866 + case ETDM_OUT2_MONITOR: 2867 + case ETDM_OUT3_MONITOR: 2868 + case AFE_ADDA_SRC_DEBUG_MON0: 2869 + case AFE_ADDA_SRC_DEBUG_MON1: 2870 + case AFE_ADDA_DL_SDM_FIFO_MON: 2871 + case AFE_ADDA_DL_SRC_LCH_MON: 2872 + case AFE_ADDA_DL_SRC_RCH_MON: 2873 + case AFE_ADDA_DL_SDM_OUT_MON: 2874 + case AFE_GASRC0_NEW_CON8: 2875 + case AFE_GASRC0_NEW_CON9: 2876 + case AFE_GASRC0_NEW_CON12: 2877 + case AFE_GASRC1_NEW_CON8: 2878 + case AFE_GASRC1_NEW_CON9: 2879 + case AFE_GASRC1_NEW_CON12: 2880 + case AFE_GASRC2_NEW_CON8: 2881 + case AFE_GASRC2_NEW_CON9: 2882 + case AFE_GASRC2_NEW_CON12: 2883 + case AFE_GASRC3_NEW_CON8: 2884 + case AFE_GASRC3_NEW_CON9: 2885 + case AFE_GASRC3_NEW_CON12: 2886 + case AFE_GASRC4_NEW_CON8: 2887 + case AFE_GASRC4_NEW_CON9: 2888 + case AFE_GASRC4_NEW_CON12: 2889 + case AFE_GASRC5_NEW_CON8: 2890 + case AFE_GASRC5_NEW_CON9: 2891 + case AFE_GASRC5_NEW_CON12: 2892 + case AFE_GASRC6_NEW_CON8: 2893 + case AFE_GASRC6_NEW_CON9: 2894 + case AFE_GASRC6_NEW_CON12: 2895 + case AFE_GASRC7_NEW_CON8: 2896 + case AFE_GASRC7_NEW_CON9: 2897 + case AFE_GASRC7_NEW_CON12: 2898 + case AFE_GASRC8_NEW_CON8: 2899 + case AFE_GASRC8_NEW_CON9: 2900 + case AFE_GASRC8_NEW_CON12: 2901 + case AFE_GASRC9_NEW_CON8: 2902 + case AFE_GASRC9_NEW_CON9: 2903 + case AFE_GASRC9_NEW_CON12: 2904 + case AFE_GASRC10_NEW_CON8: 2905 + case AFE_GASRC10_NEW_CON9: 2906 + case AFE_GASRC10_NEW_CON12: 2907 + case AFE_GASRC11_NEW_CON8: 2908 + case AFE_GASRC11_NEW_CON9: 2909 + case AFE_GASRC11_NEW_CON12: 2910 + return true; 2911 + default: 2912 + return false; 2913 + }; 2914 + } 2915 + 2916 + static const struct regmap_config mt8188_afe_regmap_config = { 2917 + .reg_bits = 32, 2918 + .reg_stride = 4, 2919 + .val_bits = 32, 2920 + .volatile_reg = mt8188_is_volatile_reg, 2921 + .max_register = AFE_MAX_REGISTER, 2922 + .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), 2923 + .cache_type = REGCACHE_FLAT, 2924 + }; 2925 + 2926 + #define AFE_IRQ_CLR_BITS (0x387) 2927 + #define ASYS_IRQ_CLR_BITS (0xffff) 2928 + 2929 + static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id) 2930 + { 2931 + struct mtk_base_afe *afe = dev_id; 2932 + unsigned int val = 0; 2933 + unsigned int asys_irq_clr_bits = 0; 2934 + unsigned int afe_irq_clr_bits = 0; 2935 + unsigned int irq_status_bits = 0; 2936 + unsigned int irq_clr_bits = 0; 2937 + unsigned int mcu_irq_mask = 0; 2938 + int i = 0; 2939 + int ret = 0; 2940 + 2941 + ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val); 2942 + if (ret) { 2943 + dev_err(afe->dev, "%s irq status err\n", __func__); 2944 + afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2945 + asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2946 + goto err_irq; 2947 + } 2948 + 2949 + ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask); 2950 + if (ret) { 2951 + dev_err(afe->dev, "%s read irq mask err\n", __func__); 2952 + afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2953 + asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2954 + goto err_irq; 2955 + } 2956 + 2957 + /* only clr cpu irq */ 2958 + val &= mcu_irq_mask; 2959 + 2960 + for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) { 2961 + struct mtk_base_afe_memif *memif = &afe->memif[i]; 2962 + struct mtk_base_irq_data const *irq_data; 2963 + 2964 + if (memif->irq_usage < 0) 2965 + continue; 2966 + 2967 + irq_data = afe->irqs[memif->irq_usage].irq_data; 2968 + 2969 + irq_status_bits = BIT(irq_data->irq_status_shift); 2970 + irq_clr_bits = BIT(irq_data->irq_clr_shift); 2971 + 2972 + if (!(val & irq_status_bits)) 2973 + continue; 2974 + 2975 + if (irq_data->irq_clr_reg == ASYS_IRQ_CLR) 2976 + asys_irq_clr_bits |= irq_clr_bits; 2977 + else 2978 + afe_irq_clr_bits |= irq_clr_bits; 2979 + 2980 + snd_pcm_period_elapsed(memif->substream); 2981 + } 2982 + 2983 + err_irq: 2984 + /* clear irq */ 2985 + if (asys_irq_clr_bits) 2986 + regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits); 2987 + if (afe_irq_clr_bits) 2988 + regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits); 2989 + 2990 + return IRQ_HANDLED; 2991 + } 2992 + 2993 + static int mt8188_afe_runtime_suspend(struct device *dev) 2994 + { 2995 + struct mtk_base_afe *afe = dev_get_drvdata(dev); 2996 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2997 + 2998 + if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2999 + goto skip_regmap; 3000 + 3001 + mt8188_afe_disable_main_clock(afe); 3002 + 3003 + regcache_cache_only(afe->regmap, true); 3004 + regcache_mark_dirty(afe->regmap); 3005 + 3006 + skip_regmap: 3007 + mt8188_afe_disable_reg_rw_clk(afe); 3008 + 3009 + return 0; 3010 + } 3011 + 3012 + static int mt8188_afe_runtime_resume(struct device *dev) 3013 + { 3014 + struct mtk_base_afe *afe = dev_get_drvdata(dev); 3015 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 3016 + struct arm_smccc_res res; 3017 + 3018 + arm_smccc_smc(MTK_SIP_AUDIO_CONTROL, 3019 + MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS, 3020 + 0, 0, 0, 0, 0, 0, &res); 3021 + 3022 + mt8188_afe_enable_reg_rw_clk(afe); 3023 + 3024 + if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 3025 + goto skip_regmap; 3026 + 3027 + regcache_cache_only(afe->regmap, false); 3028 + regcache_sync(afe->regmap); 3029 + 3030 + mt8188_afe_enable_main_clock(afe); 3031 + skip_regmap: 3032 + return 0; 3033 + } 3034 + 3035 + static int mt8188_afe_component_probe(struct snd_soc_component *component) 3036 + { 3037 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 3038 + int ret; 3039 + 3040 + snd_soc_component_init_regmap(component, afe->regmap); 3041 + 3042 + ret = mtk_afe_add_sub_dai_control(component); 3043 + 3044 + return ret; 3045 + } 3046 + 3047 + static const struct snd_soc_component_driver mt8188_afe_component = { 3048 + .name = AFE_PCM_NAME, 3049 + .pointer = mtk_afe_pcm_pointer, 3050 + .pcm_construct = mtk_afe_pcm_new, 3051 + .probe = mt8188_afe_component_probe, 3052 + }; 3053 + 3054 + static int init_memif_priv_data(struct mtk_base_afe *afe) 3055 + { 3056 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 3057 + struct mtk_dai_memif_priv *memif_priv; 3058 + int i; 3059 + 3060 + for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) { 3061 + memif_priv = devm_kzalloc(afe->dev, 3062 + sizeof(struct mtk_dai_memif_priv), 3063 + GFP_KERNEL); 3064 + if (!memif_priv) 3065 + return -ENOMEM; 3066 + 3067 + afe_priv->dai_priv[i] = memif_priv; 3068 + } 3069 + 3070 + return 0; 3071 + } 3072 + 3073 + static int mt8188_dai_memif_register(struct mtk_base_afe *afe) 3074 + { 3075 + struct mtk_base_afe_dai *dai; 3076 + 3077 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 3078 + if (!dai) 3079 + return -ENOMEM; 3080 + 3081 + list_add(&dai->list, &afe->sub_dais); 3082 + 3083 + dai->dai_drivers = mt8188_memif_dai_driver; 3084 + dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver); 3085 + 3086 + dai->dapm_widgets = mt8188_memif_widgets; 3087 + dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets); 3088 + dai->dapm_routes = mt8188_memif_routes; 3089 + dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes); 3090 + dai->controls = mt8188_memif_controls; 3091 + dai->num_controls = ARRAY_SIZE(mt8188_memif_controls); 3092 + 3093 + return init_memif_priv_data(afe); 3094 + } 3095 + 3096 + typedef int (*dai_register_cb)(struct mtk_base_afe *); 3097 + static const dai_register_cb dai_register_cbs[] = { 3098 + mt8188_dai_adda_register, 3099 + mt8188_dai_etdm_register, 3100 + mt8188_dai_pcm_register, 3101 + mt8188_dai_memif_register, 3102 + }; 3103 + 3104 + static const struct reg_sequence mt8188_afe_reg_defaults[] = { 3105 + { AFE_IRQ_MASK, 0x387ffff }, 3106 + { AFE_IRQ3_CON, BIT(30) }, 3107 + { AFE_IRQ9_CON, BIT(30) }, 3108 + { ETDM_IN1_CON4, 0x12000100 }, 3109 + { ETDM_IN2_CON4, 0x12000100 }, 3110 + }; 3111 + 3112 + static const struct reg_sequence mt8188_cg_patch[] = { 3113 + { AUDIO_TOP_CON0, 0xfffffffb }, 3114 + { AUDIO_TOP_CON1, 0xfffffff8 }, 3115 + }; 3116 + 3117 + static int mt8188_afe_init_registers(struct mtk_base_afe *afe) 3118 + { 3119 + return regmap_multi_reg_write(afe->regmap, 3120 + mt8188_afe_reg_defaults, 3121 + ARRAY_SIZE(mt8188_afe_reg_defaults)); 3122 + } 3123 + 3124 + static int mt8188_afe_parse_of(struct mtk_base_afe *afe, 3125 + struct device_node *np) 3126 + { 3127 + #if IS_ENABLED(CONFIG_SND_SOC_MT6359) 3128 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 3129 + 3130 + afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node, 3131 + "mediatek,topckgen"); 3132 + if (IS_ERR(afe_priv->topckgen)) 3133 + return dev_err_probe(afe->dev, PTR_ERR(afe_priv->topckgen), 3134 + "%s() Cannot find topckgen controller\n", 3135 + __func__); 3136 + #endif 3137 + return 0; 3138 + } 3139 + 3140 + static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev) 3141 + { 3142 + struct mtk_base_afe *afe; 3143 + struct mt8188_afe_private *afe_priv; 3144 + struct device *dev; 3145 + int i, irq_id, ret; 3146 + struct snd_soc_component *component; 3147 + struct reset_control *rstc; 3148 + 3149 + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 3150 + if (ret) 3151 + return ret; 3152 + 3153 + afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 3154 + if (!afe) 3155 + return -ENOMEM; 3156 + 3157 + afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 3158 + GFP_KERNEL); 3159 + if (!afe->platform_priv) 3160 + return -ENOMEM; 3161 + 3162 + afe_priv = afe->platform_priv; 3163 + afe->dev = &pdev->dev; 3164 + dev = afe->dev; 3165 + 3166 + afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 3167 + if (IS_ERR(afe->base_addr)) 3168 + return dev_err_probe(dev, PTR_ERR(afe->base_addr), 3169 + "AFE base_addr not found\n"); 3170 + 3171 + /* reset controller to reset audio regs before regmap cache */ 3172 + rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 3173 + if (IS_ERR(rstc)) 3174 + return dev_err_probe(dev, PTR_ERR(rstc), 3175 + "could not get audiosys reset\n"); 3176 + 3177 + ret = reset_control_reset(rstc); 3178 + if (ret) { 3179 + dev_err(dev, "failed to trigger audio reset:%d\n", ret); 3180 + return ret; 3181 + } 3182 + 3183 + /* initial audio related clock */ 3184 + ret = mt8188_afe_init_clock(afe); 3185 + if (ret) 3186 + return dev_err_probe(dev, ret, "init clock error"); 3187 + 3188 + ret = devm_add_action_or_reset(dev, mt8188_afe_deinit_clock, (void *)afe); 3189 + if (ret) 3190 + return ret; 3191 + 3192 + spin_lock_init(&afe_priv->afe_ctrl_lock); 3193 + 3194 + mutex_init(&afe->irq_alloc_lock); 3195 + 3196 + /* irq initialize */ 3197 + afe->irqs_size = MT8188_AFE_IRQ_NUM; 3198 + afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 3199 + GFP_KERNEL); 3200 + if (!afe->irqs) 3201 + return -ENOMEM; 3202 + 3203 + for (i = 0; i < afe->irqs_size; i++) 3204 + afe->irqs[i].irq_data = &irq_data[i]; 3205 + 3206 + /* init memif */ 3207 + afe->memif_size = MT8188_AFE_MEMIF_NUM; 3208 + afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 3209 + GFP_KERNEL); 3210 + if (!afe->memif) 3211 + return -ENOMEM; 3212 + 3213 + for (i = 0; i < afe->memif_size; i++) { 3214 + afe->memif[i].data = &memif_data[i]; 3215 + afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i]; 3216 + afe->memif[i].const_irq = 1; 3217 + afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true; 3218 + } 3219 + 3220 + /* request irq */ 3221 + irq_id = platform_get_irq(pdev, 0); 3222 + if (irq_id < 0) 3223 + return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO, 3224 + "no irq found"); 3225 + 3226 + ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler, 3227 + IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 3228 + if (ret) 3229 + return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n"); 3230 + 3231 + /* init sub_dais */ 3232 + INIT_LIST_HEAD(&afe->sub_dais); 3233 + 3234 + for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 3235 + ret = dai_register_cbs[i](afe); 3236 + if (ret) 3237 + return dev_err_probe(dev, ret, "dai register i %d fail\n", i); 3238 + } 3239 + 3240 + /* init dai_driver and component_driver */ 3241 + ret = mtk_afe_combine_sub_dai(afe); 3242 + if (ret) 3243 + return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); 3244 + 3245 + afe->mtk_afe_hardware = &mt8188_afe_hardware; 3246 + afe->memif_fs = mt8188_memif_fs; 3247 + afe->irq_fs = mt8188_irq_fs; 3248 + 3249 + afe->runtime_resume = mt8188_afe_runtime_resume; 3250 + afe->runtime_suspend = mt8188_afe_runtime_suspend; 3251 + 3252 + platform_set_drvdata(pdev, afe); 3253 + 3254 + ret = mt8188_afe_parse_of(afe, pdev->dev.of_node); 3255 + if (ret) 3256 + return ret; 3257 + 3258 + ret = devm_pm_runtime_enable(dev); 3259 + if (ret) 3260 + return ret; 3261 + 3262 + /* enable clock for regcache get default value from hw */ 3263 + afe_priv->pm_runtime_bypass_reg_ctl = true; 3264 + ret = pm_runtime_resume_and_get(dev); 3265 + if (ret) 3266 + return dev_err_probe(dev, ret, "failed to resume device\n"); 3267 + 3268 + afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 3269 + &mt8188_afe_regmap_config); 3270 + if (IS_ERR(afe->regmap)) { 3271 + ret = PTR_ERR(afe->regmap); 3272 + goto err_pm_put; 3273 + } 3274 + 3275 + ret = regmap_register_patch(afe->regmap, mt8188_cg_patch, 3276 + ARRAY_SIZE(mt8188_cg_patch)); 3277 + if (ret < 0) { 3278 + dev_info(dev, "Failed to apply cg patch\n"); 3279 + goto err_pm_put; 3280 + } 3281 + 3282 + /* register component */ 3283 + ret = devm_snd_soc_register_component(dev, &mt8188_afe_component, 3284 + NULL, 0); 3285 + if (ret) { 3286 + dev_warn(dev, "err_platform\n"); 3287 + goto err_pm_put; 3288 + } 3289 + 3290 + component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL); 3291 + if (!component) { 3292 + ret = -ENOMEM; 3293 + goto err_pm_put; 3294 + } 3295 + 3296 + ret = snd_soc_component_initialize(component, 3297 + &mt8188_afe_pcm_dai_component, 3298 + &pdev->dev); 3299 + if (ret) 3300 + goto err_pm_put; 3301 + #ifdef CONFIG_DEBUG_FS 3302 + component->debugfs_prefix = "pcm"; 3303 + #endif 3304 + ret = snd_soc_add_component(component, 3305 + afe->dai_drivers, 3306 + afe->num_dai_drivers); 3307 + if (ret) { 3308 + dev_warn(dev, "err_add_component\n"); 3309 + goto err_pm_put; 3310 + } 3311 + 3312 + mt8188_afe_init_registers(afe); 3313 + 3314 + pm_runtime_put_sync(&pdev->dev); 3315 + afe_priv->pm_runtime_bypass_reg_ctl = false; 3316 + 3317 + regcache_cache_only(afe->regmap, true); 3318 + regcache_mark_dirty(afe->regmap); 3319 + 3320 + return 0; 3321 + err_pm_put: 3322 + pm_runtime_put_sync(dev); 3323 + 3324 + return ret; 3325 + } 3326 + 3327 + static int mt8188_afe_pcm_dev_remove(struct platform_device *pdev) 3328 + { 3329 + snd_soc_unregister_component(&pdev->dev); 3330 + 3331 + return 0; 3332 + } 3333 + 3334 + static const struct of_device_id mt8188_afe_pcm_dt_match[] = { 3335 + { .compatible = "mediatek,mt8188-afe", }, 3336 + {}, 3337 + }; 3338 + MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match); 3339 + 3340 + static const struct dev_pm_ops mt8188_afe_pm_ops = { 3341 + SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend, 3342 + mt8188_afe_runtime_resume, NULL) 3343 + }; 3344 + 3345 + static struct platform_driver mt8188_afe_pcm_driver = { 3346 + .driver = { 3347 + .name = "mt8188-audio", 3348 + .of_match_table = mt8188_afe_pcm_dt_match, 3349 + .pm = &mt8188_afe_pm_ops, 3350 + }, 3351 + .probe = mt8188_afe_pcm_dev_probe, 3352 + .remove = mt8188_afe_pcm_dev_remove, 3353 + }; 3354 + 3355 + module_platform_driver(mt8188_afe_pcm_driver); 3356 + 3357 + MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188"); 3358 + MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>"); 3359 + MODULE_LICENSE("GPL");

+205

sound/soc/mediatek/mt8188/mt8188-audsys-clk.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * mt8188-audsys-clk.c -- MediaTek 8188 audsys clock control 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 7 + */ 8 + 9 + #include <linux/clk.h> 10 + #include <linux/clk-provider.h> 11 + #include <linux/clkdev.h> 12 + #include "mt8188-afe-common.h" 13 + #include "mt8188-audsys-clk.h" 14 + #include "mt8188-audsys-clkid.h" 15 + #include "mt8188-reg.h" 16 + 17 + struct afe_gate { 18 + int id; 19 + const char *name; 20 + const char *parent_name; 21 + int reg; 22 + u8 bit; 23 + const struct clk_ops *ops; 24 + unsigned long flags; 25 + u8 cg_flags; 26 + }; 27 + 28 + #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 29 + .id = _id, \ 30 + .name = _name, \ 31 + .parent_name = _parent, \ 32 + .reg = _reg, \ 33 + .bit = _bit, \ 34 + .flags = _flags, \ 35 + .cg_flags = _cgflags, \ 36 + } 37 + 38 + #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 39 + GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \ 40 + CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE) 41 + 42 + #define GATE_AUD0(_id, _name, _parent, _bit) \ 43 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit) 44 + 45 + #define GATE_AUD1(_id, _name, _parent, _bit) \ 46 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit) 47 + 48 + #define GATE_AUD3(_id, _name, _parent, _bit) \ 49 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit) 50 + 51 + #define GATE_AUD4(_id, _name, _parent, _bit) \ 52 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit) 53 + 54 + #define GATE_AUD5(_id, _name, _parent, _bit) \ 55 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit) 56 + 57 + #define GATE_AUD6(_id, _name, _parent, _bit) \ 58 + GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit) 59 + 60 + static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = { 61 + /* AUD0 */ 62 + GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2), 63 + GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4), 64 + GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10), 65 + GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11), 66 + GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18), 67 + GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19), 68 + GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20), 69 + GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21), 70 + GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23), 71 + GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24), 72 + GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25), 73 + GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26), 74 + GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27), 75 + GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28), 76 + GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31), 77 + 78 + /* AUD1 */ 79 + GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2), 80 + GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10), 81 + GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11), 82 + GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12), 83 + GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13), 84 + GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14), 85 + GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16), 86 + GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17), 87 + 88 + /* AUD3 */ 89 + GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5), 90 + GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7), 91 + 92 + /* AUD4 */ 93 + GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0), 94 + GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1), 95 + GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6), 96 + GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7), 97 + GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8), 98 + GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16), 99 + GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17), 100 + GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19), 101 + GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20), 102 + GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21), 103 + GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys", 22), 104 + GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24), 105 + GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys", 30), 106 + GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys", 31), 107 + 108 + /* AUD5 */ 109 + GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0), 110 + GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1), 111 + GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2), 112 + GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3), 113 + GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4), 114 + GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5), 115 + GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7), 116 + GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8), 117 + GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9), 118 + GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18), 119 + GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19), 120 + GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22), 121 + GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23), 122 + GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24), 123 + GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26), 124 + GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27), 125 + 126 + /* AUD6 */ 127 + GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0), 128 + GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1), 129 + GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2), 130 + GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3), 131 + GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4), 132 + GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5), 133 + GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6), 134 + GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7), 135 + GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8), 136 + GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9), 137 + GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10), 138 + GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11), 139 + }; 140 + 141 + int mt8188_audsys_clk_register(struct mtk_base_afe *afe) 142 + { 143 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 144 + struct clk *clk; 145 + struct clk_lookup *cl; 146 + int i; 147 + 148 + afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK, 149 + sizeof(*afe_priv->lookup), 150 + GFP_KERNEL); 151 + 152 + if (!afe_priv->lookup) 153 + return -ENOMEM; 154 + 155 + for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 156 + const struct afe_gate *gate = &aud_clks[i]; 157 + 158 + clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 159 + gate->flags, afe->base_addr + gate->reg, 160 + gate->bit, gate->cg_flags, NULL); 161 + 162 + if (IS_ERR(clk)) { 163 + dev_err(afe->dev, "Failed to register clk %s: %ld\n", 164 + gate->name, PTR_ERR(clk)); 165 + continue; 166 + } 167 + 168 + /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */ 169 + cl = kzalloc(sizeof(*cl), GFP_KERNEL); 170 + if (!cl) 171 + return -ENOMEM; 172 + 173 + cl->clk = clk; 174 + cl->con_id = gate->name; 175 + cl->dev_id = dev_name(afe->dev); 176 + cl->clk_hw = NULL; 177 + clkdev_add(cl); 178 + 179 + afe_priv->lookup[i] = cl; 180 + } 181 + 182 + return 0; 183 + } 184 + 185 + void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe) 186 + { 187 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 188 + struct clk *clk; 189 + struct clk_lookup *cl; 190 + int i; 191 + 192 + if (!afe_priv) 193 + return; 194 + 195 + for (i = 0; i < CLK_AUD_NR_CLK; i++) { 196 + cl = afe_priv->lookup[i]; 197 + if (!cl) 198 + continue; 199 + 200 + clk = cl->clk; 201 + clk_unregister_gate(clk); 202 + 203 + clkdev_drop(cl); 204 + } 205 + }

+15

sound/soc/mediatek/mt8188/mt8188-audsys-clk.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mt8188-audsys-clk.h -- MediaTek 8188 audsys clock definition 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 7 + */ 8 + 9 + #ifndef _MT8188_AUDSYS_CLK_H_ 10 + #define _MT8188_AUDSYS_CLK_H_ 11 + 12 + int mt8188_audsys_clk_register(struct mtk_base_afe *afe); 13 + void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe); 14 + 15 + #endif

+83

sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mt8188-audsys-clkid.h -- MediaTek 8188 audsys clock id definition 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 7 + */ 8 + 9 + #ifndef _MT8188_AUDSYS_CLKID_H_ 10 + #define _MT8188_AUDSYS_CLKID_H_ 11 + 12 + enum{ 13 + CLK_AUD_AFE, 14 + CLK_AUD_LRCK_CNT, 15 + CLK_AUD_SPDIFIN_TUNER_APLL, 16 + CLK_AUD_SPDIFIN_TUNER_DBG, 17 + CLK_AUD_UL_TML, 18 + CLK_AUD_APLL1_TUNER, 19 + CLK_AUD_APLL2_TUNER, 20 + CLK_AUD_TOP0_SPDF, 21 + CLK_AUD_APLL, 22 + CLK_AUD_APLL2, 23 + CLK_AUD_DAC, 24 + CLK_AUD_DAC_PREDIS, 25 + CLK_AUD_TML, 26 + CLK_AUD_ADC, 27 + CLK_AUD_DAC_HIRES, 28 + CLK_AUD_A1SYS_HP, 29 + CLK_AUD_AFE_DMIC1, 30 + CLK_AUD_AFE_DMIC2, 31 + CLK_AUD_AFE_DMIC3, 32 + CLK_AUD_AFE_DMIC4, 33 + CLK_AUD_AFE_26M_DMIC_TM, 34 + CLK_AUD_UL_TML_HIRES, 35 + CLK_AUD_ADC_HIRES, 36 + CLK_AUD_LINEIN_TUNER, 37 + CLK_AUD_EARC_TUNER, 38 + CLK_AUD_I2SIN, 39 + CLK_AUD_TDM_IN, 40 + CLK_AUD_I2S_OUT, 41 + CLK_AUD_TDM_OUT, 42 + CLK_AUD_HDMI_OUT, 43 + CLK_AUD_ASRC11, 44 + CLK_AUD_ASRC12, 45 + CLK_AUD_MULTI_IN, 46 + CLK_AUD_INTDIR, 47 + CLK_AUD_A1SYS, 48 + CLK_AUD_A2SYS, 49 + CLK_AUD_PCMIF, 50 + CLK_AUD_A3SYS, 51 + CLK_AUD_A4SYS, 52 + CLK_AUD_MEMIF_UL1, 53 + CLK_AUD_MEMIF_UL2, 54 + CLK_AUD_MEMIF_UL3, 55 + CLK_AUD_MEMIF_UL4, 56 + CLK_AUD_MEMIF_UL5, 57 + CLK_AUD_MEMIF_UL6, 58 + CLK_AUD_MEMIF_UL8, 59 + CLK_AUD_MEMIF_UL9, 60 + CLK_AUD_MEMIF_UL10, 61 + CLK_AUD_MEMIF_DL2, 62 + CLK_AUD_MEMIF_DL3, 63 + CLK_AUD_MEMIF_DL6, 64 + CLK_AUD_MEMIF_DL7, 65 + CLK_AUD_MEMIF_DL8, 66 + CLK_AUD_MEMIF_DL10, 67 + CLK_AUD_MEMIF_DL11, 68 + CLK_AUD_GASRC0, 69 + CLK_AUD_GASRC1, 70 + CLK_AUD_GASRC2, 71 + CLK_AUD_GASRC3, 72 + CLK_AUD_GASRC4, 73 + CLK_AUD_GASRC5, 74 + CLK_AUD_GASRC6, 75 + CLK_AUD_GASRC7, 76 + CLK_AUD_GASRC8, 77 + CLK_AUD_GASRC9, 78 + CLK_AUD_GASRC10, 79 + CLK_AUD_GASRC11, 80 + CLK_AUD_NR_CLK, 81 + }; 82 + 83 + #endif

+632

sound/soc/mediatek/mt8188/mt8188-dai-adda.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * MediaTek ALSA SoC Audio DAI ADDA Control 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #include <linux/bitfield.h> 12 + #include <linux/delay.h> 13 + #include <linux/regmap.h> 14 + #include "mt8188-afe-clk.h" 15 + #include "mt8188-afe-common.h" 16 + #include "mt8188-reg.h" 17 + 18 + #define ADDA_HIRES_THRES 48000 19 + 20 + enum { 21 + SUPPLY_SEQ_CLOCK_SEL, 22 + SUPPLY_SEQ_ADDA_DL_ON, 23 + SUPPLY_SEQ_ADDA_MTKAIF_CFG, 24 + SUPPLY_SEQ_ADDA_UL_ON, 25 + SUPPLY_SEQ_ADDA_AFE_ON, 26 + }; 27 + 28 + enum { 29 + MTK_AFE_ADDA_DL_RATE_8K = 0, 30 + MTK_AFE_ADDA_DL_RATE_11K = 1, 31 + MTK_AFE_ADDA_DL_RATE_12K = 2, 32 + MTK_AFE_ADDA_DL_RATE_16K = 3, 33 + MTK_AFE_ADDA_DL_RATE_22K = 4, 34 + MTK_AFE_ADDA_DL_RATE_24K = 5, 35 + MTK_AFE_ADDA_DL_RATE_32K = 6, 36 + MTK_AFE_ADDA_DL_RATE_44K = 7, 37 + MTK_AFE_ADDA_DL_RATE_48K = 8, 38 + MTK_AFE_ADDA_DL_RATE_96K = 9, 39 + MTK_AFE_ADDA_DL_RATE_192K = 10, 40 + }; 41 + 42 + enum { 43 + MTK_AFE_ADDA_UL_RATE_8K = 0, 44 + MTK_AFE_ADDA_UL_RATE_16K = 1, 45 + MTK_AFE_ADDA_UL_RATE_32K = 2, 46 + MTK_AFE_ADDA_UL_RATE_48K = 3, 47 + MTK_AFE_ADDA_UL_RATE_96K = 4, 48 + MTK_AFE_ADDA_UL_RATE_192K = 5, 49 + }; 50 + 51 + enum { 52 + DELAY_DATA_MISO1 = 0, 53 + DELAY_DATA_MISO0 = 1, 54 + }; 55 + 56 + struct mtk_dai_adda_priv { 57 + unsigned int dl_rate; 58 + unsigned int ul_rate; 59 + }; 60 + 61 + static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe, 62 + unsigned int rate) 63 + { 64 + switch (rate) { 65 + case 8000: 66 + return MTK_AFE_ADDA_DL_RATE_8K; 67 + case 11025: 68 + return MTK_AFE_ADDA_DL_RATE_11K; 69 + case 12000: 70 + return MTK_AFE_ADDA_DL_RATE_12K; 71 + case 16000: 72 + return MTK_AFE_ADDA_DL_RATE_16K; 73 + case 22050: 74 + return MTK_AFE_ADDA_DL_RATE_22K; 75 + case 24000: 76 + return MTK_AFE_ADDA_DL_RATE_24K; 77 + case 32000: 78 + return MTK_AFE_ADDA_DL_RATE_32K; 79 + case 44100: 80 + return MTK_AFE_ADDA_DL_RATE_44K; 81 + case 48000: 82 + return MTK_AFE_ADDA_DL_RATE_48K; 83 + case 96000: 84 + return MTK_AFE_ADDA_DL_RATE_96K; 85 + case 192000: 86 + return MTK_AFE_ADDA_DL_RATE_192K; 87 + default: 88 + dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 89 + __func__, rate); 90 + return MTK_AFE_ADDA_DL_RATE_48K; 91 + } 92 + } 93 + 94 + static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe, 95 + unsigned int rate) 96 + { 97 + switch (rate) { 98 + case 8000: 99 + return MTK_AFE_ADDA_UL_RATE_8K; 100 + case 16000: 101 + return MTK_AFE_ADDA_UL_RATE_16K; 102 + case 32000: 103 + return MTK_AFE_ADDA_UL_RATE_32K; 104 + case 48000: 105 + return MTK_AFE_ADDA_UL_RATE_48K; 106 + case 96000: 107 + return MTK_AFE_ADDA_UL_RATE_96K; 108 + case 192000: 109 + return MTK_AFE_ADDA_UL_RATE_192K; 110 + default: 111 + dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 112 + __func__, rate); 113 + return MTK_AFE_ADDA_UL_RATE_48K; 114 + } 115 + } 116 + 117 + static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe) 118 + { 119 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 120 + struct mtkaif_param *param = &afe_priv->mtkaif_params; 121 + int delay_data; 122 + int delay_cycle; 123 + unsigned int mask = 0; 124 + unsigned int val = 0; 125 + 126 + /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */ 127 + regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 128 + MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 129 + 130 + regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2); 131 + 132 + if (!param->mtkaif_calibration_ok) { 133 + dev_info(afe->dev, "%s(), calibration fail\n", __func__); 134 + return 0; 135 + } 136 + 137 + /* set delay for ch1, ch2 */ 138 + if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >= 139 + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) { 140 + delay_data = DELAY_DATA_MISO1; 141 + delay_cycle = 142 + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] - 143 + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]; 144 + } else { 145 + delay_data = DELAY_DATA_MISO0; 146 + delay_cycle = 147 + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] - 148 + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0]; 149 + } 150 + 151 + val = 0; 152 + mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 153 + val |= FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle); 154 + val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data); 155 + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val); 156 + 157 + return 0; 158 + } 159 + 160 + static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 161 + struct snd_kcontrol *kcontrol, 162 + int event) 163 + { 164 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 165 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 166 + 167 + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 168 + __func__, w->name, event); 169 + 170 + switch (event) { 171 + case SND_SOC_DAPM_PRE_PMU: 172 + mt8188_adda_mtkaif_init(afe); 173 + break; 174 + default: 175 + break; 176 + } 177 + 178 + return 0; 179 + } 180 + 181 + static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 182 + struct snd_kcontrol *kcontrol, 183 + int event) 184 + { 185 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 186 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 187 + 188 + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 189 + __func__, w->name, event); 190 + 191 + switch (event) { 192 + case SND_SOC_DAPM_POST_PMD: 193 + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 194 + usleep_range(125, 135); 195 + break; 196 + default: 197 + break; 198 + } 199 + 200 + return 0; 201 + } 202 + 203 + static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic) 204 + { 205 + unsigned int reg = AFE_ADDA_UL_SRC_CON0; 206 + unsigned int val; 207 + 208 + val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | 209 + UL_MODE_3P25M_CH2_CTL); 210 + 211 + /* turn on dmic, ch1, ch2 */ 212 + if (dmic) 213 + regmap_set_bits(afe->regmap, reg, val); 214 + else 215 + regmap_clear_bits(afe->regmap, reg, val); 216 + } 217 + 218 + static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 219 + struct snd_kcontrol *kcontrol, 220 + int event) 221 + { 222 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 223 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 224 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 225 + struct mtkaif_param *param = &afe_priv->mtkaif_params; 226 + 227 + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 228 + __func__, w->name, event); 229 + 230 + switch (event) { 231 + case SND_SOC_DAPM_PRE_PMU: 232 + mtk_adda_ul_mictype(afe, param->mtkaif_dmic_on); 233 + break; 234 + case SND_SOC_DAPM_POST_PMD: 235 + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 236 + usleep_range(125, 135); 237 + break; 238 + default: 239 + break; 240 + } 241 + 242 + return 0; 243 + } 244 + 245 + static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w, 246 + struct snd_kcontrol *kcontrol, 247 + int event) 248 + { 249 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 250 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 251 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 252 + struct clk *clk = afe_priv->clk[MT8188_CLK_TOP_AUDIO_H_SEL]; 253 + struct clk *clk_parent; 254 + 255 + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 256 + __func__, w->name, event); 257 + 258 + switch (event) { 259 + case SND_SOC_DAPM_PRE_PMU: 260 + clk_parent = afe_priv->clk[MT8188_CLK_APMIXED_APLL1]; 261 + break; 262 + case SND_SOC_DAPM_POST_PMD: 263 + clk_parent = afe_priv->clk[MT8188_CLK_XTAL_26M]; 264 + break; 265 + default: 266 + return 0; 267 + } 268 + mt8188_afe_set_clk_parent(afe, clk, clk_parent); 269 + 270 + return 0; 271 + } 272 + 273 + static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 274 + struct snd_soc_dapm_widget *sink) 275 + { 276 + struct snd_soc_dapm_widget *w = source; 277 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 278 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 279 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 280 + struct mtk_dai_adda_priv *adda_priv; 281 + 282 + adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 283 + 284 + if (!adda_priv) { 285 + dev_err(afe->dev, "%s adda_priv == NULL", __func__); 286 + return 0; 287 + } 288 + 289 + return !!(adda_priv->ul_rate > ADDA_HIRES_THRES); 290 + } 291 + 292 + static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 293 + struct snd_soc_dapm_widget *sink) 294 + { 295 + struct snd_soc_dapm_widget *w = source; 296 + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 297 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 298 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 299 + struct mtk_dai_adda_priv *adda_priv; 300 + 301 + adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 302 + 303 + if (!adda_priv) { 304 + dev_err(afe->dev, "%s adda_priv == NULL", __func__); 305 + return 0; 306 + } 307 + 308 + return !!(adda_priv->dl_rate > ADDA_HIRES_THRES); 309 + } 310 + 311 + static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = { 312 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0), 313 + SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0), 314 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0), 315 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0), 316 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0), 317 + }; 318 + 319 + static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = { 320 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0), 321 + SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0), 322 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0), 323 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0), 324 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0), 325 + }; 326 + 327 + static const char * const adda_dlgain_mux_map[] = { 328 + "Bypass", "Connect", 329 + }; 330 + 331 + static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum, 332 + SND_SOC_NOPM, 0, 333 + adda_dlgain_mux_map); 334 + 335 + static const struct snd_kcontrol_new adda_dlgain_mux_control = 336 + SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum); 337 + 338 + static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 339 + SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0), 340 + SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0), 341 + 342 + SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0, 343 + mtk_dai_adda_o176_mix, 344 + ARRAY_SIZE(mtk_dai_adda_o176_mix)), 345 + SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0, 346 + mtk_dai_adda_o177_mix, 347 + ARRAY_SIZE(mtk_dai_adda_o177_mix)), 348 + 349 + SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 350 + AFE_ADDA_UL_DL_CON0, 351 + ADDA_AFE_ON_SHIFT, 0, 352 + NULL, 353 + 0), 354 + 355 + SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 356 + AFE_ADDA_DL_SRC2_CON0, 357 + DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0, 358 + mtk_adda_dl_event, 359 + SND_SOC_DAPM_POST_PMD), 360 + 361 + SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 362 + AFE_ADDA_UL_SRC_CON0, 363 + UL_SRC_ON_TMP_CTL_SHIFT, 0, 364 + mtk_adda_ul_event, 365 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 366 + 367 + SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL, 368 + SND_SOC_NOPM, 369 + 0, 0, 370 + mtk_audio_hires_event, 371 + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 372 + 373 + SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 374 + SND_SOC_NOPM, 375 + 0, 0, 376 + mtk_adda_mtkaif_cfg_event, 377 + SND_SOC_DAPM_PRE_PMU), 378 + 379 + SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0, 380 + &adda_dlgain_mux_control), 381 + 382 + SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0, 383 + DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0), 384 + 385 + SND_SOC_DAPM_INPUT("ADDA_INPUT"), 386 + SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"), 387 + 388 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"), 389 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"), 390 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"), 391 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"), 392 + }; 393 + 394 + static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 395 + {"ADDA Capture", NULL, "ADDA Enable"}, 396 + {"ADDA Capture", NULL, "ADDA Capture Enable"}, 397 + {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 398 + {"ADDA Capture", NULL, "aud_adc"}, 399 + {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adc_hires_connect}, 400 + {"aud_adc_hires", NULL, "AUDIO_HIRES"}, 401 + 402 + {"I168", NULL, "ADDA Capture"}, 403 + {"I169", NULL, "ADDA Capture"}, 404 + 405 + {"ADDA Playback", NULL, "ADDA Enable"}, 406 + {"ADDA Playback", NULL, "ADDA Playback Enable"}, 407 + {"ADDA Playback", NULL, "aud_dac"}, 408 + {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_dac_hires_connect}, 409 + {"aud_dac_hires", NULL, "AUDIO_HIRES"}, 410 + 411 + {"DL_GAIN", NULL, "O176"}, 412 + {"DL_GAIN", NULL, "O177"}, 413 + 414 + {"DL_GAIN_MUX", "Bypass", "O176"}, 415 + {"DL_GAIN_MUX", "Bypass", "O177"}, 416 + {"DL_GAIN_MUX", "Connect", "DL_GAIN"}, 417 + 418 + {"ADDA Playback", NULL, "DL_GAIN_MUX"}, 419 + 420 + {"O176", "I000 Switch", "I000"}, 421 + {"O177", "I001 Switch", "I001"}, 422 + 423 + {"O176", "I002 Switch", "I002"}, 424 + {"O177", "I003 Switch", "I003"}, 425 + 426 + {"O176", "I020 Switch", "I020"}, 427 + {"O177", "I021 Switch", "I021"}, 428 + 429 + {"O176", "I022 Switch", "I022"}, 430 + {"O177", "I023 Switch", "I023"}, 431 + 432 + {"O176", "I070 Switch", "I070"}, 433 + {"O177", "I071 Switch", "I071"}, 434 + 435 + {"ADDA Capture", NULL, "ADDA_INPUT"}, 436 + {"ADDA_OUTPUT", NULL, "ADDA Playback"}, 437 + }; 438 + 439 + static int mt8188_adda_dmic_get(struct snd_kcontrol *kcontrol, 440 + struct snd_ctl_elem_value *ucontrol) 441 + { 442 + struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 443 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 444 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 445 + struct mtkaif_param *param = &afe_priv->mtkaif_params; 446 + 447 + ucontrol->value.integer.value[0] = param->mtkaif_dmic_on; 448 + return 0; 449 + } 450 + 451 + static int mt8188_adda_dmic_set(struct snd_kcontrol *kcontrol, 452 + struct snd_ctl_elem_value *ucontrol) 453 + { 454 + struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 455 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 456 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 457 + struct mtkaif_param *param = &afe_priv->mtkaif_params; 458 + int dmic_on; 459 + 460 + dmic_on = !!ucontrol->value.integer.value[0]; 461 + 462 + dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 463 + __func__, kcontrol->id.name, dmic_on); 464 + 465 + if (param->mtkaif_dmic_on == dmic_on) 466 + return 0; 467 + 468 + param->mtkaif_dmic_on = dmic_on; 469 + return 1; 470 + } 471 + 472 + static const struct snd_kcontrol_new mtk_dai_adda_controls[] = { 473 + SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 474 + DL_2_GAIN_CTL_PRE_SHIFT, 65535, 0), 475 + SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 476 + mt8188_adda_dmic_get, mt8188_adda_dmic_set), 477 + }; 478 + 479 + static int mtk_dai_da_configure(struct mtk_base_afe *afe, 480 + unsigned int rate, int id) 481 + { 482 + unsigned int val = 0; 483 + unsigned int mask = 0; 484 + 485 + /* set sampling rate */ 486 + mask |= DL_2_INPUT_MODE_CTL_MASK; 487 + val |= FIELD_PREP(DL_2_INPUT_MODE_CTL_MASK, 488 + afe_adda_dl_rate_transform(afe, rate)); 489 + 490 + /* turn off saturation */ 491 + mask |= DL_2_CH1_SATURATION_EN_CTL; 492 + mask |= DL_2_CH2_SATURATION_EN_CTL; 493 + 494 + /* turn off mute function */ 495 + mask |= DL_2_MUTE_CH1_OFF_CTL_PRE; 496 + mask |= DL_2_MUTE_CH2_OFF_CTL_PRE; 497 + val |= DL_2_MUTE_CH1_OFF_CTL_PRE; 498 + val |= DL_2_MUTE_CH2_OFF_CTL_PRE; 499 + 500 + /* set voice input data if input sample rate is 8k or 16k */ 501 + mask |= DL_2_VOICE_MODE_CTL_PRE; 502 + if (rate == 8000 || rate == 16000) 503 + val |= DL_2_VOICE_MODE_CTL_PRE; 504 + 505 + regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val); 506 + 507 + /* new 2nd sdm */ 508 + regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, 509 + DL_USE_NEW_2ND_SDM); 510 + 511 + return 0; 512 + } 513 + 514 + static int mtk_dai_ad_configure(struct mtk_base_afe *afe, 515 + unsigned int rate, int id) 516 + { 517 + unsigned int val; 518 + unsigned int mask; 519 + 520 + mask = UL_VOICE_MODE_CTL_MASK; 521 + val = FIELD_PREP(UL_VOICE_MODE_CTL_MASK, 522 + afe_adda_ul_rate_transform(afe, rate)); 523 + 524 + regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 525 + mask, val); 526 + return 0; 527 + } 528 + 529 + static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 530 + struct snd_pcm_hw_params *params, 531 + struct snd_soc_dai *dai) 532 + { 533 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 534 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 535 + struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id]; 536 + unsigned int rate = params_rate(params); 537 + int id = dai->id; 538 + int ret = 0; 539 + 540 + dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %u\n", 541 + __func__, id, substream->stream, rate); 542 + 543 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 544 + adda_priv->dl_rate = rate; 545 + ret = mtk_dai_da_configure(afe, rate, id); 546 + } else { 547 + adda_priv->ul_rate = rate; 548 + ret = mtk_dai_ad_configure(afe, rate, id); 549 + } 550 + 551 + return ret; 552 + } 553 + 554 + static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 555 + .hw_params = mtk_dai_adda_hw_params, 556 + }; 557 + 558 + /* dai driver */ 559 + #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 560 + SNDRV_PCM_RATE_96000 |\ 561 + SNDRV_PCM_RATE_192000) 562 + 563 + #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 564 + SNDRV_PCM_RATE_16000 |\ 565 + SNDRV_PCM_RATE_32000 |\ 566 + SNDRV_PCM_RATE_48000 |\ 567 + SNDRV_PCM_RATE_96000 |\ 568 + SNDRV_PCM_RATE_192000) 569 + 570 + #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 571 + SNDRV_PCM_FMTBIT_S24_LE |\ 572 + SNDRV_PCM_FMTBIT_S32_LE) 573 + 574 + static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 575 + { 576 + .name = "ADDA", 577 + .id = MT8188_AFE_IO_ADDA, 578 + .playback = { 579 + .stream_name = "ADDA Playback", 580 + .channels_min = 1, 581 + .channels_max = 2, 582 + .rates = MTK_ADDA_PLAYBACK_RATES, 583 + .formats = MTK_ADDA_FORMATS, 584 + }, 585 + .capture = { 586 + .stream_name = "ADDA Capture", 587 + .channels_min = 1, 588 + .channels_max = 2, 589 + .rates = MTK_ADDA_CAPTURE_RATES, 590 + .formats = MTK_ADDA_FORMATS, 591 + }, 592 + .ops = &mtk_dai_adda_ops, 593 + }, 594 + }; 595 + 596 + static int init_adda_priv_data(struct mtk_base_afe *afe) 597 + { 598 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 599 + struct mtk_dai_adda_priv *adda_priv; 600 + 601 + adda_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_adda_priv), 602 + GFP_KERNEL); 603 + if (!adda_priv) 604 + return -ENOMEM; 605 + 606 + afe_priv->dai_priv[MT8188_AFE_IO_ADDA] = adda_priv; 607 + 608 + return 0; 609 + } 610 + 611 + int mt8188_dai_adda_register(struct mtk_base_afe *afe) 612 + { 613 + struct mtk_base_afe_dai *dai; 614 + 615 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 616 + if (!dai) 617 + return -ENOMEM; 618 + 619 + list_add(&dai->list, &afe->sub_dais); 620 + 621 + dai->dai_drivers = mtk_dai_adda_driver; 622 + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 623 + 624 + dai->dapm_widgets = mtk_dai_adda_widgets; 625 + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 626 + dai->dapm_routes = mtk_dai_adda_routes; 627 + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 628 + dai->controls = mtk_dai_adda_controls; 629 + dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls); 630 + 631 + return init_adda_priv_data(afe); 632 + }

+2588

sound/soc/mediatek/mt8188/mt8188-dai-etdm.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * MediaTek ALSA SoC Audio DAI eTDM Control 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #include <linux/bitfield.h> 12 + #include <linux/pm_runtime.h> 13 + #include <linux/regmap.h> 14 + #include <sound/pcm_params.h> 15 + #include "mt8188-afe-clk.h" 16 + #include "mt8188-afe-common.h" 17 + #include "mt8188-reg.h" 18 + 19 + #define MT8188_ETDM_MAX_CHANNELS 16 20 + #define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000 21 + #define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START) 22 + #define ENUM_TO_STR(x) #x 23 + 24 + enum { 25 + MTK_DAI_ETDM_FORMAT_I2S = 0, 26 + MTK_DAI_ETDM_FORMAT_LJ, 27 + MTK_DAI_ETDM_FORMAT_RJ, 28 + MTK_DAI_ETDM_FORMAT_EIAJ, 29 + MTK_DAI_ETDM_FORMAT_DSPA, 30 + MTK_DAI_ETDM_FORMAT_DSPB, 31 + }; 32 + 33 + enum { 34 + MTK_DAI_ETDM_DATA_ONE_PIN = 0, 35 + MTK_DAI_ETDM_DATA_MULTI_PIN, 36 + }; 37 + 38 + enum { 39 + ETDM_IN, 40 + ETDM_OUT, 41 + }; 42 + 43 + enum { 44 + COWORK_ETDM_NONE = 0, 45 + COWORK_ETDM_IN1_M = 2, 46 + COWORK_ETDM_IN1_S = 3, 47 + COWORK_ETDM_IN2_M = 4, 48 + COWORK_ETDM_IN2_S = 5, 49 + COWORK_ETDM_OUT1_M = 10, 50 + COWORK_ETDM_OUT1_S = 11, 51 + COWORK_ETDM_OUT2_M = 12, 52 + COWORK_ETDM_OUT2_S = 13, 53 + COWORK_ETDM_OUT3_M = 14, 54 + COWORK_ETDM_OUT3_S = 15, 55 + }; 56 + 57 + enum { 58 + ETDM_RELATCH_TIMING_A1A2SYS, 59 + ETDM_RELATCH_TIMING_A3SYS, 60 + ETDM_RELATCH_TIMING_A4SYS, 61 + }; 62 + 63 + enum { 64 + ETDM_SYNC_NONE, 65 + ETDM_SYNC_FROM_IN1 = 2, 66 + ETDM_SYNC_FROM_IN2 = 4, 67 + ETDM_SYNC_FROM_OUT1 = 10, 68 + ETDM_SYNC_FROM_OUT2 = 12, 69 + ETDM_SYNC_FROM_OUT3 = 14, 70 + }; 71 + 72 + struct etdm_con_reg { 73 + unsigned int con0; 74 + unsigned int con1; 75 + unsigned int con2; 76 + unsigned int con3; 77 + unsigned int con4; 78 + unsigned int con5; 79 + }; 80 + 81 + struct mtk_dai_etdm_rate { 82 + unsigned int rate; 83 + unsigned int reg_value; 84 + }; 85 + 86 + struct mtk_dai_etdm_priv { 87 + unsigned int clock_mode; 88 + unsigned int data_mode; 89 + bool slave_mode; 90 + bool lrck_inv; 91 + bool bck_inv; 92 + unsigned int format; 93 + unsigned int slots; 94 + unsigned int lrck_width; 95 + unsigned int mclk_freq; 96 + unsigned int mclk_fixed_apll; 97 + unsigned int mclk_apll; 98 + unsigned int mclk_dir; 99 + int cowork_source_id; //dai id 100 + unsigned int cowork_slv_count; 101 + int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 102 + bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 103 + unsigned int en_ref_cnt; 104 + bool is_prepared; 105 + }; 106 + 107 + static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { 108 + { .rate = 8000, .reg_value = 0, }, 109 + { .rate = 12000, .reg_value = 1, }, 110 + { .rate = 16000, .reg_value = 2, }, 111 + { .rate = 24000, .reg_value = 3, }, 112 + { .rate = 32000, .reg_value = 4, }, 113 + { .rate = 48000, .reg_value = 5, }, 114 + { .rate = 96000, .reg_value = 7, }, 115 + { .rate = 192000, .reg_value = 9, }, 116 + { .rate = 384000, .reg_value = 11, }, 117 + { .rate = 11025, .reg_value = 16, }, 118 + { .rate = 22050, .reg_value = 17, }, 119 + { .rate = 44100, .reg_value = 18, }, 120 + { .rate = 88200, .reg_value = 19, }, 121 + { .rate = 176400, .reg_value = 20, }, 122 + { .rate = 352800, .reg_value = 21, }, 123 + }; 124 + 125 + static int get_etdm_fs_timing(unsigned int rate) 126 + { 127 + int i; 128 + 129 + for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++) 130 + if (mt8188_etdm_rates[i].rate == rate) 131 + return mt8188_etdm_rates[i].reg_value; 132 + 133 + return -EINVAL; 134 + } 135 + 136 + static unsigned int get_etdm_ch_fixup(unsigned int channels) 137 + { 138 + if (channels > 16) 139 + return 24; 140 + else if (channels > 8) 141 + return 16; 142 + else if (channels > 4) 143 + return 8; 144 + else if (channels > 2) 145 + return 4; 146 + else 147 + return 2; 148 + } 149 + 150 + static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 151 + { 152 + switch (dai_id) { 153 + case MT8188_AFE_IO_ETDM1_IN: 154 + etdm_reg->con0 = ETDM_IN1_CON0; 155 + etdm_reg->con1 = ETDM_IN1_CON1; 156 + etdm_reg->con2 = ETDM_IN1_CON2; 157 + etdm_reg->con3 = ETDM_IN1_CON3; 158 + etdm_reg->con4 = ETDM_IN1_CON4; 159 + etdm_reg->con5 = ETDM_IN1_CON5; 160 + break; 161 + case MT8188_AFE_IO_ETDM2_IN: 162 + etdm_reg->con0 = ETDM_IN2_CON0; 163 + etdm_reg->con1 = ETDM_IN2_CON1; 164 + etdm_reg->con2 = ETDM_IN2_CON2; 165 + etdm_reg->con3 = ETDM_IN2_CON3; 166 + etdm_reg->con4 = ETDM_IN2_CON4; 167 + etdm_reg->con5 = ETDM_IN2_CON5; 168 + break; 169 + case MT8188_AFE_IO_ETDM1_OUT: 170 + etdm_reg->con0 = ETDM_OUT1_CON0; 171 + etdm_reg->con1 = ETDM_OUT1_CON1; 172 + etdm_reg->con2 = ETDM_OUT1_CON2; 173 + etdm_reg->con3 = ETDM_OUT1_CON3; 174 + etdm_reg->con4 = ETDM_OUT1_CON4; 175 + etdm_reg->con5 = ETDM_OUT1_CON5; 176 + break; 177 + case MT8188_AFE_IO_ETDM2_OUT: 178 + etdm_reg->con0 = ETDM_OUT2_CON0; 179 + etdm_reg->con1 = ETDM_OUT2_CON1; 180 + etdm_reg->con2 = ETDM_OUT2_CON2; 181 + etdm_reg->con3 = ETDM_OUT2_CON3; 182 + etdm_reg->con4 = ETDM_OUT2_CON4; 183 + etdm_reg->con5 = ETDM_OUT2_CON5; 184 + break; 185 + case MT8188_AFE_IO_ETDM3_OUT: 186 + case MT8188_AFE_IO_DPTX: 187 + etdm_reg->con0 = ETDM_OUT3_CON0; 188 + etdm_reg->con1 = ETDM_OUT3_CON1; 189 + etdm_reg->con2 = ETDM_OUT3_CON2; 190 + etdm_reg->con3 = ETDM_OUT3_CON3; 191 + etdm_reg->con4 = ETDM_OUT3_CON4; 192 + etdm_reg->con5 = ETDM_OUT3_CON5; 193 + break; 194 + default: 195 + return -EINVAL; 196 + } 197 + return 0; 198 + } 199 + 200 + static int get_etdm_dir(unsigned int dai_id) 201 + { 202 + switch (dai_id) { 203 + case MT8188_AFE_IO_ETDM1_IN: 204 + case MT8188_AFE_IO_ETDM2_IN: 205 + return ETDM_IN; 206 + case MT8188_AFE_IO_ETDM1_OUT: 207 + case MT8188_AFE_IO_ETDM2_OUT: 208 + case MT8188_AFE_IO_ETDM3_OUT: 209 + return ETDM_OUT; 210 + default: 211 + return -EINVAL; 212 + } 213 + } 214 + 215 + static int get_etdm_wlen(unsigned int bitwidth) 216 + { 217 + return bitwidth <= 16 ? 16 : 32; 218 + } 219 + 220 + static bool is_valid_etdm_dai(int dai_id) 221 + { 222 + switch (dai_id) { 223 + case MT8188_AFE_IO_ETDM1_IN: 224 + fallthrough; 225 + case MT8188_AFE_IO_ETDM2_IN: 226 + fallthrough; 227 + case MT8188_AFE_IO_ETDM1_OUT: 228 + fallthrough; 229 + case MT8188_AFE_IO_ETDM2_OUT: 230 + fallthrough; 231 + case MT8188_AFE_IO_DPTX: 232 + fallthrough; 233 + case MT8188_AFE_IO_ETDM3_OUT: 234 + return true; 235 + default: 236 + return false; 237 + } 238 + } 239 + 240 + static int is_cowork_mode(struct snd_soc_dai *dai) 241 + { 242 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 243 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 244 + struct mtk_dai_etdm_priv *etdm_data; 245 + 246 + if (!is_valid_etdm_dai(dai->id)) 247 + return -EINVAL; 248 + etdm_data = afe_priv->dai_priv[dai->id]; 249 + 250 + return (etdm_data->cowork_slv_count > 0 || 251 + etdm_data->cowork_source_id != COWORK_ETDM_NONE); 252 + } 253 + 254 + static int sync_to_dai_id(int source_sel) 255 + { 256 + switch (source_sel) { 257 + case ETDM_SYNC_FROM_IN1: 258 + return MT8188_AFE_IO_ETDM1_IN; 259 + case ETDM_SYNC_FROM_IN2: 260 + return MT8188_AFE_IO_ETDM2_IN; 261 + case ETDM_SYNC_FROM_OUT1: 262 + return MT8188_AFE_IO_ETDM1_OUT; 263 + case ETDM_SYNC_FROM_OUT2: 264 + return MT8188_AFE_IO_ETDM2_OUT; 265 + case ETDM_SYNC_FROM_OUT3: 266 + return MT8188_AFE_IO_ETDM3_OUT; 267 + default: 268 + return 0; 269 + } 270 + } 271 + 272 + static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 273 + { 274 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 275 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 276 + struct mtk_dai_etdm_priv *etdm_data; 277 + int dai_id; 278 + 279 + if (!is_valid_etdm_dai(dai->id)) 280 + return -EINVAL; 281 + etdm_data = afe_priv->dai_priv[dai->id]; 282 + dai_id = etdm_data->cowork_source_id; 283 + 284 + if (dai_id == COWORK_ETDM_NONE) 285 + dai_id = dai->id; 286 + 287 + return dai_id; 288 + } 289 + 290 + static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 291 + { 292 + switch (dai_id) { 293 + case MT8188_AFE_IO_DPTX: 294 + return MT8188_CLK_AUD_HDMI_OUT; 295 + case MT8188_AFE_IO_ETDM1_IN: 296 + return MT8188_CLK_AUD_TDM_IN; 297 + case MT8188_AFE_IO_ETDM2_IN: 298 + return MT8188_CLK_AUD_I2SIN; 299 + case MT8188_AFE_IO_ETDM1_OUT: 300 + return MT8188_CLK_AUD_TDM_OUT; 301 + case MT8188_AFE_IO_ETDM2_OUT: 302 + return MT8188_CLK_AUD_I2S_OUT; 303 + case MT8188_AFE_IO_ETDM3_OUT: 304 + return MT8188_CLK_AUD_HDMI_OUT; 305 + default: 306 + return -EINVAL; 307 + } 308 + } 309 + 310 + static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 311 + { 312 + switch (dai_id) { 313 + case MT8188_AFE_IO_DPTX: 314 + return MT8188_CLK_TOP_DPTX_M_SEL; 315 + case MT8188_AFE_IO_ETDM1_IN: 316 + return MT8188_CLK_TOP_I2SI1_M_SEL; 317 + case MT8188_AFE_IO_ETDM2_IN: 318 + return MT8188_CLK_TOP_I2SI2_M_SEL; 319 + case MT8188_AFE_IO_ETDM1_OUT: 320 + return MT8188_CLK_TOP_I2SO1_M_SEL; 321 + case MT8188_AFE_IO_ETDM2_OUT: 322 + return MT8188_CLK_TOP_I2SO2_M_SEL; 323 + case MT8188_AFE_IO_ETDM3_OUT: 324 + default: 325 + return -EINVAL; 326 + } 327 + } 328 + 329 + static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 330 + { 331 + switch (dai_id) { 332 + case MT8188_AFE_IO_DPTX: 333 + return MT8188_CLK_TOP_APLL12_DIV9; 334 + case MT8188_AFE_IO_ETDM1_IN: 335 + return MT8188_CLK_TOP_APLL12_DIV0; 336 + case MT8188_AFE_IO_ETDM2_IN: 337 + return MT8188_CLK_TOP_APLL12_DIV1; 338 + case MT8188_AFE_IO_ETDM1_OUT: 339 + return MT8188_CLK_TOP_APLL12_DIV2; 340 + case MT8188_AFE_IO_ETDM2_OUT: 341 + return MT8188_CLK_TOP_APLL12_DIV3; 342 + case MT8188_AFE_IO_ETDM3_OUT: 343 + default: 344 + return -EINVAL; 345 + } 346 + } 347 + 348 + static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 349 + { 350 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 351 + int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 352 + 353 + if (clkdiv_id < 0) 354 + return -EINVAL; 355 + 356 + mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 357 + 358 + return 0; 359 + } 360 + 361 + static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 362 + { 363 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 364 + int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 365 + 366 + if (clkdiv_id < 0) 367 + return -EINVAL; 368 + 369 + mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 370 + 371 + return 0; 372 + } 373 + 374 + static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 375 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 376 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 377 + SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 378 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 379 + }; 380 + 381 + static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 382 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 383 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 384 + SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 385 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 386 + }; 387 + 388 + static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 389 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 390 + SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 391 + }; 392 + 393 + static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 394 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 395 + SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 396 + }; 397 + 398 + static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 399 + SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 400 + SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 401 + }; 402 + 403 + static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 404 + SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 405 + SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 406 + }; 407 + 408 + static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 409 + SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 410 + SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 411 + }; 412 + 413 + static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 414 + SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 415 + SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 416 + }; 417 + 418 + static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 419 + SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 420 + SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 421 + }; 422 + 423 + static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 424 + SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 425 + SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 426 + }; 427 + 428 + static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 429 + SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 430 + SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 431 + }; 432 + 433 + static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 434 + SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 435 + SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 436 + }; 437 + 438 + static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 439 + SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 440 + SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 441 + }; 442 + 443 + static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 444 + SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 445 + SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 446 + }; 447 + 448 + static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 449 + SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 450 + SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 451 + }; 452 + 453 + static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 454 + SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 455 + SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 456 + }; 457 + 458 + static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 459 + SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 460 + SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 461 + SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 462 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 463 + }; 464 + 465 + static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 466 + SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 467 + SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 468 + SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 469 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 470 + }; 471 + 472 + static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 473 + SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 474 + SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 475 + }; 476 + 477 + static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 478 + SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 479 + SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 480 + }; 481 + 482 + static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 483 + SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 484 + SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 485 + }; 486 + 487 + static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 488 + SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 489 + SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 490 + }; 491 + 492 + static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 493 + SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 494 + SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 495 + }; 496 + 497 + static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 498 + SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 499 + SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 500 + }; 501 + 502 + static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 503 + SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 504 + SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 505 + }; 506 + 507 + static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 508 + SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 509 + SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 510 + }; 511 + 512 + static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 513 + SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 514 + SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 515 + }; 516 + 517 + static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 518 + SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 519 + SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 520 + }; 521 + 522 + static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 523 + SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 524 + SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 525 + }; 526 + 527 + static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 528 + SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 529 + SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 530 + }; 531 + 532 + static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 533 + SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 534 + SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 535 + }; 536 + 537 + static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 538 + SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 539 + SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 540 + }; 541 + 542 + static const char * const mt8188_etdm_clk_src_sel_text[] = { 543 + "26m", 544 + "a1sys_a2sys", 545 + "a3sys", 546 + "a4sys", 547 + }; 548 + 549 + static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 550 + mt8188_etdm_clk_src_sel_text); 551 + 552 + static const char * const hdmitx_dptx_mux_map[] = { 553 + "Disconnect", "Connect", 554 + }; 555 + 556 + static int hdmitx_dptx_mux_map_value[] = { 557 + 0, 1, 558 + }; 559 + 560 + /* HDMI_OUT_MUX */ 561 + static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 562 + SND_SOC_NOPM, 563 + 0, 564 + 1, 565 + hdmitx_dptx_mux_map, 566 + hdmitx_dptx_mux_map_value); 567 + 568 + static const struct snd_kcontrol_new hdmi_out_mux_control = 569 + SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 570 + 571 + /* DPTX_OUT_MUX */ 572 + static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 573 + SND_SOC_NOPM, 574 + 0, 575 + 1, 576 + hdmitx_dptx_mux_map, 577 + hdmitx_dptx_mux_map_value); 578 + 579 + static const struct snd_kcontrol_new dptx_out_mux_control = 580 + SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 581 + 582 + /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 583 + static const char *const afe_conn_hdmi_mux_map[] = { 584 + "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 585 + }; 586 + 587 + static int afe_conn_hdmi_mux_map_value[] = { 588 + 0, 1, 2, 3, 4, 5, 6, 7, 589 + }; 590 + 591 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 592 + AFE_TDMOUT_CONN0, 593 + 0, 594 + 0xf, 595 + afe_conn_hdmi_mux_map, 596 + afe_conn_hdmi_mux_map_value); 597 + 598 + static const struct snd_kcontrol_new hdmi_ch0_mux_control = 599 + SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 600 + 601 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 602 + AFE_TDMOUT_CONN0, 603 + 4, 604 + 0xf, 605 + afe_conn_hdmi_mux_map, 606 + afe_conn_hdmi_mux_map_value); 607 + 608 + static const struct snd_kcontrol_new hdmi_ch1_mux_control = 609 + SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 610 + 611 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 612 + AFE_TDMOUT_CONN0, 613 + 8, 614 + 0xf, 615 + afe_conn_hdmi_mux_map, 616 + afe_conn_hdmi_mux_map_value); 617 + 618 + static const struct snd_kcontrol_new hdmi_ch2_mux_control = 619 + SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 620 + 621 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 622 + AFE_TDMOUT_CONN0, 623 + 12, 624 + 0xf, 625 + afe_conn_hdmi_mux_map, 626 + afe_conn_hdmi_mux_map_value); 627 + 628 + static const struct snd_kcontrol_new hdmi_ch3_mux_control = 629 + SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 630 + 631 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 632 + AFE_TDMOUT_CONN0, 633 + 16, 634 + 0xf, 635 + afe_conn_hdmi_mux_map, 636 + afe_conn_hdmi_mux_map_value); 637 + 638 + static const struct snd_kcontrol_new hdmi_ch4_mux_control = 639 + SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 640 + 641 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 642 + AFE_TDMOUT_CONN0, 643 + 20, 644 + 0xf, 645 + afe_conn_hdmi_mux_map, 646 + afe_conn_hdmi_mux_map_value); 647 + 648 + static const struct snd_kcontrol_new hdmi_ch5_mux_control = 649 + SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 650 + 651 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 652 + AFE_TDMOUT_CONN0, 653 + 24, 654 + 0xf, 655 + afe_conn_hdmi_mux_map, 656 + afe_conn_hdmi_mux_map_value); 657 + 658 + static const struct snd_kcontrol_new hdmi_ch6_mux_control = 659 + SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 660 + 661 + static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 662 + AFE_TDMOUT_CONN0, 663 + 28, 664 + 0xf, 665 + afe_conn_hdmi_mux_map, 666 + afe_conn_hdmi_mux_map_value); 667 + 668 + static const struct snd_kcontrol_new hdmi_ch7_mux_control = 669 + SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 670 + 671 + static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 672 + struct snd_ctl_elem_value *ucontrol) 673 + { 674 + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 675 + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 676 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 677 + unsigned int source = ucontrol->value.enumerated.item[0]; 678 + unsigned int val; 679 + unsigned int old_val; 680 + unsigned int mask; 681 + unsigned int reg; 682 + unsigned int shift; 683 + 684 + if (source >= e->items) 685 + return -EINVAL; 686 + 687 + if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 688 + reg = ETDM_OUT1_CON4; 689 + mask = ETDM_OUT_CON4_CLOCK_MASK; 690 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 691 + val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 692 + } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 693 + reg = ETDM_OUT2_CON4; 694 + mask = ETDM_OUT_CON4_CLOCK_MASK; 695 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 696 + val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 697 + } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 698 + reg = ETDM_OUT3_CON4; 699 + mask = ETDM_OUT_CON4_CLOCK_MASK; 700 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 701 + val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 702 + } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 703 + reg = ETDM_IN1_CON2; 704 + mask = ETDM_IN_CON2_CLOCK_MASK; 705 + shift = ETDM_IN_CON2_CLOCK_SHIFT; 706 + val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 707 + } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 708 + reg = ETDM_IN2_CON2; 709 + mask = ETDM_IN_CON2_CLOCK_MASK; 710 + shift = ETDM_IN_CON2_CLOCK_SHIFT; 711 + val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 712 + } else { 713 + return -EINVAL; 714 + } 715 + 716 + regmap_read(afe->regmap, reg, &old_val); 717 + old_val &= mask; 718 + old_val >>= shift; 719 + 720 + if (old_val == val) 721 + return 0; 722 + 723 + regmap_update_bits(afe->regmap, reg, mask, val); 724 + 725 + return 1; 726 + } 727 + 728 + static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 729 + struct snd_ctl_elem_value *ucontrol) 730 + { 731 + struct snd_soc_component *component = 732 + snd_soc_kcontrol_component(kcontrol); 733 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 734 + unsigned int value; 735 + unsigned int reg; 736 + unsigned int mask; 737 + unsigned int shift; 738 + 739 + if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 740 + reg = ETDM_OUT1_CON4; 741 + mask = ETDM_OUT_CON4_CLOCK_MASK; 742 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 743 + } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 744 + reg = ETDM_OUT2_CON4; 745 + mask = ETDM_OUT_CON4_CLOCK_MASK; 746 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 747 + } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 748 + reg = ETDM_OUT3_CON4; 749 + mask = ETDM_OUT_CON4_CLOCK_MASK; 750 + shift = ETDM_OUT_CON4_CLOCK_SHIFT; 751 + } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 752 + reg = ETDM_IN1_CON2; 753 + mask = ETDM_IN_CON2_CLOCK_MASK; 754 + shift = ETDM_IN_CON2_CLOCK_SHIFT; 755 + } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 756 + reg = ETDM_IN2_CON2; 757 + mask = ETDM_IN_CON2_CLOCK_MASK; 758 + shift = ETDM_IN_CON2_CLOCK_SHIFT; 759 + } else { 760 + return -EINVAL; 761 + } 762 + 763 + regmap_read(afe->regmap, reg, &value); 764 + 765 + value &= mask; 766 + value >>= shift; 767 + ucontrol->value.enumerated.item[0] = value; 768 + return 0; 769 + } 770 + 771 + static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 772 + SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum, 773 + mt8188_etdm_clk_src_sel_get, 774 + mt8188_etdm_clk_src_sel_put), 775 + SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum, 776 + mt8188_etdm_clk_src_sel_get, 777 + mt8188_etdm_clk_src_sel_put), 778 + SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum, 779 + mt8188_etdm_clk_src_sel_get, 780 + mt8188_etdm_clk_src_sel_put), 781 + SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum, 782 + mt8188_etdm_clk_src_sel_get, 783 + mt8188_etdm_clk_src_sel_put), 784 + SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum, 785 + mt8188_etdm_clk_src_sel_get, 786 + mt8188_etdm_clk_src_sel_put), 787 + }; 788 + 789 + static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 790 + /* eTDM_IN2 */ 791 + SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 792 + SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 793 + SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 794 + SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 795 + SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 796 + SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 797 + SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 798 + SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 799 + SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0), 800 + SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0), 801 + SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0), 802 + SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0), 803 + SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0), 804 + SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0), 805 + SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0), 806 + SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0), 807 + 808 + /* eTDM_IN1 */ 809 + SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 810 + SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 811 + SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 812 + SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 813 + SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 814 + SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 815 + SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 816 + SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 817 + SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 818 + SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 819 + SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 820 + SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 821 + SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 822 + SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 823 + SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 824 + SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 825 + 826 + /* eTDM_OUT2 */ 827 + SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 828 + mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 829 + SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 830 + mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 831 + SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 832 + mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 833 + SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 834 + mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 835 + SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 836 + mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 837 + SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 838 + mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 839 + SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 840 + mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 841 + SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 842 + mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 843 + SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 844 + mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 845 + SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 846 + mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 847 + SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 848 + mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 849 + SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 850 + mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 851 + SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 852 + mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 853 + SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 854 + mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 855 + SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 856 + mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 857 + SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 858 + mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 859 + 860 + /* eTDM_OUT1 */ 861 + SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 862 + mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 863 + SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 864 + mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 865 + SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 866 + mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 867 + SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 868 + mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 869 + SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 870 + mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 871 + SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 872 + mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 873 + SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 874 + mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 875 + SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 876 + mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 877 + SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 878 + mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 879 + SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 880 + mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 881 + SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 882 + mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 883 + SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 884 + mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 885 + SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 886 + mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 887 + SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 888 + mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 889 + SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 890 + mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 891 + SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 892 + mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 893 + 894 + /* eTDM_OUT3 */ 895 + SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 896 + &hdmi_out_mux_control), 897 + SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 898 + &dptx_out_mux_control), 899 + 900 + SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 901 + &hdmi_ch0_mux_control), 902 + SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 903 + &hdmi_ch1_mux_control), 904 + SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 905 + &hdmi_ch2_mux_control), 906 + SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 907 + &hdmi_ch3_mux_control), 908 + SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 909 + &hdmi_ch4_mux_control), 910 + SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 911 + &hdmi_ch5_mux_control), 912 + SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 913 + &hdmi_ch6_mux_control), 914 + SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 915 + &hdmi_ch7_mux_control), 916 + 917 + SND_SOC_DAPM_INPUT("ETDM_INPUT"), 918 + SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 919 + }; 920 + 921 + static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 922 + {"I012", NULL, "ETDM2_IN"}, 923 + {"I013", NULL, "ETDM2_IN"}, 924 + {"I014", NULL, "ETDM2_IN"}, 925 + {"I015", NULL, "ETDM2_IN"}, 926 + {"I016", NULL, "ETDM2_IN"}, 927 + {"I017", NULL, "ETDM2_IN"}, 928 + {"I018", NULL, "ETDM2_IN"}, 929 + {"I019", NULL, "ETDM2_IN"}, 930 + {"I188", NULL, "ETDM2_IN"}, 931 + {"I189", NULL, "ETDM2_IN"}, 932 + {"I190", NULL, "ETDM2_IN"}, 933 + {"I191", NULL, "ETDM2_IN"}, 934 + {"I192", NULL, "ETDM2_IN"}, 935 + {"I193", NULL, "ETDM2_IN"}, 936 + {"I194", NULL, "ETDM2_IN"}, 937 + {"I195", NULL, "ETDM2_IN"}, 938 + 939 + {"I072", NULL, "ETDM1_IN"}, 940 + {"I073", NULL, "ETDM1_IN"}, 941 + {"I074", NULL, "ETDM1_IN"}, 942 + {"I075", NULL, "ETDM1_IN"}, 943 + {"I076", NULL, "ETDM1_IN"}, 944 + {"I077", NULL, "ETDM1_IN"}, 945 + {"I078", NULL, "ETDM1_IN"}, 946 + {"I079", NULL, "ETDM1_IN"}, 947 + {"I080", NULL, "ETDM1_IN"}, 948 + {"I081", NULL, "ETDM1_IN"}, 949 + {"I082", NULL, "ETDM1_IN"}, 950 + {"I083", NULL, "ETDM1_IN"}, 951 + {"I084", NULL, "ETDM1_IN"}, 952 + {"I085", NULL, "ETDM1_IN"}, 953 + {"I086", NULL, "ETDM1_IN"}, 954 + {"I087", NULL, "ETDM1_IN"}, 955 + 956 + {"UL8", NULL, "ETDM1_IN"}, 957 + {"UL3", NULL, "ETDM2_IN"}, 958 + 959 + {"ETDM2_OUT", NULL, "O048"}, 960 + {"ETDM2_OUT", NULL, "O049"}, 961 + {"ETDM2_OUT", NULL, "O050"}, 962 + {"ETDM2_OUT", NULL, "O051"}, 963 + {"ETDM2_OUT", NULL, "O052"}, 964 + {"ETDM2_OUT", NULL, "O053"}, 965 + {"ETDM2_OUT", NULL, "O054"}, 966 + {"ETDM2_OUT", NULL, "O055"}, 967 + {"ETDM2_OUT", NULL, "O056"}, 968 + {"ETDM2_OUT", NULL, "O057"}, 969 + {"ETDM2_OUT", NULL, "O058"}, 970 + {"ETDM2_OUT", NULL, "O059"}, 971 + {"ETDM2_OUT", NULL, "O060"}, 972 + {"ETDM2_OUT", NULL, "O061"}, 973 + {"ETDM2_OUT", NULL, "O062"}, 974 + {"ETDM2_OUT", NULL, "O063"}, 975 + 976 + {"ETDM1_OUT", NULL, "O072"}, 977 + {"ETDM1_OUT", NULL, "O073"}, 978 + {"ETDM1_OUT", NULL, "O074"}, 979 + {"ETDM1_OUT", NULL, "O075"}, 980 + {"ETDM1_OUT", NULL, "O076"}, 981 + {"ETDM1_OUT", NULL, "O077"}, 982 + {"ETDM1_OUT", NULL, "O078"}, 983 + {"ETDM1_OUT", NULL, "O079"}, 984 + {"ETDM1_OUT", NULL, "O080"}, 985 + {"ETDM1_OUT", NULL, "O081"}, 986 + {"ETDM1_OUT", NULL, "O082"}, 987 + {"ETDM1_OUT", NULL, "O083"}, 988 + {"ETDM1_OUT", NULL, "O084"}, 989 + {"ETDM1_OUT", NULL, "O085"}, 990 + {"ETDM1_OUT", NULL, "O086"}, 991 + {"ETDM1_OUT", NULL, "O087"}, 992 + 993 + {"O048", "I020 Switch", "I020"}, 994 + {"O049", "I021 Switch", "I021"}, 995 + 996 + {"O048", "I022 Switch", "I022"}, 997 + {"O049", "I023 Switch", "I023"}, 998 + {"O050", "I024 Switch", "I024"}, 999 + {"O051", "I025 Switch", "I025"}, 1000 + {"O052", "I026 Switch", "I026"}, 1001 + {"O053", "I027 Switch", "I027"}, 1002 + {"O054", "I028 Switch", "I028"}, 1003 + {"O055", "I029 Switch", "I029"}, 1004 + {"O056", "I030 Switch", "I030"}, 1005 + {"O057", "I031 Switch", "I031"}, 1006 + {"O058", "I032 Switch", "I032"}, 1007 + {"O059", "I033 Switch", "I033"}, 1008 + {"O060", "I034 Switch", "I034"}, 1009 + {"O061", "I035 Switch", "I035"}, 1010 + {"O062", "I036 Switch", "I036"}, 1011 + {"O063", "I037 Switch", "I037"}, 1012 + 1013 + {"O048", "I046 Switch", "I046"}, 1014 + {"O049", "I047 Switch", "I047"}, 1015 + {"O050", "I048 Switch", "I048"}, 1016 + {"O051", "I049 Switch", "I049"}, 1017 + {"O052", "I050 Switch", "I050"}, 1018 + {"O053", "I051 Switch", "I051"}, 1019 + {"O054", "I052 Switch", "I052"}, 1020 + {"O055", "I053 Switch", "I053"}, 1021 + {"O056", "I054 Switch", "I054"}, 1022 + {"O057", "I055 Switch", "I055"}, 1023 + {"O058", "I056 Switch", "I056"}, 1024 + {"O059", "I057 Switch", "I057"}, 1025 + {"O060", "I058 Switch", "I058"}, 1026 + {"O061", "I059 Switch", "I059"}, 1027 + {"O062", "I060 Switch", "I060"}, 1028 + {"O063", "I061 Switch", "I061"}, 1029 + 1030 + {"O048", "I070 Switch", "I070"}, 1031 + {"O049", "I071 Switch", "I071"}, 1032 + 1033 + {"O072", "I020 Switch", "I020"}, 1034 + {"O073", "I021 Switch", "I021"}, 1035 + 1036 + {"O072", "I022 Switch", "I022"}, 1037 + {"O073", "I023 Switch", "I023"}, 1038 + {"O074", "I024 Switch", "I024"}, 1039 + {"O075", "I025 Switch", "I025"}, 1040 + {"O076", "I026 Switch", "I026"}, 1041 + {"O077", "I027 Switch", "I027"}, 1042 + {"O078", "I028 Switch", "I028"}, 1043 + {"O079", "I029 Switch", "I029"}, 1044 + {"O080", "I030 Switch", "I030"}, 1045 + {"O081", "I031 Switch", "I031"}, 1046 + {"O082", "I032 Switch", "I032"}, 1047 + {"O083", "I033 Switch", "I033"}, 1048 + {"O084", "I034 Switch", "I034"}, 1049 + {"O085", "I035 Switch", "I035"}, 1050 + {"O086", "I036 Switch", "I036"}, 1051 + {"O087", "I037 Switch", "I037"}, 1052 + 1053 + {"O072", "I046 Switch", "I046"}, 1054 + {"O073", "I047 Switch", "I047"}, 1055 + {"O074", "I048 Switch", "I048"}, 1056 + {"O075", "I049 Switch", "I049"}, 1057 + {"O076", "I050 Switch", "I050"}, 1058 + {"O077", "I051 Switch", "I051"}, 1059 + {"O078", "I052 Switch", "I052"}, 1060 + {"O079", "I053 Switch", "I053"}, 1061 + {"O080", "I054 Switch", "I054"}, 1062 + {"O081", "I055 Switch", "I055"}, 1063 + {"O082", "I056 Switch", "I056"}, 1064 + {"O083", "I057 Switch", "I057"}, 1065 + {"O084", "I058 Switch", "I058"}, 1066 + {"O085", "I059 Switch", "I059"}, 1067 + {"O086", "I060 Switch", "I060"}, 1068 + {"O087", "I061 Switch", "I061"}, 1069 + 1070 + {"O072", "I070 Switch", "I070"}, 1071 + {"O073", "I071 Switch", "I071"}, 1072 + 1073 + {"HDMI_CH0_MUX", "CH0", "DL10"}, 1074 + {"HDMI_CH0_MUX", "CH1", "DL10"}, 1075 + {"HDMI_CH0_MUX", "CH2", "DL10"}, 1076 + {"HDMI_CH0_MUX", "CH3", "DL10"}, 1077 + {"HDMI_CH0_MUX", "CH4", "DL10"}, 1078 + {"HDMI_CH0_MUX", "CH5", "DL10"}, 1079 + {"HDMI_CH0_MUX", "CH6", "DL10"}, 1080 + {"HDMI_CH0_MUX", "CH7", "DL10"}, 1081 + 1082 + {"HDMI_CH1_MUX", "CH0", "DL10"}, 1083 + {"HDMI_CH1_MUX", "CH1", "DL10"}, 1084 + {"HDMI_CH1_MUX", "CH2", "DL10"}, 1085 + {"HDMI_CH1_MUX", "CH3", "DL10"}, 1086 + {"HDMI_CH1_MUX", "CH4", "DL10"}, 1087 + {"HDMI_CH1_MUX", "CH5", "DL10"}, 1088 + {"HDMI_CH1_MUX", "CH6", "DL10"}, 1089 + {"HDMI_CH1_MUX", "CH7", "DL10"}, 1090 + 1091 + {"HDMI_CH2_MUX", "CH0", "DL10"}, 1092 + {"HDMI_CH2_MUX", "CH1", "DL10"}, 1093 + {"HDMI_CH2_MUX", "CH2", "DL10"}, 1094 + {"HDMI_CH2_MUX", "CH3", "DL10"}, 1095 + {"HDMI_CH2_MUX", "CH4", "DL10"}, 1096 + {"HDMI_CH2_MUX", "CH5", "DL10"}, 1097 + {"HDMI_CH2_MUX", "CH6", "DL10"}, 1098 + {"HDMI_CH2_MUX", "CH7", "DL10"}, 1099 + 1100 + {"HDMI_CH3_MUX", "CH0", "DL10"}, 1101 + {"HDMI_CH3_MUX", "CH1", "DL10"}, 1102 + {"HDMI_CH3_MUX", "CH2", "DL10"}, 1103 + {"HDMI_CH3_MUX", "CH3", "DL10"}, 1104 + {"HDMI_CH3_MUX", "CH4", "DL10"}, 1105 + {"HDMI_CH3_MUX", "CH5", "DL10"}, 1106 + {"HDMI_CH3_MUX", "CH6", "DL10"}, 1107 + {"HDMI_CH3_MUX", "CH7", "DL10"}, 1108 + 1109 + {"HDMI_CH4_MUX", "CH0", "DL10"}, 1110 + {"HDMI_CH4_MUX", "CH1", "DL10"}, 1111 + {"HDMI_CH4_MUX", "CH2", "DL10"}, 1112 + {"HDMI_CH4_MUX", "CH3", "DL10"}, 1113 + {"HDMI_CH4_MUX", "CH4", "DL10"}, 1114 + {"HDMI_CH4_MUX", "CH5", "DL10"}, 1115 + {"HDMI_CH4_MUX", "CH6", "DL10"}, 1116 + {"HDMI_CH4_MUX", "CH7", "DL10"}, 1117 + 1118 + {"HDMI_CH5_MUX", "CH0", "DL10"}, 1119 + {"HDMI_CH5_MUX", "CH1", "DL10"}, 1120 + {"HDMI_CH5_MUX", "CH2", "DL10"}, 1121 + {"HDMI_CH5_MUX", "CH3", "DL10"}, 1122 + {"HDMI_CH5_MUX", "CH4", "DL10"}, 1123 + {"HDMI_CH5_MUX", "CH5", "DL10"}, 1124 + {"HDMI_CH5_MUX", "CH6", "DL10"}, 1125 + {"HDMI_CH5_MUX", "CH7", "DL10"}, 1126 + 1127 + {"HDMI_CH6_MUX", "CH0", "DL10"}, 1128 + {"HDMI_CH6_MUX", "CH1", "DL10"}, 1129 + {"HDMI_CH6_MUX", "CH2", "DL10"}, 1130 + {"HDMI_CH6_MUX", "CH3", "DL10"}, 1131 + {"HDMI_CH6_MUX", "CH4", "DL10"}, 1132 + {"HDMI_CH6_MUX", "CH5", "DL10"}, 1133 + {"HDMI_CH6_MUX", "CH6", "DL10"}, 1134 + {"HDMI_CH6_MUX", "CH7", "DL10"}, 1135 + 1136 + {"HDMI_CH7_MUX", "CH0", "DL10"}, 1137 + {"HDMI_CH7_MUX", "CH1", "DL10"}, 1138 + {"HDMI_CH7_MUX", "CH2", "DL10"}, 1139 + {"HDMI_CH7_MUX", "CH3", "DL10"}, 1140 + {"HDMI_CH7_MUX", "CH4", "DL10"}, 1141 + {"HDMI_CH7_MUX", "CH5", "DL10"}, 1142 + {"HDMI_CH7_MUX", "CH6", "DL10"}, 1143 + {"HDMI_CH7_MUX", "CH7", "DL10"}, 1144 + 1145 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1146 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1147 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1148 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1149 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1150 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1151 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1152 + {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1153 + 1154 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1155 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1156 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1157 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1158 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1159 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1160 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1161 + {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1162 + 1163 + {"ETDM3_OUT", NULL, "HDMI_OUT_MUX"}, 1164 + {"DPTX", NULL, "DPTX_OUT_MUX"}, 1165 + 1166 + {"ETDM_OUTPUT", NULL, "DPTX"}, 1167 + {"ETDM_OUTPUT", NULL, "ETDM1_OUT"}, 1168 + {"ETDM_OUTPUT", NULL, "ETDM2_OUT"}, 1169 + {"ETDM_OUTPUT", NULL, "ETDM3_OUT"}, 1170 + {"ETDM1_IN", NULL, "ETDM_INPUT"}, 1171 + {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1172 + }; 1173 + 1174 + static int mt8188_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1175 + { 1176 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1177 + struct mtk_dai_etdm_priv *etdm_data; 1178 + struct etdm_con_reg etdm_reg; 1179 + unsigned long flags; 1180 + int ret = 0; 1181 + 1182 + if (!is_valid_etdm_dai(dai_id)) 1183 + return -EINVAL; 1184 + etdm_data = afe_priv->dai_priv[dai_id]; 1185 + 1186 + dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1187 + spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1188 + etdm_data->en_ref_cnt++; 1189 + if (etdm_data->en_ref_cnt == 1) { 1190 + ret = get_etdm_reg(dai_id, &etdm_reg); 1191 + if (ret < 0) 1192 + goto out; 1193 + 1194 + regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_EN); 1195 + } 1196 + 1197 + out: 1198 + spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1199 + return ret; 1200 + } 1201 + 1202 + static int mt8188_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1203 + { 1204 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1205 + struct mtk_dai_etdm_priv *etdm_data; 1206 + struct etdm_con_reg etdm_reg; 1207 + unsigned long flags; 1208 + int ret = 0; 1209 + 1210 + if (!is_valid_etdm_dai(dai_id)) 1211 + return -EINVAL; 1212 + etdm_data = afe_priv->dai_priv[dai_id]; 1213 + 1214 + dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1215 + spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1216 + if (etdm_data->en_ref_cnt > 0) { 1217 + etdm_data->en_ref_cnt--; 1218 + if (etdm_data->en_ref_cnt == 0) { 1219 + ret = get_etdm_reg(dai_id, &etdm_reg); 1220 + if (ret < 0) 1221 + goto out; 1222 + regmap_clear_bits(afe->regmap, etdm_reg.con0, 1223 + ETDM_CON0_EN); 1224 + } 1225 + } 1226 + 1227 + out: 1228 + spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1229 + return ret; 1230 + } 1231 + 1232 + static int etdm_cowork_slv_sel(int id, int slave_mode) 1233 + { 1234 + if (slave_mode) { 1235 + switch (id) { 1236 + case MT8188_AFE_IO_ETDM1_IN: 1237 + return COWORK_ETDM_IN1_S; 1238 + case MT8188_AFE_IO_ETDM2_IN: 1239 + return COWORK_ETDM_IN2_S; 1240 + case MT8188_AFE_IO_ETDM1_OUT: 1241 + return COWORK_ETDM_OUT1_S; 1242 + case MT8188_AFE_IO_ETDM2_OUT: 1243 + return COWORK_ETDM_OUT2_S; 1244 + case MT8188_AFE_IO_ETDM3_OUT: 1245 + return COWORK_ETDM_OUT3_S; 1246 + default: 1247 + return -EINVAL; 1248 + } 1249 + } else { 1250 + switch (id) { 1251 + case MT8188_AFE_IO_ETDM1_IN: 1252 + return COWORK_ETDM_IN1_M; 1253 + case MT8188_AFE_IO_ETDM2_IN: 1254 + return COWORK_ETDM_IN2_M; 1255 + case MT8188_AFE_IO_ETDM1_OUT: 1256 + return COWORK_ETDM_OUT1_M; 1257 + case MT8188_AFE_IO_ETDM2_OUT: 1258 + return COWORK_ETDM_OUT2_M; 1259 + case MT8188_AFE_IO_ETDM3_OUT: 1260 + return COWORK_ETDM_OUT3_M; 1261 + default: 1262 + return -EINVAL; 1263 + } 1264 + } 1265 + } 1266 + 1267 + static int etdm_cowork_sync_sel(int id) 1268 + { 1269 + switch (id) { 1270 + case MT8188_AFE_IO_ETDM1_IN: 1271 + return ETDM_SYNC_FROM_IN1; 1272 + case MT8188_AFE_IO_ETDM2_IN: 1273 + return ETDM_SYNC_FROM_IN2; 1274 + case MT8188_AFE_IO_ETDM1_OUT: 1275 + return ETDM_SYNC_FROM_OUT1; 1276 + case MT8188_AFE_IO_ETDM2_OUT: 1277 + return ETDM_SYNC_FROM_OUT2; 1278 + case MT8188_AFE_IO_ETDM3_OUT: 1279 + return ETDM_SYNC_FROM_OUT3; 1280 + default: 1281 + return -EINVAL; 1282 + } 1283 + } 1284 + 1285 + static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id) 1286 + { 1287 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1288 + struct mtk_dai_etdm_priv *etdm_data; 1289 + unsigned int reg = 0; 1290 + unsigned int mask; 1291 + unsigned int val; 1292 + int cowork_source_sel; 1293 + 1294 + if (!is_valid_etdm_dai(dai_id)) 1295 + return -EINVAL; 1296 + etdm_data = afe_priv->dai_priv[dai_id]; 1297 + 1298 + cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1299 + true); 1300 + if (cowork_source_sel < 0) 1301 + return cowork_source_sel; 1302 + 1303 + switch (dai_id) { 1304 + case MT8188_AFE_IO_ETDM1_IN: 1305 + reg = ETDM_COWORK_CON1; 1306 + mask = ETDM_IN1_SLAVE_SEL_MASK; 1307 + val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel); 1308 + break; 1309 + case MT8188_AFE_IO_ETDM2_IN: 1310 + reg = ETDM_COWORK_CON2; 1311 + mask = ETDM_IN2_SLAVE_SEL_MASK; 1312 + val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel); 1313 + break; 1314 + case MT8188_AFE_IO_ETDM1_OUT: 1315 + reg = ETDM_COWORK_CON0; 1316 + mask = ETDM_OUT1_SLAVE_SEL_MASK; 1317 + val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel); 1318 + break; 1319 + case MT8188_AFE_IO_ETDM2_OUT: 1320 + reg = ETDM_COWORK_CON2; 1321 + mask = ETDM_OUT2_SLAVE_SEL_MASK; 1322 + val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel); 1323 + break; 1324 + case MT8188_AFE_IO_ETDM3_OUT: 1325 + reg = ETDM_COWORK_CON2; 1326 + mask = ETDM_OUT3_SLAVE_SEL_MASK; 1327 + val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel); 1328 + break; 1329 + default: 1330 + return 0; 1331 + } 1332 + 1333 + regmap_update_bits(afe->regmap, reg, mask, val); 1334 + 1335 + return 0; 1336 + } 1337 + 1338 + static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id) 1339 + { 1340 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1341 + struct mtk_dai_etdm_priv *etdm_data; 1342 + struct etdm_con_reg etdm_reg; 1343 + unsigned int reg = 0; 1344 + unsigned int mask; 1345 + unsigned int val; 1346 + int cowork_source_sel; 1347 + int ret; 1348 + 1349 + if (!is_valid_etdm_dai(dai_id)) 1350 + return -EINVAL; 1351 + etdm_data = afe_priv->dai_priv[dai_id]; 1352 + 1353 + cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id); 1354 + if (cowork_source_sel < 0) 1355 + return cowork_source_sel; 1356 + 1357 + switch (dai_id) { 1358 + case MT8188_AFE_IO_ETDM1_IN: 1359 + reg = ETDM_COWORK_CON1; 1360 + mask = ETDM_IN1_SYNC_SEL_MASK; 1361 + val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel); 1362 + break; 1363 + case MT8188_AFE_IO_ETDM2_IN: 1364 + reg = ETDM_COWORK_CON2; 1365 + mask = ETDM_IN2_SYNC_SEL_MASK; 1366 + val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel); 1367 + break; 1368 + case MT8188_AFE_IO_ETDM1_OUT: 1369 + reg = ETDM_COWORK_CON0; 1370 + mask = ETDM_OUT1_SYNC_SEL_MASK; 1371 + val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel); 1372 + break; 1373 + case MT8188_AFE_IO_ETDM2_OUT: 1374 + reg = ETDM_COWORK_CON2; 1375 + mask = ETDM_OUT2_SYNC_SEL_MASK; 1376 + val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel); 1377 + break; 1378 + case MT8188_AFE_IO_ETDM3_OUT: 1379 + reg = ETDM_COWORK_CON2; 1380 + mask = ETDM_OUT3_SYNC_SEL_MASK; 1381 + val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel); 1382 + break; 1383 + default: 1384 + return 0; 1385 + } 1386 + 1387 + ret = get_etdm_reg(dai_id, &etdm_reg); 1388 + if (ret < 0) 1389 + return ret; 1390 + 1391 + regmap_update_bits(afe->regmap, reg, mask, val); 1392 + 1393 + regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE); 1394 + 1395 + return 0; 1396 + } 1397 + 1398 + static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1399 + { 1400 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1401 + struct mtk_dai_etdm_priv *etdm_data; 1402 + 1403 + if (!is_valid_etdm_dai(dai_id)) 1404 + return -EINVAL; 1405 + etdm_data = afe_priv->dai_priv[dai_id]; 1406 + 1407 + if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1408 + return 0; 1409 + 1410 + if (etdm_data->slave_mode) 1411 + mt8188_etdm_sync_mode_slv(afe, dai_id); 1412 + else 1413 + mt8188_etdm_sync_mode_mst(afe, dai_id); 1414 + 1415 + return 0; 1416 + } 1417 + 1418 + /* dai ops */ 1419 + static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1420 + struct snd_soc_dai *dai) 1421 + { 1422 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1423 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1424 + struct mtk_dai_etdm_priv *mst_etdm_data; 1425 + int mst_dai_id; 1426 + int slv_dai_id; 1427 + int cg_id; 1428 + int i; 1429 + 1430 + if (is_cowork_mode(dai)) { 1431 + mst_dai_id = get_etdm_cowork_master_id(dai); 1432 + if (!is_valid_etdm_dai(mst_dai_id)) 1433 + return -EINVAL; 1434 + mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1435 + 1436 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1437 + if (cg_id >= 0) 1438 + mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1439 + 1440 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1441 + 1442 + for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1443 + slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1444 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1445 + if (cg_id >= 0) 1446 + mt8188_afe_enable_clk(afe, 1447 + afe_priv->clk[cg_id]); 1448 + } 1449 + } else { 1450 + mtk_dai_etdm_enable_mclk(afe, dai->id); 1451 + 1452 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1453 + if (cg_id >= 0) 1454 + mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1455 + } 1456 + 1457 + return 0; 1458 + } 1459 + 1460 + static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1461 + struct snd_soc_dai *dai) 1462 + { 1463 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1464 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1465 + struct mtk_dai_etdm_priv *mst_etdm_data; 1466 + int mst_dai_id; 1467 + int slv_dai_id; 1468 + int cg_id; 1469 + int ret; 1470 + int i; 1471 + 1472 + if (!is_valid_etdm_dai(dai->id)) 1473 + return; 1474 + mst_etdm_data = afe_priv->dai_priv[dai->id]; 1475 + 1476 + dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1477 + mst_etdm_data->is_prepared); 1478 + 1479 + if (mst_etdm_data->is_prepared) { 1480 + mst_etdm_data->is_prepared = false; 1481 + 1482 + if (is_cowork_mode(dai)) { 1483 + mst_dai_id = get_etdm_cowork_master_id(dai); 1484 + if (!is_valid_etdm_dai(mst_dai_id)) 1485 + return; 1486 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1487 + 1488 + ret = mt8188_afe_disable_etdm(afe, mst_dai_id); 1489 + if (ret) 1490 + dev_dbg(afe->dev, "%s disable %d failed\n", 1491 + __func__, mst_dai_id); 1492 + 1493 + for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1494 + slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1495 + ret = mt8188_afe_disable_etdm(afe, slv_dai_id); 1496 + if (ret) 1497 + dev_dbg(afe->dev, "%s disable %d failed\n", 1498 + __func__, slv_dai_id); 1499 + } 1500 + } else { 1501 + ret = mt8188_afe_disable_etdm(afe, dai->id); 1502 + if (ret) 1503 + dev_dbg(afe->dev, "%s disable %d failed\n", 1504 + __func__, dai->id); 1505 + } 1506 + } 1507 + 1508 + if (is_cowork_mode(dai)) { 1509 + mst_dai_id = get_etdm_cowork_master_id(dai); 1510 + if (!is_valid_etdm_dai(mst_dai_id)) 1511 + return; 1512 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1513 + if (cg_id >= 0) 1514 + mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1515 + 1516 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1517 + for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1518 + slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1519 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1520 + if (cg_id >= 0) 1521 + mt8188_afe_disable_clk(afe, 1522 + afe_priv->clk[cg_id]); 1523 + } 1524 + mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1525 + } else { 1526 + cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1527 + if (cg_id >= 0) 1528 + mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1529 + 1530 + mtk_dai_etdm_disable_mclk(afe, dai->id); 1531 + } 1532 + } 1533 + 1534 + static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1535 + int dai_id, unsigned int rate) 1536 + { 1537 + unsigned int mode = 0; 1538 + unsigned int reg = 0; 1539 + unsigned int val = 0; 1540 + unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1541 + 1542 + if (rate != 0) 1543 + mode = mt8188_afe_fs_timing(rate); 1544 + 1545 + switch (dai_id) { 1546 + case MT8188_AFE_IO_ETDM1_IN: 1547 + reg = ETDM_IN1_AFIFO_CON; 1548 + if (rate == 0) 1549 + mode = MT8188_ETDM_IN1_1X_EN; 1550 + break; 1551 + case MT8188_AFE_IO_ETDM2_IN: 1552 + reg = ETDM_IN2_AFIFO_CON; 1553 + if (rate == 0) 1554 + mode = MT8188_ETDM_IN2_1X_EN; 1555 + break; 1556 + default: 1557 + return -EINVAL; 1558 + } 1559 + 1560 + val = (mode | ETDM_IN_USE_AFIFO); 1561 + 1562 + regmap_update_bits(afe->regmap, reg, mask, val); 1563 + return 0; 1564 + } 1565 + 1566 + static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1567 + unsigned int rate, 1568 + unsigned int channels, 1569 + int dai_id) 1570 + { 1571 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1572 + struct mtk_dai_etdm_priv *etdm_data; 1573 + struct etdm_con_reg etdm_reg; 1574 + bool slave_mode; 1575 + unsigned int data_mode; 1576 + unsigned int lrck_width; 1577 + unsigned int val = 0; 1578 + unsigned int mask = 0; 1579 + int ret; 1580 + int i; 1581 + 1582 + if (!is_valid_etdm_dai(dai_id)) 1583 + return -EINVAL; 1584 + etdm_data = afe_priv->dai_priv[dai_id]; 1585 + slave_mode = etdm_data->slave_mode; 1586 + data_mode = etdm_data->data_mode; 1587 + lrck_width = etdm_data->lrck_width; 1588 + 1589 + dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1590 + __func__, rate, channels, dai_id); 1591 + 1592 + ret = get_etdm_reg(dai_id, &etdm_reg); 1593 + if (ret < 0) 1594 + return ret; 1595 + 1596 + /* afifo */ 1597 + if (slave_mode) 1598 + mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1599 + else 1600 + mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1601 + 1602 + /* con1 */ 1603 + if (lrck_width > 0) { 1604 + mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1605 + ETDM_IN_CON1_LRCK_WIDTH_MASK); 1606 + val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1607 + } 1608 + regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1609 + 1610 + mask = 0; 1611 + val = 0; 1612 + 1613 + /* con2 */ 1614 + if (!slave_mode) { 1615 + mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1616 + if (rate == 352800 || rate == 384000) 1617 + val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4); 1618 + else 1619 + val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3); 1620 + } 1621 + mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1622 + ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1623 + if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1624 + val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1625 + FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1); 1626 + } 1627 + regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1628 + 1629 + mask = 0; 1630 + val = 0; 1631 + 1632 + /* con3 */ 1633 + mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1634 + for (i = 0; i < channels; i += 2) { 1635 + if (etdm_data->in_disable_ch[i] && 1636 + etdm_data->in_disable_ch[i + 1]) 1637 + val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1638 + } 1639 + if (!slave_mode) { 1640 + mask |= ETDM_IN_CON3_FS_MASK; 1641 + val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate)); 1642 + } 1643 + regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1644 + 1645 + mask = 0; 1646 + val = 0; 1647 + 1648 + /* con4 */ 1649 + mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1650 + ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1651 + if (slave_mode) { 1652 + if (etdm_data->lrck_inv) 1653 + val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1654 + if (etdm_data->bck_inv) 1655 + val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1656 + } else { 1657 + if (etdm_data->lrck_inv) 1658 + val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1659 + if (etdm_data->bck_inv) 1660 + val |= ETDM_IN_CON4_MASTER_BCK_INV; 1661 + } 1662 + regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1663 + 1664 + mask = 0; 1665 + val = 0; 1666 + 1667 + /* con5 */ 1668 + mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1669 + mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1670 + for (i = 0; i < channels; i += 2) { 1671 + if (etdm_data->in_disable_ch[i] && 1672 + !etdm_data->in_disable_ch[i + 1]) { 1673 + val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1674 + val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1675 + } else if (!etdm_data->in_disable_ch[i] && 1676 + etdm_data->in_disable_ch[i + 1]) { 1677 + val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1678 + } 1679 + } 1680 + regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1681 + return 0; 1682 + } 1683 + 1684 + static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1685 + unsigned int rate, 1686 + unsigned int channels, 1687 + int dai_id) 1688 + { 1689 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1690 + struct mtk_dai_etdm_priv *etdm_data; 1691 + struct etdm_con_reg etdm_reg; 1692 + bool slave_mode; 1693 + unsigned int lrck_width; 1694 + unsigned int val = 0; 1695 + unsigned int mask = 0; 1696 + int fs = 0; 1697 + int ret; 1698 + 1699 + if (!is_valid_etdm_dai(dai_id)) 1700 + return -EINVAL; 1701 + etdm_data = afe_priv->dai_priv[dai_id]; 1702 + slave_mode = etdm_data->slave_mode; 1703 + lrck_width = etdm_data->lrck_width; 1704 + 1705 + dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1706 + __func__, rate, channels, dai_id); 1707 + 1708 + ret = get_etdm_reg(dai_id, &etdm_reg); 1709 + if (ret < 0) 1710 + return ret; 1711 + 1712 + /* con0 */ 1713 + mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1714 + val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK, 1715 + ETDM_RELATCH_TIMING_A1A2SYS); 1716 + regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1717 + 1718 + mask = 0; 1719 + val = 0; 1720 + 1721 + /* con1 */ 1722 + if (lrck_width > 0) { 1723 + mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1724 + ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1725 + val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1726 + } 1727 + regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1728 + 1729 + mask = 0; 1730 + val = 0; 1731 + 1732 + if (!slave_mode) { 1733 + /* con4 */ 1734 + mask |= ETDM_OUT_CON4_FS_MASK; 1735 + val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate)); 1736 + } 1737 + 1738 + mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1739 + if (dai_id == MT8188_AFE_IO_ETDM1_OUT) 1740 + fs = MT8188_ETDM_OUT1_1X_EN; 1741 + else if (dai_id == MT8188_AFE_IO_ETDM2_OUT) 1742 + fs = MT8188_ETDM_OUT2_1X_EN; 1743 + 1744 + val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs); 1745 + 1746 + regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1747 + 1748 + mask = 0; 1749 + val = 0; 1750 + 1751 + /* con5 */ 1752 + mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1753 + ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1754 + if (slave_mode) { 1755 + if (etdm_data->lrck_inv) 1756 + val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1757 + if (etdm_data->bck_inv) 1758 + val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1759 + } else { 1760 + if (etdm_data->lrck_inv) 1761 + val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1762 + if (etdm_data->bck_inv) 1763 + val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1764 + } 1765 + regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1766 + 1767 + return 0; 1768 + } 1769 + 1770 + static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1771 + { 1772 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1773 + struct mtk_dai_etdm_priv *etdm_data; 1774 + struct etdm_con_reg etdm_reg; 1775 + int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1776 + int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1777 + int apll_clk_id; 1778 + int apll; 1779 + int ret; 1780 + 1781 + if (clk_id < 0 || clkdiv_id < 0) 1782 + return -EINVAL; 1783 + 1784 + if (!is_valid_etdm_dai(dai_id)) 1785 + return -EINVAL; 1786 + etdm_data = afe_priv->dai_priv[dai_id]; 1787 + 1788 + ret = get_etdm_reg(dai_id, &etdm_reg); 1789 + if (ret < 0) 1790 + return ret; 1791 + 1792 + if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1793 + regmap_set_bits(afe->regmap, etdm_reg.con1, 1794 + ETDM_CON1_MCLK_OUTPUT); 1795 + else 1796 + regmap_clear_bits(afe->regmap, etdm_reg.con1, 1797 + ETDM_CON1_MCLK_OUTPUT); 1798 + 1799 + if (etdm_data->mclk_freq) { 1800 + apll = etdm_data->mclk_apll; 1801 + apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 1802 + if (apll_clk_id < 0) 1803 + return apll_clk_id; 1804 + 1805 + /* select apll */ 1806 + ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1807 + afe_priv->clk[apll_clk_id]); 1808 + if (ret) 1809 + return ret; 1810 + 1811 + /* set rate */ 1812 + ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1813 + etdm_data->mclk_freq); 1814 + if (ret) 1815 + return ret; 1816 + } else { 1817 + if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1818 + dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1819 + } 1820 + 1821 + return 0; 1822 + } 1823 + 1824 + static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1825 + unsigned int rate, 1826 + unsigned int channels, 1827 + unsigned int bit_width, 1828 + int dai_id) 1829 + { 1830 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1831 + struct mtk_dai_etdm_priv *etdm_data; 1832 + struct etdm_con_reg etdm_reg; 1833 + bool slave_mode; 1834 + unsigned int etdm_channels; 1835 + unsigned int val = 0; 1836 + unsigned int mask = 0; 1837 + unsigned int bck; 1838 + unsigned int wlen = get_etdm_wlen(bit_width); 1839 + int ret; 1840 + 1841 + if (!is_valid_etdm_dai(dai_id)) 1842 + return -EINVAL; 1843 + etdm_data = afe_priv->dai_priv[dai_id]; 1844 + slave_mode = etdm_data->slave_mode; 1845 + 1846 + ret = get_etdm_reg(dai_id, &etdm_reg); 1847 + if (ret < 0) 1848 + return ret; 1849 + 1850 + dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1851 + __func__, etdm_data->format, etdm_data->data_mode, 1852 + etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1853 + etdm_data->clock_mode, etdm_data->slave_mode); 1854 + dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 1855 + __func__, rate, channels, bit_width, dai_id); 1856 + 1857 + etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1858 + get_etdm_ch_fixup(channels) : 2; 1859 + 1860 + bck = rate * etdm_channels * wlen; 1861 + if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) { 1862 + dev_err(afe->dev, "%s bck rate %u not support\n", 1863 + __func__, bck); 1864 + return -EINVAL; 1865 + } 1866 + 1867 + /* con0 */ 1868 + mask |= ETDM_CON0_BIT_LEN_MASK; 1869 + val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1); 1870 + mask |= ETDM_CON0_WORD_LEN_MASK; 1871 + val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1); 1872 + mask |= ETDM_CON0_FORMAT_MASK; 1873 + val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format); 1874 + mask |= ETDM_CON0_CH_NUM_MASK; 1875 + val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1); 1876 + 1877 + mask |= ETDM_CON0_SLAVE_MODE; 1878 + if (slave_mode) { 1879 + if (dai_id == MT8188_AFE_IO_ETDM1_OUT) { 1880 + dev_err(afe->dev, "%s id %d only support master mode\n", 1881 + __func__, dai_id); 1882 + return -EINVAL; 1883 + } 1884 + val |= ETDM_CON0_SLAVE_MODE; 1885 + } 1886 + regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1887 + 1888 + if (get_etdm_dir(dai_id) == ETDM_IN) 1889 + mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 1890 + else 1891 + mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 1892 + 1893 + return 0; 1894 + } 1895 + 1896 + static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 1897 + struct snd_pcm_hw_params *params, 1898 + struct snd_soc_dai *dai) 1899 + { 1900 + unsigned int rate = params_rate(params); 1901 + unsigned int bit_width = params_width(params); 1902 + unsigned int channels = params_channels(params); 1903 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1904 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1905 + struct mtk_dai_etdm_priv *mst_etdm_data; 1906 + int mst_dai_id; 1907 + int slv_dai_id; 1908 + int ret; 1909 + int i; 1910 + 1911 + dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 1912 + __func__, snd_pcm_stream_str(substream), 1913 + params_period_size(params), params_periods(params)); 1914 + 1915 + if (is_cowork_mode(dai)) { 1916 + mst_dai_id = get_etdm_cowork_master_id(dai); 1917 + if (!is_valid_etdm_dai(mst_dai_id)) 1918 + return -EINVAL; 1919 + 1920 + ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 1921 + if (ret) 1922 + return ret; 1923 + 1924 + ret = mtk_dai_etdm_configure(afe, rate, channels, 1925 + bit_width, mst_dai_id); 1926 + if (ret) 1927 + return ret; 1928 + 1929 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1930 + for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1931 + slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1932 + ret = mtk_dai_etdm_configure(afe, rate, channels, 1933 + bit_width, slv_dai_id); 1934 + if (ret) 1935 + return ret; 1936 + 1937 + ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id); 1938 + if (ret) 1939 + return ret; 1940 + } 1941 + } else { 1942 + ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 1943 + if (ret) 1944 + return ret; 1945 + 1946 + ret = mtk_dai_etdm_configure(afe, rate, channels, 1947 + bit_width, dai->id); 1948 + if (ret) 1949 + return ret; 1950 + } 1951 + 1952 + return 0; 1953 + } 1954 + 1955 + static int mtk_dai_etdm_prepare(struct snd_pcm_substream *substream, 1956 + struct snd_soc_dai *dai) 1957 + { 1958 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1959 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1960 + struct mtk_dai_etdm_priv *mst_etdm_data; 1961 + int mst_dai_id; 1962 + int slv_dai_id; 1963 + int ret; 1964 + int i; 1965 + 1966 + if (!is_valid_etdm_dai(dai->id)) 1967 + return -EINVAL; 1968 + mst_etdm_data = afe_priv->dai_priv[dai->id]; 1969 + 1970 + dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1971 + mst_etdm_data->is_prepared); 1972 + 1973 + if (mst_etdm_data->is_prepared) 1974 + return 0; 1975 + 1976 + mst_etdm_data->is_prepared = true; 1977 + 1978 + if (is_cowork_mode(dai)) { 1979 + mst_dai_id = get_etdm_cowork_master_id(dai); 1980 + if (!is_valid_etdm_dai(mst_dai_id)) 1981 + return -EINVAL; 1982 + mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1983 + 1984 + for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1985 + slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1986 + ret = mt8188_afe_enable_etdm(afe, slv_dai_id); 1987 + if (ret) { 1988 + dev_dbg(afe->dev, "%s enable %d failed\n", 1989 + __func__, slv_dai_id); 1990 + 1991 + return ret; 1992 + } 1993 + } 1994 + 1995 + ret = mt8188_afe_enable_etdm(afe, mst_dai_id); 1996 + if (ret) { 1997 + dev_dbg(afe->dev, "%s enable %d failed\n", 1998 + __func__, mst_dai_id); 1999 + 2000 + return ret; 2001 + } 2002 + } else { 2003 + ret = mt8188_afe_enable_etdm(afe, dai->id); 2004 + if (ret) { 2005 + dev_dbg(afe->dev, "%s enable %d failed\n", 2006 + __func__, dai->id); 2007 + 2008 + return ret; 2009 + } 2010 + } 2011 + 2012 + return 0; 2013 + } 2014 + 2015 + static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2016 + { 2017 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2018 + struct mtk_dai_etdm_priv *etdm_data; 2019 + int apll_rate; 2020 + int apll; 2021 + 2022 + if (!is_valid_etdm_dai(dai_id)) 2023 + return -EINVAL; 2024 + etdm_data = afe_priv->dai_priv[dai_id]; 2025 + 2026 + if (freq == 0) { 2027 + etdm_data->mclk_freq = freq; 2028 + return 0; 2029 + } 2030 + 2031 + if (etdm_data->mclk_fixed_apll == 0) 2032 + apll = mt8188_afe_get_default_mclk_source_by_rate(freq); 2033 + else 2034 + apll = etdm_data->mclk_apll; 2035 + 2036 + apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); 2037 + 2038 + if (freq > apll_rate) { 2039 + dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2040 + return -EINVAL; 2041 + } 2042 + 2043 + if (apll_rate % freq != 0) { 2044 + dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2045 + return -EINVAL; 2046 + } 2047 + 2048 + if (etdm_data->mclk_fixed_apll == 0) 2049 + etdm_data->mclk_apll = apll; 2050 + etdm_data->mclk_freq = freq; 2051 + 2052 + return 0; 2053 + } 2054 + 2055 + static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2056 + int clk_id, unsigned int freq, int dir) 2057 + { 2058 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2059 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2060 + struct mtk_dai_etdm_priv *etdm_data; 2061 + int dai_id; 2062 + 2063 + dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2064 + __func__, dai->id, freq, dir); 2065 + if (is_cowork_mode(dai)) 2066 + dai_id = get_etdm_cowork_master_id(dai); 2067 + else 2068 + dai_id = dai->id; 2069 + 2070 + if (!is_valid_etdm_dai(dai_id)) 2071 + return -EINVAL; 2072 + etdm_data = afe_priv->dai_priv[dai_id]; 2073 + etdm_data->mclk_dir = dir; 2074 + return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2075 + } 2076 + 2077 + static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2078 + unsigned int tx_mask, unsigned int rx_mask, 2079 + int slots, int slot_width) 2080 + { 2081 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2082 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2083 + struct mtk_dai_etdm_priv *etdm_data; 2084 + 2085 + if (!is_valid_etdm_dai(dai->id)) 2086 + return -EINVAL; 2087 + etdm_data = afe_priv->dai_priv[dai->id]; 2088 + 2089 + dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2090 + __func__, dai->id, slot_width); 2091 + 2092 + etdm_data->slots = slots; 2093 + etdm_data->lrck_width = slot_width; 2094 + return 0; 2095 + } 2096 + 2097 + static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2098 + { 2099 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2100 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2101 + struct mtk_dai_etdm_priv *etdm_data; 2102 + 2103 + if (!is_valid_etdm_dai(dai->id)) 2104 + return -EINVAL; 2105 + etdm_data = afe_priv->dai_priv[dai->id]; 2106 + 2107 + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2108 + case SND_SOC_DAIFMT_I2S: 2109 + etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2110 + break; 2111 + case SND_SOC_DAIFMT_LEFT_J: 2112 + etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2113 + break; 2114 + case SND_SOC_DAIFMT_RIGHT_J: 2115 + etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2116 + break; 2117 + case SND_SOC_DAIFMT_DSP_A: 2118 + etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2119 + break; 2120 + case SND_SOC_DAIFMT_DSP_B: 2121 + etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2122 + break; 2123 + default: 2124 + return -EINVAL; 2125 + } 2126 + 2127 + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2128 + case SND_SOC_DAIFMT_NB_NF: 2129 + etdm_data->bck_inv = false; 2130 + etdm_data->lrck_inv = false; 2131 + break; 2132 + case SND_SOC_DAIFMT_NB_IF: 2133 + etdm_data->bck_inv = false; 2134 + etdm_data->lrck_inv = true; 2135 + break; 2136 + case SND_SOC_DAIFMT_IB_NF: 2137 + etdm_data->bck_inv = true; 2138 + etdm_data->lrck_inv = false; 2139 + break; 2140 + case SND_SOC_DAIFMT_IB_IF: 2141 + etdm_data->bck_inv = true; 2142 + etdm_data->lrck_inv = true; 2143 + break; 2144 + default: 2145 + return -EINVAL; 2146 + } 2147 + 2148 + switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2149 + case SND_SOC_DAIFMT_BC_FC: 2150 + etdm_data->slave_mode = true; 2151 + break; 2152 + case SND_SOC_DAIFMT_BP_FP: 2153 + etdm_data->slave_mode = false; 2154 + break; 2155 + default: 2156 + return -EINVAL; 2157 + } 2158 + 2159 + return 0; 2160 + } 2161 + 2162 + static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2163 + struct snd_soc_dai *dai) 2164 + { 2165 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2166 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2167 + int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2168 + 2169 + if (cg_id >= 0) 2170 + mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2171 + 2172 + mtk_dai_etdm_enable_mclk(afe, dai->id); 2173 + 2174 + return 0; 2175 + } 2176 + 2177 + static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2178 + struct snd_soc_dai *dai) 2179 + { 2180 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2181 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2182 + int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2183 + struct mtk_dai_etdm_priv *etdm_data; 2184 + int ret; 2185 + 2186 + if (!is_valid_etdm_dai(dai->id)) 2187 + return; 2188 + etdm_data = afe_priv->dai_priv[dai->id]; 2189 + 2190 + if (etdm_data->is_prepared) { 2191 + etdm_data->is_prepared = false; 2192 + /* disable etdm_out3 */ 2193 + ret = mt8188_afe_disable_etdm(afe, dai->id); 2194 + if (ret) 2195 + dev_dbg(afe->dev, "%s disable failed\n", __func__); 2196 + 2197 + /* disable dptx interface */ 2198 + if (dai->id == MT8188_AFE_IO_DPTX) 2199 + regmap_clear_bits(afe->regmap, AFE_DPTX_CON, 2200 + AFE_DPTX_CON_ON); 2201 + } 2202 + 2203 + mtk_dai_etdm_disable_mclk(afe, dai->id); 2204 + 2205 + if (cg_id >= 0) 2206 + mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2207 + } 2208 + 2209 + static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2210 + { 2211 + switch (channel) { 2212 + case 1 ... 2: 2213 + return AFE_DPTX_CON_CH_EN_2CH; 2214 + case 3 ... 4: 2215 + return AFE_DPTX_CON_CH_EN_4CH; 2216 + case 5 ... 6: 2217 + return AFE_DPTX_CON_CH_EN_6CH; 2218 + case 7 ... 8: 2219 + return AFE_DPTX_CON_CH_EN_8CH; 2220 + default: 2221 + return AFE_DPTX_CON_CH_EN_2CH; 2222 + } 2223 + } 2224 + 2225 + static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2226 + { 2227 + return (ch > 2) ? 2228 + AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2229 + } 2230 + 2231 + static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2232 + { 2233 + return snd_pcm_format_physical_width(format) <= 16 ? 2234 + AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2235 + } 2236 + 2237 + static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2238 + struct snd_pcm_hw_params *params, 2239 + struct snd_soc_dai *dai) 2240 + { 2241 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2242 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2243 + struct mtk_dai_etdm_priv *etdm_data; 2244 + unsigned int rate = params_rate(params); 2245 + unsigned int channels = params_channels(params); 2246 + snd_pcm_format_t format = params_format(params); 2247 + int width = snd_pcm_format_physical_width(format); 2248 + int ret; 2249 + 2250 + if (!is_valid_etdm_dai(dai->id)) 2251 + return -EINVAL; 2252 + etdm_data = afe_priv->dai_priv[dai->id]; 2253 + 2254 + /* dptx configure */ 2255 + if (dai->id == MT8188_AFE_IO_DPTX) { 2256 + regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2257 + AFE_DPTX_CON_CH_EN_MASK, 2258 + mtk_dai_get_dptx_ch_en(channels)); 2259 + regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2260 + AFE_DPTX_CON_CH_NUM_MASK, 2261 + mtk_dai_get_dptx_ch(channels)); 2262 + regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2263 + AFE_DPTX_CON_16BIT_MASK, 2264 + mtk_dai_get_dptx_wlen(format)); 2265 + 2266 + if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2267 + etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2268 + channels = 8; 2269 + } else { 2270 + channels = 2; 2271 + } 2272 + } else { 2273 + etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2274 + } 2275 + 2276 + ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2277 + if (ret) 2278 + return ret; 2279 + 2280 + ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2281 + 2282 + return ret; 2283 + } 2284 + 2285 + static int mtk_dai_hdmitx_dptx_prepare(struct snd_pcm_substream *substream, 2286 + struct snd_soc_dai *dai) 2287 + { 2288 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2289 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2290 + struct mtk_dai_etdm_priv *etdm_data; 2291 + 2292 + if (!is_valid_etdm_dai(dai->id)) 2293 + return -EINVAL; 2294 + etdm_data = afe_priv->dai_priv[dai->id]; 2295 + 2296 + dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 2297 + etdm_data->is_prepared); 2298 + 2299 + if (etdm_data->is_prepared) 2300 + return 0; 2301 + 2302 + etdm_data->is_prepared = true; 2303 + 2304 + /* enable dptx interface */ 2305 + if (dai->id == MT8188_AFE_IO_DPTX) 2306 + regmap_set_bits(afe->regmap, AFE_DPTX_CON, AFE_DPTX_CON_ON); 2307 + 2308 + /* enable etdm_out3 */ 2309 + return mt8188_afe_enable_etdm(afe, dai->id); 2310 + } 2311 + 2312 + static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2313 + int clk_id, 2314 + unsigned int freq, 2315 + int dir) 2316 + { 2317 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2318 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2319 + struct mtk_dai_etdm_priv *etdm_data; 2320 + 2321 + if (!is_valid_etdm_dai(dai->id)) 2322 + return -EINVAL; 2323 + etdm_data = afe_priv->dai_priv[dai->id]; 2324 + 2325 + dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2326 + __func__, dai->id, freq, dir); 2327 + 2328 + etdm_data->mclk_dir = dir; 2329 + return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2330 + } 2331 + 2332 + static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2333 + .startup = mtk_dai_etdm_startup, 2334 + .shutdown = mtk_dai_etdm_shutdown, 2335 + .hw_params = mtk_dai_etdm_hw_params, 2336 + .prepare = mtk_dai_etdm_prepare, 2337 + .set_sysclk = mtk_dai_etdm_set_sysclk, 2338 + .set_fmt = mtk_dai_etdm_set_fmt, 2339 + .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2340 + }; 2341 + 2342 + static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2343 + .startup = mtk_dai_hdmitx_dptx_startup, 2344 + .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2345 + .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2346 + .prepare = mtk_dai_hdmitx_dptx_prepare, 2347 + .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2348 + .set_fmt = mtk_dai_etdm_set_fmt, 2349 + }; 2350 + 2351 + /* dai driver */ 2352 + #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000) 2353 + 2354 + #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2355 + SNDRV_PCM_FMTBIT_S24_LE |\ 2356 + SNDRV_PCM_FMTBIT_S32_LE) 2357 + 2358 + static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2359 + { 2360 + .name = "DPTX", 2361 + .id = MT8188_AFE_IO_DPTX, 2362 + .playback = { 2363 + .stream_name = "DPTX", 2364 + .channels_min = 1, 2365 + .channels_max = 8, 2366 + .rates = MTK_ETDM_RATES, 2367 + .formats = MTK_ETDM_FORMATS, 2368 + }, 2369 + .ops = &mtk_dai_hdmitx_dptx_ops, 2370 + }, 2371 + { 2372 + .name = "ETDM1_IN", 2373 + .id = MT8188_AFE_IO_ETDM1_IN, 2374 + .capture = { 2375 + .stream_name = "ETDM1_IN", 2376 + .channels_min = 1, 2377 + .channels_max = 16, 2378 + .rates = MTK_ETDM_RATES, 2379 + .formats = MTK_ETDM_FORMATS, 2380 + }, 2381 + .ops = &mtk_dai_etdm_ops, 2382 + }, 2383 + { 2384 + .name = "ETDM2_IN", 2385 + .id = MT8188_AFE_IO_ETDM2_IN, 2386 + .capture = { 2387 + .stream_name = "ETDM2_IN", 2388 + .channels_min = 1, 2389 + .channels_max = 16, 2390 + .rates = MTK_ETDM_RATES, 2391 + .formats = MTK_ETDM_FORMATS, 2392 + }, 2393 + .ops = &mtk_dai_etdm_ops, 2394 + }, 2395 + { 2396 + .name = "ETDM1_OUT", 2397 + .id = MT8188_AFE_IO_ETDM1_OUT, 2398 + .playback = { 2399 + .stream_name = "ETDM1_OUT", 2400 + .channels_min = 1, 2401 + .channels_max = 16, 2402 + .rates = MTK_ETDM_RATES, 2403 + .formats = MTK_ETDM_FORMATS, 2404 + }, 2405 + .ops = &mtk_dai_etdm_ops, 2406 + }, 2407 + { 2408 + .name = "ETDM2_OUT", 2409 + .id = MT8188_AFE_IO_ETDM2_OUT, 2410 + .playback = { 2411 + .stream_name = "ETDM2_OUT", 2412 + .channels_min = 1, 2413 + .channels_max = 16, 2414 + .rates = MTK_ETDM_RATES, 2415 + .formats = MTK_ETDM_FORMATS, 2416 + }, 2417 + .ops = &mtk_dai_etdm_ops, 2418 + }, 2419 + { 2420 + .name = "ETDM3_OUT", 2421 + .id = MT8188_AFE_IO_ETDM3_OUT, 2422 + .playback = { 2423 + .stream_name = "ETDM3_OUT", 2424 + .channels_min = 1, 2425 + .channels_max = 8, 2426 + .rates = MTK_ETDM_RATES, 2427 + .formats = MTK_ETDM_FORMATS, 2428 + }, 2429 + .ops = &mtk_dai_hdmitx_dptx_ops, 2430 + }, 2431 + }; 2432 + 2433 + static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe) 2434 + { 2435 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2436 + struct mtk_dai_etdm_priv *etdm_data; 2437 + struct mtk_dai_etdm_priv *mst_data; 2438 + int mst_dai_id; 2439 + int i; 2440 + 2441 + for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2442 + etdm_data = afe_priv->dai_priv[i]; 2443 + if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2444 + mst_dai_id = etdm_data->cowork_source_id; 2445 + mst_data = afe_priv->dai_priv[mst_dai_id]; 2446 + if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2447 + dev_err(afe->dev, "%s [%d] wrong sync source\n", 2448 + __func__, i); 2449 + mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2450 + mst_data->cowork_slv_count++; 2451 + } 2452 + } 2453 + } 2454 + 2455 + static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe) 2456 + { 2457 + const struct device_node *of_node = afe->dev->of_node; 2458 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2459 + struct mtk_dai_etdm_priv *etdm_data; 2460 + char prop[48]; 2461 + u8 disable_chn[MT8188_ETDM_MAX_CHANNELS]; 2462 + int max_chn = MT8188_ETDM_MAX_CHANNELS; 2463 + unsigned int sync_id; 2464 + u32 sel; 2465 + int ret; 2466 + int dai_id; 2467 + int i, j; 2468 + struct { 2469 + const char *name; 2470 + const unsigned int sync_id; 2471 + } of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = { 2472 + {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2473 + {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2474 + {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2475 + {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2476 + {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2477 + }; 2478 + 2479 + for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) { 2480 + dai_id = ETDM_TO_DAI_ID(i); 2481 + etdm_data = afe_priv->dai_priv[dai_id]; 2482 + 2483 + ret = snprintf(prop, sizeof(prop), 2484 + "mediatek,%s-multi-pin-mode", 2485 + of_afe_etdms[i].name); 2486 + if (ret < 0) { 2487 + dev_err(afe->dev, "%s snprintf err=%d\n", 2488 + __func__, ret); 2489 + return; 2490 + } 2491 + etdm_data->data_mode = of_property_read_bool(of_node, prop); 2492 + 2493 + ret = snprintf(prop, sizeof(prop), 2494 + "mediatek,%s-cowork-source", 2495 + of_afe_etdms[i].name); 2496 + if (ret < 0) { 2497 + dev_err(afe->dev, "%s snprintf err=%d\n", 2498 + __func__, ret); 2499 + return; 2500 + } 2501 + ret = of_property_read_u32(of_node, prop, &sel); 2502 + if (ret == 0) { 2503 + if (sel >= MT8188_AFE_IO_ETDM_NUM) { 2504 + dev_err(afe->dev, "%s invalid id=%d\n", 2505 + __func__, sel); 2506 + etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2507 + } else { 2508 + sync_id = of_afe_etdms[sel].sync_id; 2509 + etdm_data->cowork_source_id = 2510 + sync_to_dai_id(sync_id); 2511 + } 2512 + } else { 2513 + etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2514 + } 2515 + } 2516 + 2517 + /* etdm in only */ 2518 + for (i = 0; i < 2; i++) { 2519 + ret = snprintf(prop, sizeof(prop), 2520 + "mediatek,%s-chn-disabled", 2521 + of_afe_etdms[i].name); 2522 + if (ret < 0) { 2523 + dev_err(afe->dev, "%s snprintf err=%d\n", 2524 + __func__, ret); 2525 + return; 2526 + } 2527 + ret = of_property_read_variable_u8_array(of_node, prop, 2528 + disable_chn, 2529 + 1, max_chn); 2530 + if (ret < 0) 2531 + continue; 2532 + 2533 + for (j = 0; j < ret; j++) { 2534 + if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS) 2535 + dev_err(afe->dev, "%s [%d] invalid chn %u\n", 2536 + __func__, j, disable_chn[j]); 2537 + else 2538 + etdm_data->in_disable_ch[disable_chn[j]] = true; 2539 + } 2540 + } 2541 + mt8188_etdm_update_sync_info(afe); 2542 + } 2543 + 2544 + static int init_etdm_priv_data(struct mtk_base_afe *afe) 2545 + { 2546 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 2547 + struct mtk_dai_etdm_priv *etdm_priv; 2548 + int i; 2549 + 2550 + for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2551 + etdm_priv = devm_kzalloc(afe->dev, 2552 + sizeof(struct mtk_dai_etdm_priv), 2553 + GFP_KERNEL); 2554 + if (!etdm_priv) 2555 + return -ENOMEM; 2556 + 2557 + afe_priv->dai_priv[i] = etdm_priv; 2558 + } 2559 + 2560 + afe_priv->dai_priv[MT8188_AFE_IO_DPTX] = 2561 + afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT]; 2562 + 2563 + mt8188_dai_etdm_parse_of(afe); 2564 + return 0; 2565 + } 2566 + 2567 + int mt8188_dai_etdm_register(struct mtk_base_afe *afe) 2568 + { 2569 + struct mtk_base_afe_dai *dai; 2570 + 2571 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2572 + if (!dai) 2573 + return -ENOMEM; 2574 + 2575 + list_add(&dai->list, &afe->sub_dais); 2576 + 2577 + dai->dai_drivers = mtk_dai_etdm_driver; 2578 + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2579 + 2580 + dai->dapm_widgets = mtk_dai_etdm_widgets; 2581 + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2582 + dai->dapm_routes = mtk_dai_etdm_routes; 2583 + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2584 + dai->controls = mtk_dai_etdm_controls; 2585 + dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2586 + 2587 + return init_etdm_priv_data(afe); 2588 + }

+367

sound/soc/mediatek/mt8188/mt8188-dai-pcm.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * MediaTek ALSA SoC Audio DAI PCM I/F Control 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #include <linux/bitfield.h> 12 + #include <linux/regmap.h> 13 + #include <sound/pcm_params.h> 14 + #include "mt8188-afe-clk.h" 15 + #include "mt8188-afe-common.h" 16 + #include "mt8188-reg.h" 17 + 18 + enum { 19 + MTK_DAI_PCM_FMT_I2S, 20 + MTK_DAI_PCM_FMT_EIAJ, 21 + MTK_DAI_PCM_FMT_MODEA, 22 + MTK_DAI_PCM_FMT_MODEB, 23 + }; 24 + 25 + enum { 26 + MTK_DAI_PCM_CLK_A1SYS, 27 + MTK_DAI_PCM_CLK_A2SYS, 28 + MTK_DAI_PCM_CLK_26M_48K, 29 + MTK_DAI_PCM_CLK_26M_441K, 30 + }; 31 + 32 + struct mtk_dai_pcm_rate { 33 + unsigned int rate; 34 + unsigned int reg_value; 35 + }; 36 + 37 + struct mtk_dai_pcmif_priv { 38 + unsigned int slave_mode; 39 + unsigned int lrck_inv; 40 + unsigned int bck_inv; 41 + unsigned int format; 42 + }; 43 + 44 + static const struct mtk_dai_pcm_rate mtk_dai_pcm_rates[] = { 45 + { .rate = 8000, .reg_value = 0, }, 46 + { .rate = 16000, .reg_value = 1, }, 47 + { .rate = 32000, .reg_value = 2, }, 48 + { .rate = 48000, .reg_value = 3, }, 49 + { .rate = 11025, .reg_value = 1, }, 50 + { .rate = 22050, .reg_value = 2, }, 51 + { .rate = 44100, .reg_value = 3, }, 52 + }; 53 + 54 + static int mtk_dai_pcm_mode(unsigned int rate) 55 + { 56 + int i; 57 + 58 + for (i = 0; i < ARRAY_SIZE(mtk_dai_pcm_rates); i++) 59 + if (mtk_dai_pcm_rates[i].rate == rate) 60 + return mtk_dai_pcm_rates[i].reg_value; 61 + 62 + return -EINVAL; 63 + } 64 + 65 + static const struct snd_kcontrol_new mtk_dai_pcm_o000_mix[] = { 66 + SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN0, 0, 1, 0), 67 + SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN0_2, 6, 1, 0), 68 + }; 69 + 70 + static const struct snd_kcontrol_new mtk_dai_pcm_o001_mix[] = { 71 + SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN1, 1, 1, 0), 72 + SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN1_2, 7, 1, 0), 73 + }; 74 + 75 + static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = { 76 + SND_SOC_DAPM_MIXER("I002", SND_SOC_NOPM, 0, 0, NULL, 0), 77 + SND_SOC_DAPM_MIXER("I003", SND_SOC_NOPM, 0, 0, NULL, 0), 78 + SND_SOC_DAPM_MIXER("O000", SND_SOC_NOPM, 0, 0, 79 + mtk_dai_pcm_o000_mix, 80 + ARRAY_SIZE(mtk_dai_pcm_o000_mix)), 81 + SND_SOC_DAPM_MIXER("O001", SND_SOC_NOPM, 0, 0, 82 + mtk_dai_pcm_o001_mix, 83 + ARRAY_SIZE(mtk_dai_pcm_o001_mix)), 84 + 85 + SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, 0, 0, NULL, 0), 86 + 87 + SND_SOC_DAPM_INPUT("PCM1_INPUT"), 88 + SND_SOC_DAPM_OUTPUT("PCM1_OUTPUT"), 89 + 90 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc11"), 91 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc12"), 92 + SND_SOC_DAPM_CLOCK_SUPPLY("aud_pcmif"), 93 + }; 94 + 95 + static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = { 96 + {"I002", NULL, "PCM1 Capture"}, 97 + {"I003", NULL, "PCM1 Capture"}, 98 + 99 + {"O000", "I000 Switch", "I000"}, 100 + {"O001", "I001 Switch", "I001"}, 101 + 102 + {"O000", "I070 Switch", "I070"}, 103 + {"O001", "I071 Switch", "I071"}, 104 + 105 + {"PCM1 Playback", NULL, "O000"}, 106 + {"PCM1 Playback", NULL, "O001"}, 107 + 108 + {"PCM1 Playback", NULL, "PCM_1_EN"}, 109 + {"PCM1 Playback", NULL, "aud_asrc12"}, 110 + {"PCM1 Playback", NULL, "aud_pcmif"}, 111 + 112 + {"PCM1 Capture", NULL, "PCM_1_EN"}, 113 + {"PCM1 Capture", NULL, "aud_asrc11"}, 114 + {"PCM1 Capture", NULL, "aud_pcmif"}, 115 + 116 + {"PCM1_OUTPUT", NULL, "PCM1 Playback"}, 117 + {"PCM1 Capture", NULL, "PCM1_INPUT"}, 118 + }; 119 + 120 + static int mtk_dai_pcm_configure(struct snd_pcm_substream *substream, 121 + struct snd_soc_dai *dai) 122 + { 123 + struct snd_pcm_runtime * const runtime = substream->runtime; 124 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 125 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 126 + struct mtk_dai_pcmif_priv *pcmif_priv = NULL; 127 + unsigned int slave_mode; 128 + unsigned int lrck_inv; 129 + unsigned int bck_inv; 130 + unsigned int fmt; 131 + unsigned int bit_width = dai->sample_bits; 132 + unsigned int val = 0; 133 + unsigned int mask = 0; 134 + int fs = 0; 135 + int mode = 0; 136 + 137 + if (dai->id < 0) 138 + return -EINVAL; 139 + 140 + pcmif_priv = afe_priv->dai_priv[dai->id]; 141 + slave_mode = pcmif_priv->slave_mode; 142 + lrck_inv = pcmif_priv->lrck_inv; 143 + bck_inv = pcmif_priv->bck_inv; 144 + fmt = pcmif_priv->format; 145 + 146 + /* sync freq mode */ 147 + fs = mt8188_afe_fs_timing(runtime->rate); 148 + if (fs < 0) 149 + return -EINVAL; 150 + 151 + val |= FIELD_PREP(PCM_INTF_CON2_SYNC_FREQ_MODE_MASK, fs); 152 + mask |= PCM_INTF_CON2_SYNC_FREQ_MODE_MASK; 153 + 154 + /* clk domain sel */ 155 + if (runtime->rate % 8000) 156 + val |= FIELD_PREP(PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK, 157 + MTK_DAI_PCM_CLK_26M_441K); 158 + else 159 + val |= FIELD_PREP(PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK, 160 + MTK_DAI_PCM_CLK_26M_48K); 161 + mask |= PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK; 162 + 163 + regmap_update_bits(afe->regmap, PCM_INTF_CON2, mask, val); 164 + 165 + val = 0; 166 + mask = 0; 167 + 168 + /* pcm mode */ 169 + mode = mtk_dai_pcm_mode(runtime->rate); 170 + if (mode < 0) 171 + return -EINVAL; 172 + 173 + val |= FIELD_PREP(PCM_INTF_CON1_PCM_MODE_MASK, mode); 174 + mask |= PCM_INTF_CON1_PCM_MODE_MASK; 175 + 176 + /* pcm format */ 177 + val |= FIELD_PREP(PCM_INTF_CON1_PCM_FMT_MASK, fmt); 178 + mask |= PCM_INTF_CON1_PCM_FMT_MASK; 179 + 180 + /* pcm sync length */ 181 + if (fmt == MTK_DAI_PCM_FMT_MODEA || 182 + fmt == MTK_DAI_PCM_FMT_MODEB) 183 + val |= FIELD_PREP(PCM_INTF_CON1_SYNC_LENGTH_MASK, 1); 184 + else 185 + val |= FIELD_PREP(PCM_INTF_CON1_SYNC_LENGTH_MASK, bit_width); 186 + mask |= PCM_INTF_CON1_SYNC_LENGTH_MASK; 187 + 188 + /* pcm bits, word length */ 189 + if (bit_width > 16) { 190 + val |= PCM_INTF_CON1_PCM_24BIT; 191 + val |= PCM_INTF_CON1_PCM_WLEN_64BCK; 192 + } else { 193 + val |= PCM_INTF_CON1_PCM_16BIT; 194 + val |= PCM_INTF_CON1_PCM_WLEN_32BCK; 195 + } 196 + mask |= PCM_INTF_CON1_PCM_BIT_MASK; 197 + mask |= PCM_INTF_CON1_PCM_WLEN_MASK; 198 + 199 + /* master/slave */ 200 + if (!slave_mode) { 201 + val |= PCM_INTF_CON1_PCM_MASTER; 202 + 203 + if (lrck_inv) 204 + val |= PCM_INTF_CON1_SYNC_OUT_INV; 205 + if (bck_inv) 206 + val |= PCM_INTF_CON1_BCLK_OUT_INV; 207 + mask |= PCM_INTF_CON1_CLK_OUT_INV_MASK; 208 + } else { 209 + val |= PCM_INTF_CON1_PCM_SLAVE; 210 + 211 + if (lrck_inv) 212 + val |= PCM_INTF_CON1_SYNC_IN_INV; 213 + if (bck_inv) 214 + val |= PCM_INTF_CON1_BCLK_IN_INV; 215 + mask |= PCM_INTF_CON1_CLK_IN_INV_MASK; 216 + 217 + // TODO: add asrc setting for slave mode 218 + } 219 + mask |= PCM_INTF_CON1_PCM_M_S_MASK; 220 + 221 + regmap_update_bits(afe->regmap, PCM_INTF_CON1, mask, val); 222 + 223 + return 0; 224 + } 225 + 226 + /* dai ops */ 227 + static int mtk_dai_pcm_prepare(struct snd_pcm_substream *substream, 228 + struct snd_soc_dai *dai) 229 + { 230 + if (dai->playback_widget->active || dai->capture_widget->active) 231 + return 0; 232 + 233 + return mtk_dai_pcm_configure(substream, dai); 234 + } 235 + 236 + static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 237 + { 238 + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 239 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 240 + struct mtk_dai_pcmif_priv *pcmif_priv = NULL; 241 + 242 + dev_dbg(dai->dev, "%s fmt 0x%x\n", __func__, fmt); 243 + 244 + if (dai->id < 0) 245 + return -EINVAL; 246 + 247 + pcmif_priv = afe_priv->dai_priv[dai->id]; 248 + 249 + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 250 + case SND_SOC_DAIFMT_I2S: 251 + pcmif_priv->format = MTK_DAI_PCM_FMT_I2S; 252 + break; 253 + case SND_SOC_DAIFMT_DSP_A: 254 + pcmif_priv->format = MTK_DAI_PCM_FMT_MODEA; 255 + break; 256 + case SND_SOC_DAIFMT_DSP_B: 257 + pcmif_priv->format = MTK_DAI_PCM_FMT_MODEB; 258 + break; 259 + default: 260 + return -EINVAL; 261 + } 262 + 263 + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 264 + case SND_SOC_DAIFMT_NB_NF: 265 + pcmif_priv->bck_inv = 0; 266 + pcmif_priv->lrck_inv = 0; 267 + break; 268 + case SND_SOC_DAIFMT_NB_IF: 269 + pcmif_priv->bck_inv = 0; 270 + pcmif_priv->lrck_inv = 1; 271 + break; 272 + case SND_SOC_DAIFMT_IB_NF: 273 + pcmif_priv->bck_inv = 1; 274 + pcmif_priv->lrck_inv = 0; 275 + break; 276 + case SND_SOC_DAIFMT_IB_IF: 277 + pcmif_priv->bck_inv = 1; 278 + pcmif_priv->lrck_inv = 1; 279 + break; 280 + default: 281 + return -EINVAL; 282 + } 283 + 284 + switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 285 + case SND_SOC_DAIFMT_BC_FC: 286 + pcmif_priv->slave_mode = 1; 287 + break; 288 + case SND_SOC_DAIFMT_BP_FP: 289 + pcmif_priv->slave_mode = 0; 290 + break; 291 + default: 292 + return -EINVAL; 293 + } 294 + 295 + return 0; 296 + } 297 + 298 + static const struct snd_soc_dai_ops mtk_dai_pcm_ops = { 299 + .prepare = mtk_dai_pcm_prepare, 300 + .set_fmt = mtk_dai_pcm_set_fmt, 301 + }; 302 + 303 + /* dai driver */ 304 + #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000) 305 + 306 + #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 307 + SNDRV_PCM_FMTBIT_S24_LE |\ 308 + SNDRV_PCM_FMTBIT_S32_LE) 309 + 310 + static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = { 311 + { 312 + .name = "PCM1", 313 + .id = MT8188_AFE_IO_PCM, 314 + .playback = { 315 + .stream_name = "PCM1 Playback", 316 + .channels_min = 1, 317 + .channels_max = 2, 318 + .rates = MTK_PCM_RATES, 319 + .formats = MTK_PCM_FORMATS, 320 + }, 321 + .capture = { 322 + .stream_name = "PCM1 Capture", 323 + .channels_min = 1, 324 + .channels_max = 2, 325 + .rates = MTK_PCM_RATES, 326 + .formats = MTK_PCM_FORMATS, 327 + }, 328 + .ops = &mtk_dai_pcm_ops, 329 + .symmetric_rate = 1, 330 + .symmetric_sample_bits = 1, 331 + }, 332 + }; 333 + 334 + static int init_pcmif_priv_data(struct mtk_base_afe *afe) 335 + { 336 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 337 + struct mtk_dai_pcmif_priv *pcmif_priv; 338 + 339 + pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_pcmif_priv), 340 + GFP_KERNEL); 341 + if (!pcmif_priv) 342 + return -ENOMEM; 343 + 344 + afe_priv->dai_priv[MT8188_AFE_IO_PCM] = pcmif_priv; 345 + return 0; 346 + } 347 + 348 + int mt8188_dai_pcm_register(struct mtk_base_afe *afe) 349 + { 350 + struct mtk_base_afe_dai *dai; 351 + 352 + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 353 + if (!dai) 354 + return -ENOMEM; 355 + 356 + list_add(&dai->list, &afe->sub_dais); 357 + 358 + dai->dai_drivers = mtk_dai_pcm_driver; 359 + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver); 360 + 361 + dai->dapm_widgets = mtk_dai_pcm_widgets; 362 + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets); 363 + dai->dapm_routes = mtk_dai_pcm_routes; 364 + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes); 365 + 366 + return init_pcmif_priv_data(afe); 367 + }

+785

sound/soc/mediatek/mt8188/mt8188-mt6359.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * mt8188-mt6359.c -- MT8188-MT6359 ALSA SoC machine driver 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Trevor Wu <trevor.wu@mediatek.com> 7 + */ 8 + 9 + #include <linux/module.h> 10 + #include <linux/of_device.h> 11 + #include <linux/pm_runtime.h> 12 + #include <sound/jack.h> 13 + #include <sound/pcm_params.h> 14 + #include <sound/soc.h> 15 + #include "mt8188-afe-common.h" 16 + #include "../../codecs/mt6359.h" 17 + #include "../common/mtk-afe-platform-driver.h" 18 + #include "../common/mtk-soundcard-driver.h" 19 + 20 + /* FE */ 21 + SND_SOC_DAILINK_DEFS(playback2, 22 + DAILINK_COMP_ARRAY(COMP_CPU("DL2")), 23 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 24 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 25 + 26 + SND_SOC_DAILINK_DEFS(playback3, 27 + DAILINK_COMP_ARRAY(COMP_CPU("DL3")), 28 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 29 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 30 + 31 + SND_SOC_DAILINK_DEFS(playback6, 32 + DAILINK_COMP_ARRAY(COMP_CPU("DL6")), 33 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 34 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 35 + 36 + SND_SOC_DAILINK_DEFS(playback7, 37 + DAILINK_COMP_ARRAY(COMP_CPU("DL7")), 38 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 39 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 40 + 41 + SND_SOC_DAILINK_DEFS(playback8, 42 + DAILINK_COMP_ARRAY(COMP_CPU("DL8")), 43 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 44 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 45 + 46 + SND_SOC_DAILINK_DEFS(playback10, 47 + DAILINK_COMP_ARRAY(COMP_CPU("DL10")), 48 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 49 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 50 + 51 + SND_SOC_DAILINK_DEFS(playback11, 52 + DAILINK_COMP_ARRAY(COMP_CPU("DL11")), 53 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 54 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 55 + 56 + SND_SOC_DAILINK_DEFS(capture1, 57 + DAILINK_COMP_ARRAY(COMP_CPU("UL1")), 58 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 59 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 60 + 61 + SND_SOC_DAILINK_DEFS(capture2, 62 + DAILINK_COMP_ARRAY(COMP_CPU("UL2")), 63 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 64 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 65 + 66 + SND_SOC_DAILINK_DEFS(capture3, 67 + DAILINK_COMP_ARRAY(COMP_CPU("UL3")), 68 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 69 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 70 + 71 + SND_SOC_DAILINK_DEFS(capture4, 72 + DAILINK_COMP_ARRAY(COMP_CPU("UL4")), 73 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 74 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 75 + 76 + SND_SOC_DAILINK_DEFS(capture5, 77 + DAILINK_COMP_ARRAY(COMP_CPU("UL5")), 78 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 79 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 80 + 81 + SND_SOC_DAILINK_DEFS(capture6, 82 + DAILINK_COMP_ARRAY(COMP_CPU("UL6")), 83 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 84 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 85 + 86 + SND_SOC_DAILINK_DEFS(capture8, 87 + DAILINK_COMP_ARRAY(COMP_CPU("UL8")), 88 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 89 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 90 + 91 + SND_SOC_DAILINK_DEFS(capture9, 92 + DAILINK_COMP_ARRAY(COMP_CPU("UL9")), 93 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 94 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 95 + 96 + SND_SOC_DAILINK_DEFS(capture10, 97 + DAILINK_COMP_ARRAY(COMP_CPU("UL10")), 98 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 99 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 100 + 101 + /* BE */ 102 + SND_SOC_DAILINK_DEFS(adda, 103 + DAILINK_COMP_ARRAY(COMP_CPU("ADDA")), 104 + DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound", 105 + "mt6359-snd-codec-aif1")), 106 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 107 + 108 + SND_SOC_DAILINK_DEFS(dptx, 109 + DAILINK_COMP_ARRAY(COMP_CPU("DPTX")), 110 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 111 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 112 + 113 + SND_SOC_DAILINK_DEFS(etdm1_in, 114 + DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")), 115 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 116 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 117 + 118 + SND_SOC_DAILINK_DEFS(etdm2_in, 119 + DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")), 120 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 121 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 122 + 123 + SND_SOC_DAILINK_DEFS(etdm1_out, 124 + DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")), 125 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 126 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 127 + 128 + SND_SOC_DAILINK_DEFS(etdm2_out, 129 + DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")), 130 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 131 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 132 + 133 + SND_SOC_DAILINK_DEFS(etdm3_out, 134 + DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")), 135 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 136 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 137 + 138 + SND_SOC_DAILINK_DEFS(pcm1, 139 + DAILINK_COMP_ARRAY(COMP_CPU("PCM1")), 140 + DAILINK_COMP_ARRAY(COMP_DUMMY()), 141 + DAILINK_COMP_ARRAY(COMP_EMPTY())); 142 + 143 + struct mt8188_mt6359_priv { 144 + struct snd_soc_jack dp_jack; 145 + struct snd_soc_jack hdmi_jack; 146 + }; 147 + 148 + struct mt8188_card_data { 149 + const char *name; 150 + unsigned long quirk; 151 + }; 152 + 153 + static const struct snd_soc_dapm_widget mt8188_mt6359_widgets[] = { 154 + SND_SOC_DAPM_HP("Headphone", NULL), 155 + SND_SOC_DAPM_MIC("Headset Mic", NULL), 156 + }; 157 + 158 + static const struct snd_kcontrol_new mt8188_mt6359_controls[] = { 159 + SOC_DAPM_PIN_SWITCH("Headphone"), 160 + SOC_DAPM_PIN_SWITCH("Headset Mic"), 161 + }; 162 + 163 + #define CKSYS_AUD_TOP_CFG 0x032c 164 + #define CKSYS_AUD_TOP_MON 0x0330 165 + 166 + static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd) 167 + { 168 + struct snd_soc_component *cmpnt_afe = 169 + snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 170 + struct snd_soc_component *cmpnt_codec = 171 + asoc_rtd_to_codec(rtd, 0)->component; 172 + struct mtk_base_afe *afe; 173 + struct mt8188_afe_private *afe_priv; 174 + struct mtkaif_param *param; 175 + int chosen_phase_1, chosen_phase_2; 176 + int prev_cycle_1, prev_cycle_2; 177 + int test_done_1, test_done_2; 178 + int cycle_1, cycle_2; 179 + int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM]; 180 + int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM]; 181 + int mtkaif_calibration_num_phase; 182 + bool mtkaif_calibration_ok; 183 + unsigned int monitor = 0; 184 + int counter; 185 + int phase; 186 + int i; 187 + 188 + if (!cmpnt_afe) 189 + return -EINVAL; 190 + 191 + afe = snd_soc_component_get_drvdata(cmpnt_afe); 192 + afe_priv = afe->platform_priv; 193 + param = &afe_priv->mtkaif_params; 194 + 195 + dev_dbg(afe->dev, "%s(), start\n", __func__); 196 + 197 + param->mtkaif_calibration_ok = false; 198 + for (i = 0; i < MT8188_MTKAIF_MISO_NUM; i++) { 199 + param->mtkaif_chosen_phase[i] = -1; 200 + param->mtkaif_phase_cycle[i] = 0; 201 + mtkaif_chosen_phase[i] = -1; 202 + mtkaif_phase_cycle[i] = 0; 203 + } 204 + 205 + if (IS_ERR(afe_priv->topckgen)) { 206 + dev_info(afe->dev, "%s() Cannot find topckgen controller\n", 207 + __func__); 208 + return 0; 209 + } 210 + 211 + pm_runtime_get_sync(afe->dev); 212 + mt6359_mtkaif_calibration_enable(cmpnt_codec); 213 + 214 + /* set test type to synchronizer pulse */ 215 + regmap_update_bits(afe_priv->topckgen, 216 + CKSYS_AUD_TOP_CFG, 0xffff, 0x4); 217 + mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */ 218 + mtkaif_calibration_ok = true; 219 + 220 + for (phase = 0; 221 + phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok; 222 + phase++) { 223 + mt6359_set_mtkaif_calibration_phase(cmpnt_codec, 224 + phase, phase, phase); 225 + 226 + regmap_set_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, 0x1); 227 + 228 + test_done_1 = 0; 229 + test_done_2 = 0; 230 + 231 + cycle_1 = -1; 232 + cycle_2 = -1; 233 + 234 + counter = 0; 235 + while (!(test_done_1 & test_done_2)) { 236 + regmap_read(afe_priv->topckgen, 237 + CKSYS_AUD_TOP_MON, &monitor); 238 + test_done_1 = (monitor >> 28) & 0x1; 239 + test_done_2 = (monitor >> 29) & 0x1; 240 + 241 + if (test_done_1 == 1) 242 + cycle_1 = monitor & 0xf; 243 + 244 + if (test_done_2 == 1) 245 + cycle_2 = (monitor >> 4) & 0xf; 246 + 247 + /* handle if never test done */ 248 + if (++counter > 10000) { 249 + dev_info(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, monitor 0x%x\n", 250 + __func__, 251 + cycle_1, cycle_2, monitor); 252 + mtkaif_calibration_ok = false; 253 + break; 254 + } 255 + } 256 + 257 + if (phase == 0) { 258 + prev_cycle_1 = cycle_1; 259 + prev_cycle_2 = cycle_2; 260 + } 261 + 262 + if (cycle_1 != prev_cycle_1 && 263 + mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] < 0) { 264 + mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] = phase - 1; 265 + mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] = prev_cycle_1; 266 + } 267 + 268 + if (cycle_2 != prev_cycle_2 && 269 + mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] < 0) { 270 + mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] = phase - 1; 271 + mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] = prev_cycle_2; 272 + } 273 + 274 + regmap_clear_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, 0x1); 275 + 276 + if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] >= 0 && 277 + mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] >= 0) 278 + break; 279 + } 280 + 281 + if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] < 0) { 282 + mtkaif_calibration_ok = false; 283 + chosen_phase_1 = 0; 284 + } else { 285 + chosen_phase_1 = mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0]; 286 + } 287 + 288 + if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] < 0) { 289 + mtkaif_calibration_ok = false; 290 + chosen_phase_2 = 0; 291 + } else { 292 + chosen_phase_2 = mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1]; 293 + } 294 + 295 + mt6359_set_mtkaif_calibration_phase(cmpnt_codec, 296 + chosen_phase_1, 297 + chosen_phase_2, 298 + 0); 299 + 300 + mt6359_mtkaif_calibration_disable(cmpnt_codec); 301 + pm_runtime_put(afe->dev); 302 + 303 + param->mtkaif_calibration_ok = mtkaif_calibration_ok; 304 + param->mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] = chosen_phase_1; 305 + param->mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] = chosen_phase_2; 306 + 307 + for (i = 0; i < MT8188_MTKAIF_MISO_NUM; i++) 308 + param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i]; 309 + 310 + dev_info(afe->dev, "%s(), end, calibration ok %d\n", 311 + __func__, param->mtkaif_calibration_ok); 312 + 313 + return 0; 314 + } 315 + 316 + static int mt8188_mt6359_init(struct snd_soc_pcm_runtime *rtd) 317 + { 318 + struct snd_soc_component *cmpnt_codec = 319 + asoc_rtd_to_codec(rtd, 0)->component; 320 + 321 + /* set mtkaif protocol */ 322 + mt6359_set_mtkaif_protocol(cmpnt_codec, 323 + MT6359_MTKAIF_PROTOCOL_2_CLK_P2); 324 + 325 + /* mtkaif calibration */ 326 + mt8188_mt6359_mtkaif_calibration(rtd); 327 + 328 + return 0; 329 + } 330 + 331 + enum { 332 + DAI_LINK_DL2_FE, 333 + DAI_LINK_DL3_FE, 334 + DAI_LINK_DL6_FE, 335 + DAI_LINK_DL7_FE, 336 + DAI_LINK_DL8_FE, 337 + DAI_LINK_DL10_FE, 338 + DAI_LINK_DL11_FE, 339 + DAI_LINK_UL1_FE, 340 + DAI_LINK_UL2_FE, 341 + DAI_LINK_UL3_FE, 342 + DAI_LINK_UL4_FE, 343 + DAI_LINK_UL5_FE, 344 + DAI_LINK_UL6_FE, 345 + DAI_LINK_UL8_FE, 346 + DAI_LINK_UL9_FE, 347 + DAI_LINK_UL10_FE, 348 + DAI_LINK_ADDA_BE, 349 + DAI_LINK_DPTX_BE, 350 + DAI_LINK_ETDM1_IN_BE, 351 + DAI_LINK_ETDM2_IN_BE, 352 + DAI_LINK_ETDM1_OUT_BE, 353 + DAI_LINK_ETDM2_OUT_BE, 354 + DAI_LINK_ETDM3_OUT_BE, 355 + DAI_LINK_PCM1_BE, 356 + }; 357 + 358 + static int mt8188_dptx_hw_params(struct snd_pcm_substream *substream, 359 + struct snd_pcm_hw_params *params) 360 + { 361 + struct snd_soc_pcm_runtime *rtd = substream->private_data; 362 + unsigned int rate = params_rate(params); 363 + unsigned int mclk_fs_ratio = 256; 364 + unsigned int mclk_fs = rate * mclk_fs_ratio; 365 + struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0); 366 + 367 + return snd_soc_dai_set_sysclk(dai, 0, mclk_fs, SND_SOC_CLOCK_OUT); 368 + } 369 + 370 + static const struct snd_soc_ops mt8188_dptx_ops = { 371 + .hw_params = mt8188_dptx_hw_params, 372 + }; 373 + 374 + static int mt8188_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, 375 + struct snd_pcm_hw_params *params) 376 + { 377 + /* fix BE i2s format to 32bit, clean param mask first */ 378 + snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), 379 + 0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST); 380 + 381 + params_set_format(params, SNDRV_PCM_FORMAT_S32_LE); 382 + 383 + return 0; 384 + } 385 + 386 + static int mt8188_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 387 + { 388 + struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card); 389 + struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; 390 + int ret = 0; 391 + 392 + ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 393 + &priv->hdmi_jack); 394 + if (ret) { 395 + dev_info(rtd->dev, "%s, new jack failed: %d\n", __func__, ret); 396 + return ret; 397 + } 398 + 399 + ret = snd_soc_component_set_jack(component, &priv->hdmi_jack, NULL); 400 + if (ret) 401 + dev_info(rtd->dev, "%s, set jack failed on %s (ret=%d)\n", 402 + __func__, component->name, ret); 403 + 404 + return ret; 405 + } 406 + 407 + static int mt8188_dptx_codec_init(struct snd_soc_pcm_runtime *rtd) 408 + { 409 + struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card); 410 + struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; 411 + int ret = 0; 412 + 413 + ret = snd_soc_card_jack_new(rtd->card, "DP Jack", SND_JACK_LINEOUT, 414 + &priv->dp_jack); 415 + if (ret) { 416 + dev_info(rtd->dev, "%s, new jack failed: %d\n", __func__, ret); 417 + return ret; 418 + } 419 + 420 + ret = snd_soc_component_set_jack(component, &priv->dp_jack, NULL); 421 + if (ret) 422 + dev_info(rtd->dev, "%s, set jack failed on %s (ret=%d)\n", 423 + __func__, component->name, ret); 424 + 425 + return ret; 426 + } 427 + 428 + static struct snd_soc_dai_link mt8188_mt6359_dai_links[] = { 429 + /* FE */ 430 + [DAI_LINK_DL2_FE] = { 431 + .name = "DL2_FE", 432 + .stream_name = "DL2 Playback", 433 + .trigger = { 434 + SND_SOC_DPCM_TRIGGER_POST, 435 + SND_SOC_DPCM_TRIGGER_POST, 436 + }, 437 + .dynamic = 1, 438 + .dpcm_playback = 1, 439 + SND_SOC_DAILINK_REG(playback2), 440 + }, 441 + [DAI_LINK_DL3_FE] = { 442 + .name = "DL3_FE", 443 + .stream_name = "DL3 Playback", 444 + .trigger = { 445 + SND_SOC_DPCM_TRIGGER_POST, 446 + SND_SOC_DPCM_TRIGGER_POST, 447 + }, 448 + .dynamic = 1, 449 + .dpcm_playback = 1, 450 + SND_SOC_DAILINK_REG(playback3), 451 + }, 452 + [DAI_LINK_DL6_FE] = { 453 + .name = "DL6_FE", 454 + .stream_name = "DL6 Playback", 455 + .trigger = { 456 + SND_SOC_DPCM_TRIGGER_POST, 457 + SND_SOC_DPCM_TRIGGER_POST, 458 + }, 459 + .dynamic = 1, 460 + .dpcm_playback = 1, 461 + SND_SOC_DAILINK_REG(playback6), 462 + }, 463 + [DAI_LINK_DL7_FE] = { 464 + .name = "DL7_FE", 465 + .stream_name = "DL7 Playback", 466 + .trigger = { 467 + SND_SOC_DPCM_TRIGGER_PRE, 468 + SND_SOC_DPCM_TRIGGER_PRE, 469 + }, 470 + .dynamic = 1, 471 + .dpcm_playback = 1, 472 + SND_SOC_DAILINK_REG(playback7), 473 + }, 474 + [DAI_LINK_DL8_FE] = { 475 + .name = "DL8_FE", 476 + .stream_name = "DL8 Playback", 477 + .trigger = { 478 + SND_SOC_DPCM_TRIGGER_POST, 479 + SND_SOC_DPCM_TRIGGER_POST, 480 + }, 481 + .dynamic = 1, 482 + .dpcm_playback = 1, 483 + SND_SOC_DAILINK_REG(playback8), 484 + }, 485 + [DAI_LINK_DL10_FE] = { 486 + .name = "DL10_FE", 487 + .stream_name = "DL10 Playback", 488 + .trigger = { 489 + SND_SOC_DPCM_TRIGGER_POST, 490 + SND_SOC_DPCM_TRIGGER_POST, 491 + }, 492 + .dynamic = 1, 493 + .dpcm_playback = 1, 494 + SND_SOC_DAILINK_REG(playback10), 495 + }, 496 + [DAI_LINK_DL11_FE] = { 497 + .name = "DL11_FE", 498 + .stream_name = "DL11 Playback", 499 + .trigger = { 500 + SND_SOC_DPCM_TRIGGER_POST, 501 + SND_SOC_DPCM_TRIGGER_POST, 502 + }, 503 + .dynamic = 1, 504 + .dpcm_playback = 1, 505 + SND_SOC_DAILINK_REG(playback11), 506 + }, 507 + [DAI_LINK_UL1_FE] = { 508 + .name = "UL1_FE", 509 + .stream_name = "UL1 Capture", 510 + .trigger = { 511 + SND_SOC_DPCM_TRIGGER_PRE, 512 + SND_SOC_DPCM_TRIGGER_PRE, 513 + }, 514 + .dynamic = 1, 515 + .dpcm_capture = 1, 516 + SND_SOC_DAILINK_REG(capture1), 517 + }, 518 + [DAI_LINK_UL2_FE] = { 519 + .name = "UL2_FE", 520 + .stream_name = "UL2 Capture", 521 + .trigger = { 522 + SND_SOC_DPCM_TRIGGER_POST, 523 + SND_SOC_DPCM_TRIGGER_POST, 524 + }, 525 + .dynamic = 1, 526 + .dpcm_capture = 1, 527 + SND_SOC_DAILINK_REG(capture2), 528 + }, 529 + [DAI_LINK_UL3_FE] = { 530 + .name = "UL3_FE", 531 + .stream_name = "UL3 Capture", 532 + .trigger = { 533 + SND_SOC_DPCM_TRIGGER_POST, 534 + SND_SOC_DPCM_TRIGGER_POST, 535 + }, 536 + .dynamic = 1, 537 + .dpcm_capture = 1, 538 + SND_SOC_DAILINK_REG(capture3), 539 + }, 540 + [DAI_LINK_UL4_FE] = { 541 + .name = "UL4_FE", 542 + .stream_name = "UL4 Capture", 543 + .trigger = { 544 + SND_SOC_DPCM_TRIGGER_POST, 545 + SND_SOC_DPCM_TRIGGER_POST, 546 + }, 547 + .dynamic = 1, 548 + .dpcm_capture = 1, 549 + SND_SOC_DAILINK_REG(capture4), 550 + }, 551 + [DAI_LINK_UL5_FE] = { 552 + .name = "UL5_FE", 553 + .stream_name = "UL5 Capture", 554 + .trigger = { 555 + SND_SOC_DPCM_TRIGGER_POST, 556 + SND_SOC_DPCM_TRIGGER_POST, 557 + }, 558 + .dynamic = 1, 559 + .dpcm_capture = 1, 560 + SND_SOC_DAILINK_REG(capture5), 561 + }, 562 + [DAI_LINK_UL6_FE] = { 563 + .name = "UL6_FE", 564 + .stream_name = "UL6 Capture", 565 + .trigger = { 566 + SND_SOC_DPCM_TRIGGER_PRE, 567 + SND_SOC_DPCM_TRIGGER_PRE, 568 + }, 569 + .dynamic = 1, 570 + .dpcm_capture = 1, 571 + SND_SOC_DAILINK_REG(capture6), 572 + }, 573 + [DAI_LINK_UL8_FE] = { 574 + .name = "UL8_FE", 575 + .stream_name = "UL8 Capture", 576 + .trigger = { 577 + SND_SOC_DPCM_TRIGGER_POST, 578 + SND_SOC_DPCM_TRIGGER_POST, 579 + }, 580 + .dynamic = 1, 581 + .dpcm_capture = 1, 582 + SND_SOC_DAILINK_REG(capture8), 583 + }, 584 + [DAI_LINK_UL9_FE] = { 585 + .name = "UL9_FE", 586 + .stream_name = "UL9 Capture", 587 + .trigger = { 588 + SND_SOC_DPCM_TRIGGER_POST, 589 + SND_SOC_DPCM_TRIGGER_POST, 590 + }, 591 + .dynamic = 1, 592 + .dpcm_capture = 1, 593 + SND_SOC_DAILINK_REG(capture9), 594 + }, 595 + [DAI_LINK_UL10_FE] = { 596 + .name = "UL10_FE", 597 + .stream_name = "UL10 Capture", 598 + .trigger = { 599 + SND_SOC_DPCM_TRIGGER_POST, 600 + SND_SOC_DPCM_TRIGGER_POST, 601 + }, 602 + .dynamic = 1, 603 + .dpcm_capture = 1, 604 + SND_SOC_DAILINK_REG(capture10), 605 + }, 606 + /* BE */ 607 + [DAI_LINK_ADDA_BE] = { 608 + .name = "ADDA_BE", 609 + .no_pcm = 1, 610 + .dpcm_playback = 1, 611 + .dpcm_capture = 1, 612 + .init = mt8188_mt6359_init, 613 + SND_SOC_DAILINK_REG(adda), 614 + }, 615 + [DAI_LINK_DPTX_BE] = { 616 + .name = "DPTX_BE", 617 + .ops = &mt8188_dptx_ops, 618 + .be_hw_params_fixup = mt8188_dptx_hw_params_fixup, 619 + .no_pcm = 1, 620 + .dpcm_playback = 1, 621 + SND_SOC_DAILINK_REG(dptx), 622 + }, 623 + [DAI_LINK_ETDM1_IN_BE] = { 624 + .name = "ETDM1_IN_BE", 625 + .no_pcm = 1, 626 + .dai_fmt = SND_SOC_DAIFMT_I2S | 627 + SND_SOC_DAIFMT_NB_NF | 628 + SND_SOC_DAIFMT_CBP_CFP, 629 + .dpcm_capture = 1, 630 + .ignore_suspend = 1, 631 + SND_SOC_DAILINK_REG(etdm1_in), 632 + }, 633 + [DAI_LINK_ETDM2_IN_BE] = { 634 + .name = "ETDM2_IN_BE", 635 + .no_pcm = 1, 636 + .dai_fmt = SND_SOC_DAIFMT_I2S | 637 + SND_SOC_DAIFMT_NB_NF | 638 + SND_SOC_DAIFMT_CBP_CFP, 639 + .dpcm_capture = 1, 640 + SND_SOC_DAILINK_REG(etdm2_in), 641 + }, 642 + [DAI_LINK_ETDM1_OUT_BE] = { 643 + .name = "ETDM1_OUT_BE", 644 + .no_pcm = 1, 645 + .dai_fmt = SND_SOC_DAIFMT_I2S | 646 + SND_SOC_DAIFMT_NB_NF | 647 + SND_SOC_DAIFMT_CBC_CFC, 648 + .dpcm_playback = 1, 649 + SND_SOC_DAILINK_REG(etdm1_out), 650 + }, 651 + [DAI_LINK_ETDM2_OUT_BE] = { 652 + .name = "ETDM2_OUT_BE", 653 + .no_pcm = 1, 654 + .dai_fmt = SND_SOC_DAIFMT_I2S | 655 + SND_SOC_DAIFMT_NB_NF | 656 + SND_SOC_DAIFMT_CBC_CFC, 657 + .dpcm_playback = 1, 658 + SND_SOC_DAILINK_REG(etdm2_out), 659 + }, 660 + [DAI_LINK_ETDM3_OUT_BE] = { 661 + .name = "ETDM3_OUT_BE", 662 + .no_pcm = 1, 663 + .dai_fmt = SND_SOC_DAIFMT_I2S | 664 + SND_SOC_DAIFMT_NB_NF | 665 + SND_SOC_DAIFMT_CBC_CFC, 666 + .dpcm_playback = 1, 667 + SND_SOC_DAILINK_REG(etdm3_out), 668 + }, 669 + [DAI_LINK_PCM1_BE] = { 670 + .name = "PCM1_BE", 671 + .no_pcm = 1, 672 + .dai_fmt = SND_SOC_DAIFMT_I2S | 673 + SND_SOC_DAIFMT_NB_NF | 674 + SND_SOC_DAIFMT_CBC_CFC, 675 + .dpcm_playback = 1, 676 + .dpcm_capture = 1, 677 + SND_SOC_DAILINK_REG(pcm1), 678 + }, 679 + }; 680 + 681 + static struct snd_soc_card mt8188_mt6359_soc_card = { 682 + .owner = THIS_MODULE, 683 + .dai_link = mt8188_mt6359_dai_links, 684 + .num_links = ARRAY_SIZE(mt8188_mt6359_dai_links), 685 + .dapm_widgets = mt8188_mt6359_widgets, 686 + .num_dapm_widgets = ARRAY_SIZE(mt8188_mt6359_widgets), 687 + .controls = mt8188_mt6359_controls, 688 + .num_controls = ARRAY_SIZE(mt8188_mt6359_controls), 689 + }; 690 + 691 + static int mt8188_mt6359_dev_probe(struct platform_device *pdev) 692 + { 693 + struct snd_soc_card *card = &mt8188_mt6359_soc_card; 694 + struct device_node *platform_node; 695 + struct mt8188_mt6359_priv *priv; 696 + struct mt8188_card_data *card_data; 697 + struct snd_soc_dai_link *dai_link; 698 + int ret, i; 699 + 700 + card_data = (struct mt8188_card_data *)of_device_get_match_data(&pdev->dev); 701 + card->dev = &pdev->dev; 702 + 703 + ret = snd_soc_of_parse_card_name(card, "model"); 704 + if (ret) 705 + return dev_err_probe(&pdev->dev, ret, "%s new card name parsing error\n", 706 + __func__); 707 + 708 + if (!card->name) 709 + card->name = card_data->name; 710 + 711 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 712 + if (!priv) 713 + return -ENOMEM; 714 + 715 + if (of_property_read_bool(pdev->dev.of_node, "audio-routing")) { 716 + ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); 717 + if (ret) 718 + return ret; 719 + } 720 + 721 + platform_node = of_parse_phandle(pdev->dev.of_node, 722 + "mediatek,platform", 0); 723 + if (!platform_node) { 724 + ret = -EINVAL; 725 + return dev_err_probe(&pdev->dev, ret, "Property 'platform' missing or invalid\n"); 726 + } 727 + 728 + ret = parse_dai_link_info(card); 729 + if (ret) 730 + goto err; 731 + 732 + for_each_card_prelinks(card, i, dai_link) { 733 + if (!dai_link->platforms->name) 734 + dai_link->platforms->of_node = platform_node; 735 + 736 + if (strcmp(dai_link->name, "DPTX_BE") == 0) { 737 + if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) 738 + dai_link->init = mt8188_dptx_codec_init; 739 + } else if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) { 740 + if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) 741 + dai_link->init = mt8188_hdmi_codec_init; 742 + } 743 + } 744 + 745 + snd_soc_card_set_drvdata(card, priv); 746 + 747 + ret = devm_snd_soc_register_card(&pdev->dev, card); 748 + if (ret) 749 + dev_err_probe(&pdev->dev, ret, "%s snd_soc_register_card fail\n", 750 + __func__); 751 + err: 752 + of_node_put(platform_node); 753 + clean_card_reference(card); 754 + return ret; 755 + } 756 + 757 + static struct mt8188_card_data mt8188_evb_card = { 758 + .name = "mt8188_mt6359", 759 + }; 760 + 761 + static const struct of_device_id mt8188_mt6359_dt_match[] = { 762 + { 763 + .compatible = "mediatek,mt8188-mt6359-evb", 764 + .data = &mt8188_evb_card, 765 + }, 766 + {}, 767 + }; 768 + MODULE_DEVICE_TABLE(of, mt8188_mt6359_dt_match); 769 + 770 + static struct platform_driver mt8188_mt6359_driver = { 771 + .driver = { 772 + .name = "mt8188_mt6359", 773 + .of_match_table = mt8188_mt6359_dt_match, 774 + .pm = &snd_soc_pm_ops, 775 + }, 776 + .probe = mt8188_mt6359_dev_probe, 777 + }; 778 + 779 + module_platform_driver(mt8188_mt6359_driver); 780 + 781 + /* Module information */ 782 + MODULE_DESCRIPTION("MT8188-MT6359 ALSA SoC machine driver"); 783 + MODULE_AUTHOR("Trevor Wu <trevor.wu@mediatek.com>"); 784 + MODULE_LICENSE("GPL"); 785 + MODULE_ALIAS("mt8188 mt6359 soc card");

+3180

sound/soc/mediatek/mt8188/mt8188-reg.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * mt8188-reg.h -- MediaTek 8188 audio driver reg definition 4 + * 5 + * Copyright (c) 2022 MediaTek Inc. 6 + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 + * Trevor Wu <trevor.wu@mediatek.com> 8 + * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 + */ 10 + 11 + #ifndef _MT8188_REG_H_ 12 + #define _MT8188_REG_H_ 13 + 14 + #define AUDIO_TOP_CON0 (0x0000) 15 + #define AUDIO_TOP_CON1 (0x0004) 16 + #define AUDIO_TOP_CON2 (0x0008) 17 + #define AUDIO_TOP_CON3 (0x000c) 18 + #define AUDIO_TOP_CON4 (0x0010) 19 + #define AUDIO_TOP_CON5 (0x0014) 20 + #define AUDIO_TOP_CON6 (0x0018) 21 + #define AFE_MAS_HADDR_MSB (0x0020) 22 + #define AFE_MEMIF_ONE_HEART (0x0024) 23 + #define AFE_MUX_SEL_CFG (0x0044) 24 + #define PWR1_ASM_CON1 (0x0108) 25 + #define ASYS_IRQ_CONFIG (0x0110) 26 + #define ASYS_IRQ1_CON (0x0114) 27 + #define ASYS_IRQ2_CON (0x0118) 28 + #define ASYS_IRQ3_CON (0x011c) 29 + #define ASYS_IRQ4_CON (0x0120) 30 + #define ASYS_IRQ5_CON (0x0124) 31 + #define ASYS_IRQ6_CON (0x0128) 32 + #define ASYS_IRQ7_CON (0x012c) 33 + #define ASYS_IRQ8_CON (0x0130) 34 + #define ASYS_IRQ9_CON (0x0134) 35 + #define ASYS_IRQ10_CON (0x0138) 36 + #define ASYS_IRQ11_CON (0x013c) 37 + #define ASYS_IRQ12_CON (0x0140) 38 + #define ASYS_IRQ13_CON (0x0144) 39 + #define ASYS_IRQ14_CON (0x0148) 40 + #define ASYS_IRQ15_CON (0x014c) 41 + #define ASYS_IRQ16_CON (0x0150) 42 + #define ASYS_IRQ_CLR (0x0154) 43 + #define ASYS_IRQ_STATUS (0x0158) 44 + #define ASYS_IRQ_MON1 (0x015c) 45 + #define ASYS_IRQ_MON2 (0x0160) 46 + #define AFE_IRQ1_CON (0x0164) 47 + #define AFE_IRQ2_CON (0x0168) 48 + #define AFE_IRQ3_CON (0x016c) 49 + #define AFE_IRQ_MCU_CLR (0x0170) 50 + #define AFE_IRQ_STATUS (0x0174) 51 + #define AFE_IRQ_MASK (0x0178) 52 + #define ASYS_IRQ_MASK (0x017c) 53 + #define AFE_IRQ3_CON_MON (0x01b0) 54 + #define AFE_IRQ_MCU_MON2 (0x01b4) 55 + #define AFE_IRQ8_CON (0x01b8) 56 + #define AFE_IRQ9_CON (0x01bc) 57 + #define AFE_IRQ10_CON (0x01c0) 58 + #define AFE_IRQ9_CON_MON (0x01c4) 59 + #define ADSP_IRQ_MASK (0x01c8) 60 + #define ADSP_IRQ_STATUS (0x01cc) 61 + #define AFE_SINEGEN_CON0 (0x01f0) 62 + #define AFE_SINEGEN_CON1 (0x01f4) 63 + #define AFE_SINEGEN_CON2 (0x01f8) 64 + #define AFE_SINEGEN_CON3 (0x01fc) 65 + #define AFE_SPDIF_OUT_CON0 (0x0380) 66 + #define AFE_TDMOUT_CONN0 (0x0390) 67 + #define PWR1_ASM_CON2 (0x03b0) 68 + #define PWR1_ASM_CON3 (0x03b4) 69 + #define AFE_APLL_TUNER_CFG (0x03f8) 70 + #define AFE_APLL_TUNER_CFG1 (0x03fc) 71 + #define AUDIO_TOP_STA0 (0x0400) 72 + #define AUDIO_TOP_STA1 (0x0404) 73 + #define AFE_GAIN1_CON0 (0x0410) 74 + #define AFE_GAIN1_CON1 (0x0414) 75 + #define AFE_GAIN1_CON2 (0x0418) 76 + #define AFE_GAIN1_CON3 (0x041c) 77 + #define AFE_GAIN1_CUR (0x0424) 78 + #define AFE_GAIN2_CON0 (0x0428) 79 + #define AFE_GAIN2_CON1 (0x042c) 80 + #define AFE_GAIN2_CON2 (0x0430) 81 + #define AFE_GAIN2_CON3 (0x0434) 82 + #define AFE_GAIN2_CUR (0x043c) 83 + #define AFE_IEC_CFG (0x0480) 84 + #define AFE_IEC_NSNUM (0x0484) 85 + #define AFE_IEC_BURST_INFO (0x0488) 86 + #define AFE_IEC_BURST_LEN (0x048c) 87 + #define AFE_IEC_NSADR (0x0490) 88 + #define AFE_IEC_CHL_STAT0 (0x04a0) 89 + #define AFE_IEC_CHL_STAT1 (0x04a4) 90 + #define AFE_IEC_CHR_STAT0 (0x04a8) 91 + #define AFE_IEC_CHR_STAT1 (0x04ac) 92 + #define AFE_SPDIFIN_CFG0 (0x0500) 93 + #define AFE_SPDIFIN_CFG1 (0x0504) 94 + #define AFE_SPDIFIN_CHSTS1 (0x0508) 95 + #define AFE_SPDIFIN_CHSTS2 (0x050c) 96 + #define AFE_SPDIFIN_CHSTS3 (0x0510) 97 + #define AFE_SPDIFIN_CHSTS4 (0x0514) 98 + #define AFE_SPDIFIN_CHSTS5 (0x0518) 99 + #define AFE_SPDIFIN_CHSTS6 (0x051c) 100 + #define AFE_SPDIFIN_DEBUG1 (0x0520) 101 + #define AFE_SPDIFIN_DEBUG2 (0x0524) 102 + #define AFE_SPDIFIN_DEBUG3 (0x0528) 103 + #define AFE_SPDIFIN_DEBUG4 (0x052c) 104 + #define AFE_SPDIFIN_EC (0x0530) 105 + #define AFE_SPDIFIN_CKLOCK_CFG (0x0534) 106 + #define AFE_SPDIFIN_BR (0x053c) 107 + #define AFE_SPDIFIN_BR_DBG1 (0x0540) 108 + #define AFE_SPDIFIN_CKFBDIV (0x0544) 109 + #define AFE_SPDIFIN_INT_EXT (0x0548) 110 + #define AFE_SPDIFIN_INT_EXT2 (0x054c) 111 + #define SPDIFIN_FREQ_INFO (0x0550) 112 + #define SPDIFIN_FREQ_INFO_2 (0x0554) 113 + #define SPDIFIN_FREQ_INFO_3 (0x0558) 114 + #define SPDIFIN_FREQ_STATUS (0x055c) 115 + #define SPDIFIN_USERCODE1 (0x0560) 116 + #define SPDIFIN_USERCODE2 (0x0564) 117 + #define SPDIFIN_USERCODE3 (0x0568) 118 + #define SPDIFIN_USERCODE4 (0x056c) 119 + #define SPDIFIN_USERCODE5 (0x0570) 120 + #define SPDIFIN_USERCODE6 (0x0574) 121 + #define SPDIFIN_USERCODE7 (0x0578) 122 + #define SPDIFIN_USERCODE8 (0x057c) 123 + #define SPDIFIN_USERCODE9 (0x0580) 124 + #define SPDIFIN_USERCODE10 (0x0584) 125 + #define SPDIFIN_USERCODE11 (0x0588) 126 + #define SPDIFIN_USERCODE12 (0x058c) 127 + #define AFE_SPDIFIN_APLL_TUNER_CFG (0x0594) 128 + #define AFE_SPDIFIN_APLL_TUNER_CFG1 (0x0598) 129 + #define ASYS_TOP_CON (0x0600) 130 + #define AFE_LINEIN_APLL_TUNER_CFG (0x0610) 131 + #define AFE_LINEIN_APLL_TUNER_MON (0x0614) 132 + #define AFE_EARC_APLL_TUNER_CFG (0x0618) 133 + #define AFE_EARC_APLL_TUNER_MON (0x061c) 134 + #define PWR2_TOP_CON0 (0x0634) 135 + #define PWR2_TOP_CON1 (0x0638) 136 + #define PCM_INTF_CON1 (0x063c) 137 + #define PCM_INTF_CON2 (0x0640) 138 + #define AFE_CM0_CON (0x0660) 139 + #define AFE_CM1_CON (0x0664) 140 + #define AFE_CM2_CON (0x0668) 141 + #define AFE_CM0_MON (0x0670) 142 + #define AFE_CM1_MON (0x0674) 143 + #define AFE_CM2_MON (0x0678) 144 + #define AFE_MPHONE_MULTI_CON0 (0x06a4) 145 + #define AFE_MPHONE_MULTI_CON1 (0x06a8) 146 + #define AFE_MPHONE_MULTI_CON2 (0x06ac) 147 + #define AFE_MPHONE_MULTI_MON (0x06b0) 148 + #define AFE_MPHONE_MULTI_DET_REG_CON0 (0x06b4) 149 + #define AFE_MPHONE_MULTI_DET_REG_CON1 (0x06b8) 150 + #define AFE_MPHONE_MULTI_DET_REG_CON2 (0x06bc) 151 + #define AFE_MPHONE_MULTI_DET_REG_CON3 (0x06c0) 152 + #define AFE_MPHONE_MULTI_DET_MON0 (0x06c4) 153 + #define AFE_MPHONE_MULTI_DET_MON1 (0x06c8) 154 + #define AFE_MPHONE_MULTI_DET_MON2 (0x06d0) 155 + #define AFE_MPHONE_MULTI2_CON0 (0x06d4) 156 + #define AFE_MPHONE_MULTI2_CON1 (0x06d8) 157 + #define AFE_MPHONE_MULTI2_CON2 (0x06dc) 158 + #define AFE_MPHONE_MULTI2_MON (0x06e0) 159 + #define AFE_MPHONE_MULTI2_DET_REG_CON0 (0x06e4) 160 + #define AFE_MPHONE_MULTI2_DET_REG_CON1 (0x06e8) 161 + #define AFE_MPHONE_MULTI2_DET_REG_CON2 (0x06ec) 162 + #define AFE_MPHONE_MULTI2_DET_REG_CON3 (0x06f0) 163 + #define AFE_MPHONE_MULTI2_DET_MON0 (0x06f4) 164 + #define AFE_MPHONE_MULTI2_DET_MON1 (0x06f8) 165 + #define AFE_MPHONE_MULTI2_DET_MON2 (0x06fc) 166 + #define AFE_ADDA_IIR_COEF_02_01 (0x0700) 167 + #define AFE_ADDA_IIR_COEF_04_03 (0x0704) 168 + #define AFE_ADDA_IIR_COEF_06_05 (0x0708) 169 + #define AFE_ADDA_IIR_COEF_08_07 (0x070c) 170 + #define AFE_ADDA_IIR_COEF_10_09 (0x0710) 171 + #define AFE_ADDA_ULCF_CFG_02_01 (0x0714) 172 + #define AFE_ADDA_ULCF_CFG_04_03 (0x0718) 173 + #define AFE_ADDA_ULCF_CFG_06_05 (0x071c) 174 + #define AFE_ADDA_ULCF_CFG_08_07 (0x0720) 175 + #define AFE_ADDA_ULCF_CFG_10_09 (0x0724) 176 + #define AFE_ADDA_ULCF_CFG_12_11 (0x0728) 177 + #define AFE_ADDA_ULCF_CFG_14_13 (0x072c) 178 + #define AFE_ADDA_ULCF_CFG_16_15 (0x0730) 179 + #define AFE_ADDA_ULCF_CFG_18_17 (0x0734) 180 + #define AFE_ADDA_ULCF_CFG_20_19 (0x0738) 181 + #define AFE_ADDA_ULCF_CFG_22_21 (0x073c) 182 + #define AFE_ADDA_ULCF_CFG_24_23 (0x0740) 183 + #define AFE_ADDA_ULCF_CFG_26_25 (0x0744) 184 + #define AFE_ADDA_ULCF_CFG_28_27 (0x0748) 185 + #define AFE_ADDA_ULCF_CFG_30_29 (0x074c) 186 + #define AFE_ADDA6_IIR_COEF_02_01 (0x0750) 187 + #define AFE_ADDA6_IIR_COEF_04_03 (0x0754) 188 + #define AFE_ADDA6_IIR_COEF_06_05 (0x0758) 189 + #define AFE_ADDA6_IIR_COEF_08_07 (0x075c) 190 + #define AFE_ADDA6_IIR_COEF_10_09 (0x0760) 191 + #define AFE_ADDA6_ULCF_CFG_02_01 (0x0764) 192 + #define AFE_ADDA6_ULCF_CFG_04_03 (0x0768) 193 + #define AFE_ADDA6_ULCF_CFG_06_05 (0x076c) 194 + #define AFE_ADDA6_ULCF_CFG_08_07 (0x0770) 195 + #define AFE_ADDA6_ULCF_CFG_10_09 (0x0774) 196 + #define AFE_ADDA6_ULCF_CFG_12_11 (0x0778) 197 + #define AFE_ADDA6_ULCF_CFG_14_13 (0x077c) 198 + #define AFE_ADDA6_ULCF_CFG_16_15 (0x0780) 199 + #define AFE_ADDA6_ULCF_CFG_18_17 (0x0784) 200 + #define AFE_ADDA6_ULCF_CFG_20_19 (0x0788) 201 + #define AFE_ADDA6_ULCF_CFG_22_21 (0x078c) 202 + #define AFE_ADDA6_ULCF_CFG_24_23 (0x0790) 203 + #define AFE_ADDA6_ULCF_CFG_26_25 (0x0794) 204 + #define AFE_ADDA6_ULCF_CFG_28_27 (0x0798) 205 + #define AFE_ADDA6_ULCF_CFG_30_29 (0x079c) 206 + #define AFE_ADDA_MTKAIF_CFG0 (0x07a0) 207 + #define AFE_ADDA_MTKAIF_SYNCWORD_CFG (0x07a8) 208 + #define AFE_ADDA_MTKAIF_RX_CFG0 (0x07b4) 209 + #define AFE_ADDA_MTKAIF_RX_CFG1 (0x07b8) 210 + #define AFE_ADDA_MTKAIF_RX_CFG2 (0x07bc) 211 + #define AFE_ADDA_MTKAIF_MON0 (0x07c8) 212 + #define AFE_ADDA_MTKAIF_MON1 (0x07cc) 213 + #define AFE_AUD_PAD_TOP (0x07d4) 214 + #define AFE_ADDA6_MTKAIF_MON0 (0x07d8) 215 + #define AFE_ADDA6_MTKAIF_MON1 (0x07dc) 216 + #define AFE_ADDA6_MTKAIF_CFG0 (0x07e0) 217 + #define AFE_ADDA6_MTKAIF_RX_CFG0 (0x07e4) 218 + #define AFE_ADDA6_MTKAIF_RX_CFG1 (0x07e8) 219 + #define AFE_ADDA6_MTKAIF_RX_CFG2 (0x07ec) 220 + #define AFE_ADDA6_TOP_CON0 (0x07f0) 221 + #define AFE_ADDA6_UL_SRC_CON0 (0x07f4) 222 + #define AFE_ADDA6_UL_SRC_CON1 (0x07f8) 223 + #define AFE_ADDA6_SRC_DEBUG (0x0800) 224 + #define AFE_ADDA6_SRC_DEBUG_MON0 (0x0804) 225 + #define AFE_ADDA6_UL_SRC_MON0 (0x0818) 226 + #define AFE_ADDA6_UL_SRC_MON1 (0x081c) 227 + #define AFE_CONN0_5 (0x0830) 228 + #define AFE_CONN1_5 (0x0834) 229 + #define AFE_CONN2_5 (0x0838) 230 + #define AFE_CONN3_5 (0x083c) 231 + #define AFE_CONN4_5 (0x0840) 232 + #define AFE_CONN5_5 (0x0844) 233 + #define AFE_CONN6_5 (0x0848) 234 + #define AFE_CONN7_5 (0x084c) 235 + #define AFE_CONN8_5 (0x0850) 236 + #define AFE_CONN9_5 (0x0854) 237 + #define AFE_CONN10_5 (0x0858) 238 + #define AFE_CONN11_5 (0x085c) 239 + #define AFE_CONN12_5 (0x0860) 240 + #define AFE_CONN13_5 (0x0864) 241 + #define AFE_CONN14_5 (0x0868) 242 + #define AFE_CONN15_5 (0x086c) 243 + #define AFE_CONN16_5 (0x0870) 244 + #define AFE_CONN17_5 (0x0874) 245 + #define AFE_CONN18_5 (0x0878) 246 + #define AFE_CONN19_5 (0x087c) 247 + #define AFE_CONN20_5 (0x0880) 248 + #define AFE_CONN21_5 (0x0884) 249 + #define AFE_CONN22_5 (0x0888) 250 + #define AFE_CONN23_5 (0x088c) 251 + #define AFE_CONN24_5 (0x0890) 252 + #define AFE_CONN25_5 (0x0894) 253 + #define AFE_CONN26_5 (0x0898) 254 + #define AFE_CONN27_5 (0x089c) 255 + #define AFE_CONN28_5 (0x08a0) 256 + #define AFE_CONN29_5 (0x08a4) 257 + #define AFE_CONN30_5 (0x08a8) 258 + #define AFE_CONN31_5 (0x08ac) 259 + #define AFE_CONN32_5 (0x08b0) 260 + #define AFE_CONN33_5 (0x08b4) 261 + #define AFE_CONN34_5 (0x08b8) 262 + #define AFE_CONN35_5 (0x08bc) 263 + #define AFE_CONN36_5 (0x08c0) 264 + #define AFE_CONN37_5 (0x08c4) 265 + #define AFE_CONN38_5 (0x08c8) 266 + #define AFE_CONN39_5 (0x08cc) 267 + #define AFE_CONN40_5 (0x08d0) 268 + #define AFE_CONN41_5 (0x08d4) 269 + #define AFE_CONN42_5 (0x08d8) 270 + #define AFE_CONN43_5 (0x08dc) 271 + #define AFE_CONN44_5 (0x08e0) 272 + #define AFE_CONN45_5 (0x08e4) 273 + #define AFE_CONN46_5 (0x08e8) 274 + #define AFE_CONN47_5 (0x08ec) 275 + #define AFE_CONN48_5 (0x08f0) 276 + #define AFE_CONN49_5 (0x08f4) 277 + #define AFE_CONN50_5 (0x08f8) 278 + #define AFE_CONN51_5 (0x08fc) 279 + #define AFE_CONN52_5 (0x0900) 280 + #define AFE_CONN53_5 (0x0904) 281 + #define AFE_CONN54_5 (0x0908) 282 + #define AFE_CONN55_5 (0x090c) 283 + #define AFE_CONN56_5 (0x0910) 284 + #define AFE_CONN57_5 (0x0914) 285 + #define AFE_CONN58_5 (0x0918) 286 + #define AFE_CONN59_5 (0x091c) 287 + #define AFE_CONN60_5 (0x0920) 288 + #define AFE_CONN61_5 (0x0924) 289 + #define AFE_CONN62_5 (0x0928) 290 + #define AFE_CONN63_5 (0x092c) 291 + #define AFE_CONN64_5 (0x0930) 292 + #define AFE_CONN65_5 (0x0934) 293 + #define AFE_CONN66_5 (0x0938) 294 + #define AFE_CONN67_5 (0x093c) 295 + #define AFE_CONN68_5 (0x0940) 296 + #define AFE_CONN69_5 (0x0944) 297 + #define AFE_CONN70_5 (0x0948) 298 + #define AFE_CONN71_5 (0x094c) 299 + #define AFE_CONN72_5 (0x0950) 300 + #define AFE_CONN73_5 (0x0954) 301 + #define AFE_CONN74_5 (0x0958) 302 + #define AFE_CONN75_5 (0x095c) 303 + #define AFE_CONN76_5 (0x0960) 304 + #define AFE_CONN77_5 (0x0964) 305 + #define AFE_CONN78_5 (0x0968) 306 + #define AFE_CONN79_5 (0x096c) 307 + #define AFE_CONN80_5 (0x0970) 308 + #define AFE_CONN81_5 (0x0974) 309 + #define AFE_CONN82_5 (0x0978) 310 + #define AFE_CONN83_5 (0x097c) 311 + #define AFE_CONN84_5 (0x0980) 312 + #define AFE_CONN85_5 (0x0984) 313 + #define AFE_CONN86_5 (0x0988) 314 + #define AFE_CONN87_5 (0x098c) 315 + #define AFE_CONN88_5 (0x0990) 316 + #define AFE_CONN89_5 (0x0994) 317 + #define AFE_CONN90_5 (0x0998) 318 + #define AFE_CONN91_5 (0x099c) 319 + #define AFE_CONN92_5 (0x09a0) 320 + #define AFE_CONN93_5 (0x09a4) 321 + #define AFE_CONN94_5 (0x09a8) 322 + #define AFE_CONN95_5 (0x09ac) 323 + #define AFE_CONN96_5 (0x09b0) 324 + #define AFE_CONN97_5 (0x09b4) 325 + #define AFE_CONN98_5 (0x09b8) 326 + #define AFE_CONN99_5 (0x09bc) 327 + #define AFE_CONN100_5 (0x09c0) 328 + #define AFE_CONN101_5 (0x09c4) 329 + #define AFE_CONN102_5 (0x09c8) 330 + #define AFE_CONN103_5 (0x09cc) 331 + #define AFE_CONN104_5 (0x09d0) 332 + #define AFE_CONN105_5 (0x09d4) 333 + #define AFE_CONN106_5 (0x09d8) 334 + #define AFE_CONN107_5 (0x09dc) 335 + #define AFE_CONN108_5 (0x09e0) 336 + #define AFE_CONN109_5 (0x09e4) 337 + #define AFE_CONN110_5 (0x09e8) 338 + #define AFE_CONN111_5 (0x09ec) 339 + #define AFE_CONN112_5 (0x09f0) 340 + #define AFE_CONN113_5 (0x09f4) 341 + #define AFE_CONN114_5 (0x09f8) 342 + #define AFE_CONN115_5 (0x09fc) 343 + #define AFE_CONN116_5 (0x0a00) 344 + #define AFE_CONN117_5 (0x0a04) 345 + #define AFE_CONN118_5 (0x0a08) 346 + #define AFE_CONN119_5 (0x0a0c) 347 + #define AFE_CONN120_5 (0x0a10) 348 + #define AFE_CONN121_5 (0x0a14) 349 + #define AFE_CONN122_5 (0x0a18) 350 + #define AFE_CONN123_5 (0x0a1c) 351 + #define AFE_CONN124_5 (0x0a20) 352 + #define AFE_CONN125_5 (0x0a24) 353 + #define AFE_CONN126_5 (0x0a28) 354 + #define AFE_CONN127_5 (0x0a2c) 355 + #define AFE_CONN128_5 (0x0a30) 356 + #define AFE_CONN129_5 (0x0a34) 357 + #define AFE_CONN130_5 (0x0a38) 358 + #define AFE_CONN131_5 (0x0a3c) 359 + #define AFE_CONN132_5 (0x0a40) 360 + #define AFE_CONN133_5 (0x0a44) 361 + #define AFE_CONN134_5 (0x0a48) 362 + #define AFE_CONN135_5 (0x0a4c) 363 + #define AFE_CONN136_5 (0x0a50) 364 + #define AFE_CONN137_5 (0x0a54) 365 + #define AFE_CONN138_5 (0x0a58) 366 + #define AFE_CONN139_5 (0x0a5c) 367 + #define AFE_CONN_RS_5 (0x0a60) 368 + #define AFE_CONN_DI_5 (0x0a64) 369 + #define AFE_CONN_16BIT_5 (0x0a68) 370 + #define AFE_CONN_24BIT_5 (0x0a6c) 371 + #define AFE_SECURE_MASK_CONN53_5 (0x0a70) 372 + #define AFE_SECURE_MASK_CONN54_5 (0x0a74) 373 + #define AFE_SECURE_MASK_CONN55_5 (0x0a78) 374 + #define AFE_SECURE_MASK_CONN56_5 (0x0a7c) 375 + #define AFE_SECURE_MASK_CONN57_5 (0x0a80) 376 + #define AFE_SECURE_MASK_CONN58_5 (0x0a84) 377 + #define AFE_SECURE_MASK_CONN59_5 (0x0a88) 378 + #define AFE_SECURE_MASK_CONN60_5 (0x0a8c) 379 + #define AFE_SECURE_MASK_CONN61_5 (0x0a90) 380 + #define AFE_SECURE_MASK_CONN62_5 (0x0a94) 381 + #define AFE_SECURE_MASK_CONN63_5 (0x0a98) 382 + #define AFE_SECURE_MASK_CONN64_5 (0x0a9c) 383 + #define AFE_SECURE_MASK_CONN65_5 (0x0aa0) 384 + #define AFE_SECURE_MASK_CONN66_5 (0x0aa4) 385 + #define AFE_SECURE_MASK_CONN67_5 (0x0aa8) 386 + #define AFE_SECURE_MASK_CONN68_5 (0x0aac) 387 + #define AFE_SECURE_MASK_CONN69_5 (0x0ab0) 388 + #define AFE_SECURE_MASK_CONN70_5 (0x0ab4) 389 + #define AFE_SECURE_MASK_CONN71_5 (0x0ab8) 390 + #define AFE_SECURE_MASK_CONN72_5 (0x0abc) 391 + #define AFE_SECURE_MASK_CONN73_5 (0x0ac0) 392 + #define AFE_SECURE_MASK_CONN74_5 (0x0ac4) 393 + #define AFE_SECURE_MASK_CONN75_5 (0x0ac8) 394 + #define AFE_SECURE_MASK_CONN76_5 (0x0acc) 395 + #define AFE_SECURE_MASK_CONN77_5 (0x0ad0) 396 + #define AFE_SECURE_MASK_CONN78_5 (0x0ad4) 397 + #define AFE_SECURE_MASK_CONN79_5 (0x0ad8) 398 + #define AFE_SECURE_MASK_CONN80_5 (0x0adc) 399 + #define AFE_SECURE_MASK_CONN81_5 (0x0ae0) 400 + #define AFE_SECURE_MASK_CONN82_5 (0x0ae4) 401 + #define AFE_SECURE_MASK_CONN83_5 (0x0ae8) 402 + #define AFE_SECURE_MASK_CONN84_5 (0x0aec) 403 + #define AFE_SECURE_MASK_CONN85_5 (0x0af0) 404 + #define AFE_SECURE_MASK_CONN86_5 (0x0af4) 405 + #define AFE_SECURE_MASK_CONN87_5 (0x0af8) 406 + #define AFE_SECURE_MASK_CONN88_5 (0x0afc) 407 + #define AFE_SECURE_MASK_CONN89_5 (0x0b00) 408 + #define AFE_SECURE_MASK_CONN90_5 (0x0b04) 409 + #define AFE_SECURE_MASK_CONN91_5 (0x0b08) 410 + #define AFE_SECURE_MASK_CONN92_5 (0x0b0c) 411 + #define AFE_SECURE_MASK_CONN93_5 (0x0b10) 412 + #define AFE_SECURE_MASK_CONN94_5 (0x0b14) 413 + #define AFE_SECURE_MASK_CONN95_5 (0x0b18) 414 + #define AFE_SECURE_MASK_CONN96_5 (0x0b1c) 415 + #define AFE_SECURE_MASK_CONN97_5 (0x0b20) 416 + #define AFE_SECURE_MASK_CONN98_5 (0x0b24) 417 + #define AFE_SECURE_MASK_CONN99_5 (0x0b28) 418 + #define AFE_SECURE_MASK_CONN100_5 (0x0b2c) 419 + #define AFE_SECURE_MASK_CONN101_5 (0x0b30) 420 + #define AFE_SECURE_MASK_CONN102_5 (0x0b34) 421 + #define AFE_SECURE_MASK_CONN103_5 (0x0b38) 422 + #define AFE_SECURE_MASK_CONN104_5 (0x0b3c) 423 + #define AFE_SECURE_MASK_CONN105_5 (0x0b40) 424 + #define AFE_SECURE_MASK_CONN106_5 (0x0b44) 425 + #define AFE_SECURE_MASK_CONN107_5 (0x0b48) 426 + #define AFE_SECURE_MASK_CONN108_5 (0x0b4c) 427 + #define AFE_SECURE_MASK_CONN109_5 (0x0b50) 428 + #define AFE_SECURE_MASK_CONN110_5 (0x0b54) 429 + #define AFE_SECURE_MASK_CONN111_5 (0x0b58) 430 + #define AFE_SECURE_MASK_CONN112_5 (0x0b5c) 431 + #define AFE_SECURE_MASK_CONN113_5 (0x0b60) 432 + #define AFE_SECURE_MASK_CONN114_5 (0x0b64) 433 + #define AFE_SECURE_MASK_CONN115_5 (0x0b68) 434 + #define AFE_SECURE_MASK_CONN116_5 (0x0b6c) 435 + #define AFE_SECURE_MASK_CONN117_5 (0x0b70) 436 + #define AFE_SECURE_MASK_CONN118_5 (0x0b74) 437 + #define AFE_SECURE_MASK_CONN119_5 (0x0b78) 438 + #define AFE_SECURE_MASK_CONN120_5 (0x0b7c) 439 + #define AFE_SECURE_MASK_CONN121_5 (0x0b80) 440 + #define AFE_SECURE_MASK_CONN122_5 (0x0b84) 441 + #define AFE_SECURE_MASK_CONN123_5 (0x0b88) 442 + #define AFE_SECURE_MASK_CONN124_5 (0x0b8c) 443 + #define AFE_SECURE_MASK_CONN125_5 (0x0b90) 444 + #define AFE_SECURE_MASK_CONN126_5 (0x0b94) 445 + #define AFE_SECURE_MASK_CONN127_5 (0x0b98) 446 + #define AFE_SECURE_MASK_CONN128_5 (0x0b9c) 447 + #define AFE_SECURE_MASK_CONN129_5 (0x0ba0) 448 + #define AFE_SECURE_MASK_CONN130_5 (0x0ba4) 449 + #define AFE_SECURE_MASK_CONN131_5 (0x0ba8) 450 + #define AFE_SECURE_MASK_CONN132_5 (0x0bac) 451 + #define AFE_SECURE_MASK_CONN133_5 (0x0bb0) 452 + #define AFE_SECURE_MASK_CONN134_5 (0x0bb4) 453 + #define AFE_SECURE_MASK_CONN135_5 (0x0bb8) 454 + #define AFE_SECURE_MASK_CONN136_5 (0x0bbc) 455 + #define AFE_SECURE_MASK_CONN137_5 (0x0bc0) 456 + #define AFE_SECURE_MASK_CONN138_5 (0x0bc4) 457 + #define AFE_SECURE_MASK_CONN139_5 (0x0bc8) 458 + #define AFE_SECURE_MASK_CONN_RS_5 (0x0bcc) 459 + #define AFE_SECURE_MASK_CONN_16BIT_5 (0x0bd0) 460 + #define AFE_SECURE_MASK_CONN_24BIT_5 (0x0bd4) 461 + #define AFE_ASRC11_NEW_CON0 (0x0d80) 462 + #define AFE_ASRC11_NEW_CON1 (0x0d84) 463 + #define AFE_ASRC11_NEW_CON2 (0x0d88) 464 + #define AFE_ASRC11_NEW_CON3 (0x0d8c) 465 + #define AFE_ASRC11_NEW_CON4 (0x0d90) 466 + #define AFE_ASRC11_NEW_CON5 (0x0d94) 467 + #define AFE_ASRC11_NEW_CON6 (0x0d98) 468 + #define AFE_ASRC11_NEW_CON7 (0x0d9c) 469 + #define AFE_ASRC11_NEW_CON8 (0x0da0) 470 + #define AFE_ASRC11_NEW_CON9 (0x0da4) 471 + #define AFE_ASRC11_NEW_CON10 (0x0da8) 472 + #define AFE_ASRC11_NEW_CON11 (0x0dac) 473 + #define AFE_ASRC11_NEW_CON13 (0x0db4) 474 + #define AFE_ASRC11_NEW_CON14 (0x0db8) 475 + #define AFE_ASRC12_NEW_CON0 (0x0dc0) 476 + #define AFE_ASRC12_NEW_CON1 (0x0dc4) 477 + #define AFE_ASRC12_NEW_CON2 (0x0dc8) 478 + #define AFE_ASRC12_NEW_CON3 (0x0dcc) 479 + #define AFE_ASRC12_NEW_CON4 (0x0dd0) 480 + #define AFE_ASRC12_NEW_CON5 (0x0dd4) 481 + #define AFE_ASRC12_NEW_CON6 (0x0dd8) 482 + #define AFE_ASRC12_NEW_CON7 (0x0ddc) 483 + #define AFE_ASRC12_NEW_CON8 (0x0de0) 484 + #define AFE_ASRC12_NEW_CON9 (0x0de4) 485 + #define AFE_ASRC12_NEW_CON10 (0x0de8) 486 + #define AFE_ASRC12_NEW_CON11 (0x0dec) 487 + #define AFE_ASRC12_NEW_CON13 (0x0df4) 488 + #define AFE_ASRC12_NEW_CON14 (0x0df8) 489 + #define AFE_SECURE_MASK_CONN176 (0x0fe0) 490 + #define AFE_SECURE_MASK_CONN176_1 (0x0fe4) 491 + #define AFE_SECURE_MASK_CONN176_2 (0x0fe8) 492 + #define AFE_SECURE_MASK_CONN176_3 (0x0fec) 493 + #define AFE_SECURE_MASK_CONN176_4 (0x0ff0) 494 + #define AFE_SECURE_MASK_CONN176_5 (0x0ff4) 495 + #define AFE_SECURE_MASK_CONN177 (0x0ff8) 496 + #define AFE_SECURE_MASK_CONN177_1 (0x0ffc) 497 + #define AFE_LRCK_CNT (0x1018) 498 + #define AFE_SECURE_MASK_CONN177_2 (0x1020) 499 + #define AFE_SECURE_MASK_CONN177_3 (0x1024) 500 + #define AFE_SECURE_MASK_CONN177_4 (0x1028) 501 + #define AFE_SECURE_MASK_CONN177_5 (0x102c) 502 + #define AFE_SECURE_MASK_CONN182 (0x1090) 503 + #define AFE_SECURE_MASK_CONN182_1 (0x1094) 504 + #define AFE_SECURE_MASK_CONN182_2 (0x1098) 505 + #define AFE_SECURE_MASK_CONN182_3 (0x109c) 506 + #define AFE_SECURE_MASK_CONN182_4 (0x10a0) 507 + #define AFE_SECURE_MASK_CONN182_5 (0x10a4) 508 + #define AFE_SECURE_MASK_CONN183 (0x10a8) 509 + #define AFE_SECURE_MASK_CONN183_1 (0x10ac) 510 + #define AFE_SECURE_MASK_CONN183_2 (0x10b0) 511 + #define AFE_SECURE_MASK_CONN183_3 (0x10b4) 512 + #define AFE_SECURE_MASK_CONN183_4 (0x10b8) 513 + #define AFE_SECURE_MASK_CONN183_5 (0x10bc) 514 + #define AFE_DAC_CON0 (0x1200) 515 + #define AFE_DAC_CON1 (0x1204) 516 + #define AFE_DAC_CON2 (0x1208) 517 + #define AFE_DAC_MON0 (0x1218) 518 + #define AFE_DL1_BASE (0x1240) 519 + #define AFE_DL1_CUR (0x1244) 520 + #define AFE_DL1_END (0x1248) 521 + #define AFE_DL1_CON0 (0x124c) 522 + #define AFE_DL2_BASE (0x1250) 523 + #define AFE_DL2_CUR (0x1254) 524 + #define AFE_DL2_END (0x1258) 525 + #define AFE_DL2_CON0 (0x125c) 526 + #define AFE_DL3_BASE (0x1260) 527 + #define AFE_DL3_CUR (0x1264) 528 + #define AFE_DL3_END (0x1268) 529 + #define AFE_DL3_CON0 (0x126c) 530 + #define AFE_DL6_BASE (0x1290) 531 + #define AFE_DL6_CUR (0x1294) 532 + #define AFE_DL6_END (0x1298) 533 + #define AFE_DL6_CON0 (0x129c) 534 + #define AFE_DL7_BASE (0x12a0) 535 + #define AFE_DL7_CUR (0x12a4) 536 + #define AFE_DL7_END (0x12a8) 537 + #define AFE_DL7_CON0 (0x12ac) 538 + #define AFE_DL8_BASE (0x12b0) 539 + #define AFE_DL8_CUR (0x12b4) 540 + #define AFE_DL8_END (0x12b8) 541 + #define AFE_DL8_CON0 (0x12bc) 542 + #define AFE_DL10_BASE (0x12d0) 543 + #define AFE_DL10_CUR (0x12d4) 544 + #define AFE_DL10_END (0x12d8) 545 + #define AFE_DL10_CON0 (0x12dc) 546 + #define AFE_DL11_BASE (0x12e0) 547 + #define AFE_DL11_CUR (0x12e4) 548 + #define AFE_DL11_END (0x12e8) 549 + #define AFE_DL11_CON0 (0x12ec) 550 + #define AFE_UL1_BASE (0x1300) 551 + #define AFE_UL1_CUR (0x1304) 552 + #define AFE_UL1_END (0x1308) 553 + #define AFE_UL1_CON0 (0x130c) 554 + #define AFE_UL2_BASE (0x1310) 555 + #define AFE_UL2_CUR (0x1314) 556 + #define AFE_UL2_END (0x1318) 557 + #define AFE_UL2_CON0 (0x131c) 558 + #define AFE_UL3_BASE (0x1320) 559 + #define AFE_UL3_CUR (0x1324) 560 + #define AFE_UL3_END (0x1328) 561 + #define AFE_UL3_CON0 (0x132c) 562 + #define AFE_UL4_BASE (0x1330) 563 + #define AFE_UL4_CUR (0x1334) 564 + #define AFE_UL4_END (0x1338) 565 + #define AFE_UL4_CON0 (0x133c) 566 + #define AFE_UL5_BASE (0x1340) 567 + #define AFE_UL5_CUR (0x1344) 568 + #define AFE_UL5_END (0x1348) 569 + #define AFE_UL5_CON0 (0x134c) 570 + #define AFE_UL6_BASE (0x1350) 571 + #define AFE_UL6_CUR (0x1354) 572 + #define AFE_UL6_END (0x1358) 573 + #define AFE_UL6_CON0 (0x135c) 574 + #define AFE_UL8_BASE (0x1370) 575 + #define AFE_UL8_CUR (0x1374) 576 + #define AFE_UL8_END (0x1378) 577 + #define AFE_UL8_CON0 (0x137c) 578 + #define AFE_UL9_BASE (0x1380) 579 + #define AFE_UL9_CUR (0x1384) 580 + #define AFE_UL9_END (0x1388) 581 + #define AFE_UL9_CON0 (0x138c) 582 + #define AFE_UL10_BASE (0x13d0) 583 + #define AFE_UL10_CUR (0x13d4) 584 + #define AFE_UL10_END (0x13d8) 585 + #define AFE_UL10_CON0 (0x13dc) 586 + #define AFE_DL8_CHK_SUM1 (0x1400) 587 + #define AFE_DL8_CHK_SUM2 (0x1404) 588 + #define AFE_DL8_CHK_SUM3 (0x1408) 589 + #define AFE_DL8_CHK_SUM4 (0x140c) 590 + #define AFE_DL8_CHK_SUM5 (0x1410) 591 + #define AFE_DL8_CHK_SUM6 (0x1414) 592 + #define AFE_DL10_CHK_SUM1 (0x1418) 593 + #define AFE_DL10_CHK_SUM2 (0x141c) 594 + #define AFE_DL10_CHK_SUM3 (0x1420) 595 + #define AFE_DL10_CHK_SUM4 (0x1424) 596 + #define AFE_DL10_CHK_SUM5 (0x1428) 597 + #define AFE_DL10_CHK_SUM6 (0x142c) 598 + #define AFE_DL11_CHK_SUM1 (0x1430) 599 + #define AFE_DL11_CHK_SUM2 (0x1434) 600 + #define AFE_DL11_CHK_SUM3 (0x1438) 601 + #define AFE_DL11_CHK_SUM4 (0x143c) 602 + #define AFE_DL11_CHK_SUM5 (0x1440) 603 + #define AFE_DL11_CHK_SUM6 (0x1444) 604 + #define AFE_UL1_CHK_SUM1 (0x1450) 605 + #define AFE_UL1_CHK_SUM2 (0x1454) 606 + #define AFE_UL2_CHK_SUM1 (0x1458) 607 + #define AFE_UL2_CHK_SUM2 (0x145c) 608 + #define AFE_UL3_CHK_SUM1 (0x1460) 609 + #define AFE_UL3_CHK_SUM2 (0x1464) 610 + #define AFE_UL4_CHK_SUM1 (0x1468) 611 + #define AFE_UL4_CHK_SUM2 (0x146c) 612 + #define AFE_UL5_CHK_SUM1 (0x1470) 613 + #define AFE_UL5_CHK_SUM2 (0x1474) 614 + #define AFE_UL6_CHK_SUM1 (0x1478) 615 + #define AFE_UL6_CHK_SUM2 (0x147c) 616 + #define AFE_UL8_CHK_SUM1 (0x1488) 617 + #define AFE_UL8_CHK_SUM2 (0x148c) 618 + #define AFE_DL1_CHK_SUM1 (0x1490) 619 + #define AFE_DL1_CHK_SUM2 (0x1494) 620 + #define AFE_DL2_CHK_SUM1 (0x14a0) 621 + #define AFE_DL2_CHK_SUM2 (0x14a4) 622 + #define AFE_DL3_CHK_SUM1 (0x14b0) 623 + #define AFE_DL3_CHK_SUM2 (0x14b4) 624 + #define AFE_DL6_CHK_SUM1 (0x14e0) 625 + #define AFE_DL6_CHK_SUM2 (0x14e4) 626 + #define AFE_DL7_CHK_SUM1 (0x14f0) 627 + #define AFE_DL7_CHK_SUM2 (0x14f4) 628 + #define AFE_UL9_CHK_SUM1 (0x1528) 629 + #define AFE_UL9_CHK_SUM2 (0x152c) 630 + #define AFE_BUS_MON1 (0x1540) 631 + #define AFE_UL10_CHK_SUM1 (0x1550) 632 + #define AFE_UL10_CHK_SUM2 (0x1554) 633 + #define UL1_MOD2AGT_CNT_LAT (0x1568) 634 + #define UL2_MOD2AGT_CNT_LAT (0x156c) 635 + #define UL3_MOD2AGT_CNT_LAT (0x1570) 636 + #define UL4_MOD2AGT_CNT_LAT (0x1574) 637 + #define UL5_MOD2AGT_CNT_LAT (0x1578) 638 + #define UL6_MOD2AGT_CNT_LAT (0x157c) 639 + #define UL8_MOD2AGT_CNT_LAT (0x1588) 640 + #define UL9_MOD2AGT_CNT_LAT (0x158c) 641 + #define UL10_MOD2AGT_CNT_LAT (0x1590) 642 + #define AFE_MEMIF_AGENT_FS_CON0 (0x15a0) 643 + #define AFE_MEMIF_AGENT_FS_CON1 (0x15a4) 644 + #define AFE_MEMIF_AGENT_FS_CON2 (0x15a8) 645 + #define AFE_MEMIF_AGENT_FS_CON3 (0x15ac) 646 + #define AFE_MEMIF_BURST_CFG (0x1600) 647 + #define AFE_MEMIF_BUF_FULL_MON (0x1610) 648 + #define AFE_MEMIF_BUF_MON0 (0x1618) 649 + #define AFE_MEMIF_BUF_MON1 (0x161c) 650 + #define AFE_MEMIF_BUF_MON3 (0x1624) 651 + #define AFE_MEMIF_BUF_MON4 (0x1628) 652 + #define AFE_MEMIF_BUF_MON5 (0x162c) 653 + #define AFE_MEMIF_BUF_MON6 (0x1630) 654 + #define AFE_MEMIF_BUF_MON7 (0x1634) 655 + #define AFE_MEMIF_BUF_MON8 (0x1638) 656 + #define AFE_MEMIF_BUF_MON9 (0x163c) 657 + #define AFE_MEMIF_BUF_MON10 (0x1640) 658 + #define DL1_AGENT2MODULE_CNT (0x1674) 659 + #define DL2_AGENT2MODULE_CNT (0x1678) 660 + #define DL3_AGENT2MODULE_CNT (0x167c) 661 + #define DL6_AGENT2MODULE_CNT (0x1688) 662 + #define DL7_AGENT2MODULE_CNT (0x168c) 663 + #define DL8_AGENT2MODULE_CNT (0x1690) 664 + #define DL10_AGENT2MODULE_CNT (0x1698) 665 + #define DL11_AGENT2MODULE_CNT (0x169c) 666 + #define UL1_MODULE2AGENT_CNT (0x16a0) 667 + #define UL2_MODULE2AGENT_CNT (0x16a4) 668 + #define UL3_MODULE2AGENT_CNT (0x16a8) 669 + #define UL4_MODULE2AGENT_CNT (0x16ac) 670 + #define UL5_MODULE2AGENT_CNT (0x16b0) 671 + #define UL6_MODULE2AGENT_CNT (0x16b4) 672 + #define UL8_MODULE2AGENT_CNT (0x16bc) 673 + #define UL9_MODULE2AGENT_CNT (0x16c0) 674 + #define UL10_MODULE2AGENT_CNT (0x16c4) 675 + #define AFE_SECURE_CON2 (0x1798) 676 + #define AFE_SECURE_CON1 (0x179c) 677 + #define AFE_SECURE_CON (0x17a0) 678 + #define AFE_SRAM_BOUND (0x17a4) 679 + #define AFE_SE_SECURE_CON (0x17a8) 680 + #define AFE_SECURE_MASK_LOOPBACK (0x17bc) 681 + #define AFE_SRAM_SECURE_CON (0x1800) 682 + #define AFE_SRAM_SECURE_CON1 (0x1804) 683 + #define AFE_SRAM_SECURE_CON2 (0x1808) 684 + #define AFE_SECURE_SIDEBAND0 (0x1908) 685 + #define AFE_SECURE_SIDEBAND1 (0x190c) 686 + #define AFE_SECURE_SIDEBAND2 (0x1910) 687 + #define AFE_SECURE_SIDEBAND3 (0x1914) 688 + #define AFE_SECURE_MASK_BASE_ADR_MSB (0x1920) 689 + #define AFE_SECURE_MASK_END_ADR_MSB (0x1924) 690 + #define AFE_NORMAL_BASE_ADR_MSB (0x192c) 691 + #define AFE_NORMAL_END_ADR_MSB (0x1930) 692 + #define AFE_SECURE_MASK_LOOPBACK0 (0x1940) 693 + #define AFE_SECURE_MASK_LOOPBACK1 (0x1944) 694 + #define AFE_SECURE_MASK_LOOPBACK2 (0x1948) 695 + #define AFE_LOOPBACK_CFG0 (0x1950) 696 + #define AFE_LOOPBACK_CFG1 (0x1954) 697 + #define AFE_LOOPBACK_CFG2 (0x1958) 698 + #define AFE_DMIC0_UL_SRC_CON0 (0x1a00) 699 + #define AFE_DMIC0_UL_SRC_CON1 (0x1a04) 700 + #define AFE_DMIC0_SRC_DEBUG (0x1a08) 701 + #define AFE_DMIC0_SRC_DEBUG_MON0 (0x1a0c) 702 + #define AFE_DMIC0_UL_SRC_MON0 (0x1a10) 703 + #define AFE_DMIC0_UL_SRC_MON1 (0x1a14) 704 + #define AFE_DMIC0_IIR_COEF_02_01 (0x1a18) 705 + #define AFE_DMIC0_IIR_COEF_04_03 (0x1a1c) 706 + #define AFE_DMIC0_IIR_COEF_06_05 (0x1a20) 707 + #define AFE_DMIC0_IIR_COEF_08_07 (0x1a24) 708 + #define AFE_DMIC0_IIR_COEF_10_09 (0x1a28) 709 + #define AFE_DMIC1_UL_SRC_CON0 (0x1a68) 710 + #define AFE_DMIC1_UL_SRC_CON1 (0x1a6c) 711 + #define AFE_DMIC1_SRC_DEBUG (0x1a70) 712 + #define AFE_DMIC1_SRC_DEBUG_MON0 (0x1a74) 713 + #define AFE_DMIC1_UL_SRC_MON0 (0x1a78) 714 + #define AFE_DMIC1_UL_SRC_MON1 (0x1a7c) 715 + #define AFE_DMIC1_IIR_COEF_02_01 (0x1a80) 716 + #define AFE_DMIC1_IIR_COEF_04_03 (0x1a84) 717 + #define AFE_DMIC1_IIR_COEF_06_05 (0x1a88) 718 + #define AFE_DMIC1_IIR_COEF_08_07 (0x1a8c) 719 + #define AFE_DMIC1_IIR_COEF_10_09 (0x1a90) 720 + #define AFE_DMIC2_UL_SRC_CON0 (0x1ad0) 721 + #define AFE_DMIC2_UL_SRC_CON1 (0x1ad4) 722 + #define AFE_DMIC2_SRC_DEBUG (0x1ad8) 723 + #define AFE_DMIC2_SRC_DEBUG_MON0 (0x1adc) 724 + #define AFE_DMIC2_UL_SRC_MON0 (0x1ae0) 725 + #define AFE_DMIC2_UL_SRC_MON1 (0x1ae4) 726 + #define AFE_DMIC2_IIR_COEF_02_01 (0x1ae8) 727 + #define AFE_DMIC2_IIR_COEF_04_03 (0x1aec) 728 + #define AFE_DMIC2_IIR_COEF_06_05 (0x1af0) 729 + #define AFE_DMIC2_IIR_COEF_08_07 (0x1af4) 730 + #define AFE_DMIC2_IIR_COEF_10_09 (0x1af8) 731 + #define AFE_DMIC3_UL_SRC_CON0 (0x1b38) 732 + #define AFE_DMIC3_UL_SRC_CON1 (0x1b3c) 733 + #define AFE_DMIC3_SRC_DEBUG (0x1b40) 734 + #define AFE_DMIC3_SRC_DEBUG_MON0 (0x1b44) 735 + #define AFE_DMIC3_UL_SRC_MON0 (0x1b48) 736 + #define AFE_DMIC3_UL_SRC_MON1 (0x1b4c) 737 + #define AFE_DMIC3_IIR_COEF_02_01 (0x1b50) 738 + #define AFE_DMIC3_IIR_COEF_04_03 (0x1b54) 739 + #define AFE_DMIC3_IIR_COEF_06_05 (0x1b58) 740 + #define AFE_DMIC3_IIR_COEF_08_07 (0x1b5c) 741 + #define AFE_DMIC3_IIR_COEF_10_09 (0x1b60) 742 + #define DMIC_BYPASS_HW_GAIN (0x1bf0) 743 + #define DMIC_GAIN1_CON0 (0x1c00) 744 + #define DMIC_GAIN1_CON1 (0x1c04) 745 + #define DMIC_GAIN1_CON2 (0x1c08) 746 + #define DMIC_GAIN1_CON3 (0x1c0c) 747 + #define DMIC_GAIN1_CUR (0x1c10) 748 + #define DMIC_GAIN2_CON0 (0x1c20) 749 + #define DMIC_GAIN2_CON1 (0x1c24) 750 + #define DMIC_GAIN2_CON2 (0x1c28) 751 + #define DMIC_GAIN2_CON3 (0x1c2c) 752 + #define DMIC_GAIN2_CUR (0x1c30) 753 + #define DMIC_GAIN3_CON0 (0x1c40) 754 + #define DMIC_GAIN3_CON1 (0x1c44) 755 + #define DMIC_GAIN3_CON2 (0x1c48) 756 + #define DMIC_GAIN3_CON3 (0x1c4c) 757 + #define DMIC_GAIN3_CUR (0x1c50) 758 + #define DMIC_GAIN4_CON0 (0x1c60) 759 + #define DMIC_GAIN4_CON1 (0x1c64) 760 + #define DMIC_GAIN4_CON2 (0x1c68) 761 + #define DMIC_GAIN4_CON3 (0x1c6c) 762 + #define DMIC_GAIN4_CUR (0x1c70) 763 + #define ETDM_OUT1_DSD_FADE_CON (0x2260) 764 + #define ETDM_OUT1_DSD_FADE_CON1 (0x2264) 765 + #define ETDM_OUT3_DSD_FADE_CON (0x2280) 766 + #define ETDM_OUT3_DSD_FADE_CON1 (0x2284) 767 + #define ETDM_IN1_AFIFO_CON (0x2294) 768 + #define ETDM_IN2_AFIFO_CON (0x2298) 769 + #define ETDM_IN1_MONITOR (0x22c0) 770 + #define ETDM_IN2_MONITOR (0x22c4) 771 + #define ETDM_OUT1_MONITOR (0x22d0) 772 + #define ETDM_OUT2_MONITOR (0x22d4) 773 + #define ETDM_OUT3_MONITOR (0x22d8) 774 + #define ETDM_COWORK_SEC_CON0 (0x22e0) 775 + #define ETDM_COWORK_SEC_CON1 (0x22e4) 776 + #define ETDM_COWORK_SEC_CON2 (0x22e8) 777 + #define ETDM_COWORK_SEC_CON3 (0x22ec) 778 + #define ETDM_COWORK_CON0 (0x22f0) 779 + #define ETDM_COWORK_CON1 (0x22f4) 780 + #define ETDM_COWORK_CON2 (0x22f8) 781 + #define ETDM_COWORK_CON3 (0x22fc) 782 + #define ETDM_IN1_CON0 (0x2300) 783 + #define ETDM_IN1_CON1 (0x2304) 784 + #define ETDM_IN1_CON2 (0x2308) 785 + #define ETDM_IN1_CON3 (0x230c) 786 + #define ETDM_IN1_CON4 (0x2310) 787 + #define ETDM_IN1_CON5 (0x2314) 788 + #define ETDM_IN1_CON6 (0x2318) 789 + #define ETDM_IN1_CON7 (0x231c) 790 + #define ETDM_IN2_CON0 (0x2320) 791 + #define ETDM_IN2_CON1 (0x2324) 792 + #define ETDM_IN2_CON2 (0x2328) 793 + #define ETDM_IN2_CON3 (0x232c) 794 + #define ETDM_IN2_CON4 (0x2330) 795 + #define ETDM_IN2_CON5 (0x2334) 796 + #define ETDM_IN2_CON6 (0x2338) 797 + #define ETDM_IN2_CON7 (0x233c) 798 + #define ETDM_OUT1_CON0 (0x2380) 799 + #define ETDM_OUT1_CON1 (0x2384) 800 + #define ETDM_OUT1_CON2 (0x2388) 801 + #define ETDM_OUT1_CON3 (0x238c) 802 + #define ETDM_OUT1_CON4 (0x2390) 803 + #define ETDM_OUT1_CON5 (0x2394) 804 + #define ETDM_OUT1_CON6 (0x2398) 805 + #define ETDM_OUT1_CON7 (0x239c) 806 + #define ETDM_OUT2_CON0 (0x23a0) 807 + #define ETDM_OUT2_CON1 (0x23a4) 808 + #define ETDM_OUT2_CON2 (0x23a8) 809 + #define ETDM_OUT2_CON3 (0x23ac) 810 + #define ETDM_OUT2_CON4 (0x23b0) 811 + #define ETDM_OUT2_CON5 (0x23b4) 812 + #define ETDM_OUT2_CON6 (0x23b8) 813 + #define ETDM_OUT2_CON7 (0x23bc) 814 + #define ETDM_OUT3_CON0 (0x23c0) 815 + #define ETDM_OUT3_CON1 (0x23c4) 816 + #define ETDM_OUT3_CON2 (0x23c8) 817 + #define ETDM_OUT3_CON3 (0x23cc) 818 + #define ETDM_OUT3_CON4 (0x23d0) 819 + #define ETDM_OUT3_CON5 (0x23d4) 820 + #define ETDM_OUT3_CON6 (0x23d8) 821 + #define ETDM_OUT3_CON7 (0x23dc) 822 + #define ETDM_OUT3_CON8 (0x23e0) 823 + #define ETDM_OUT1_CON8 (0x23e4) 824 + #define ETDM_OUT2_CON8 (0x23e8) 825 + #define GASRC_TIMING_CON0 (0x2414) 826 + #define GASRC_TIMING_CON1 (0x2418) 827 + #define GASRC_TIMING_CON2 (0x241c) 828 + #define GASRC_TIMING_CON3 (0x2420) 829 + #define GASRC_TIMING_CON4 (0x2424) 830 + #define GASRC_TIMING_CON5 (0x2428) 831 + #define A3_A4_TIMING_SEL0 (0x2440) 832 + #define A3_A4_TIMING_SEL1 (0x2444) 833 + #define A3_A4_TIMING_SEL2 (0x2448) 834 + #define A3_A4_TIMING_SEL3 (0x244c) 835 + #define A3_A4_TIMING_SEL4 (0x2450) 836 + #define A3_A4_TIMING_SEL5 (0x2454) 837 + #define A3_A4_TIMING_SEL6 (0x2458) 838 + #define ASYS_TOP_DEBUG (0x2500) 839 + #define AFE_DPTX_CON (0x2558) 840 + #define AFE_DPTX_MON (0x255c) 841 + #define AFE_ADDA_DL_SRC2_CON0 (0x2d00) 842 + #define AFE_ADDA_DL_SRC2_CON1 (0x2d04) 843 + #define AFE_ADDA_TOP_CON0 (0x2d0c) 844 + #define AFE_ADDA_UL_DL_CON0 (0x2d10) 845 + #define AFE_ADDA_SRC_DEBUG (0x2d14) 846 + #define AFE_ADDA_SRC_DEBUG_MON0 (0x2d18) 847 + #define AFE_ADDA_SRC_DEBUG_MON1 (0x2d20) 848 + #define AFE_ADDA_PREDIS_CON0 (0x2d24) 849 + #define AFE_ADDA_PREDIS_CON1 (0x2d28) 850 + #define AFE_ADDA_PREDIS_CON2 (0x2d2c) 851 + #define AFE_ADDA_PREDIS_CON3 (0x2d30) 852 + #define AFE_ADDA_DL_SDM_DCCOMP_CON (0x2d34) 853 + #define AFE_ADDA_DL_SDM_TEST (0x2d38) 854 + #define AFE_ADDA_DL_DC_COMP_CFG0 (0x2d3c) 855 + #define AFE_ADDA_DL_DC_COMP_CFG1 (0x2d40) 856 + #define AFE_ADDA_DL_SDM_FIFO_MON (0x2d44) 857 + #define AFE_ADDA_DL_SRC_LCH_MON (0x2d50) 858 + #define AFE_ADDA_DL_SRC_RCH_MON (0x2d54) 859 + #define AFE_ADDA_DL_SDM_OUT_MON (0x2d58) 860 + #define AFE_ADDA_DL_SDM_DITHER_CON (0x2d5c) 861 + #define AFE_ADDA_DL_SDM_AUTO_RESET_CON (0x2d60) 862 + #define AFE_ADDA_UL_SRC_CON0 (0x2e3c) 863 + #define AFE_ADDA_UL_SRC_CON1 (0x2e40) 864 + #define AFE_CONN0 (0x3000) 865 + #define AFE_CONN0_1 (0x3004) 866 + #define AFE_CONN0_2 (0x3008) 867 + #define AFE_CONN0_3 (0x300c) 868 + #define AFE_CONN0_4 (0x3010) 869 + #define AFE_CONN1 (0x3014) 870 + #define AFE_CONN1_1 (0x3018) 871 + #define AFE_CONN1_2 (0x301c) 872 + #define AFE_CONN1_3 (0x3020) 873 + #define AFE_CONN1_4 (0x3024) 874 + #define AFE_CONN2 (0x3028) 875 + #define AFE_CONN2_1 (0x302c) 876 + #define AFE_CONN2_2 (0x3030) 877 + #define AFE_CONN2_3 (0x3034) 878 + #define AFE_CONN2_4 (0x3038) 879 + #define AFE_CONN3 (0x303c) 880 + #define AFE_CONN3_1 (0x3040) 881 + #define AFE_CONN3_2 (0x3044) 882 + #define AFE_CONN3_3 (0x3048) 883 + #define AFE_CONN3_4 (0x304c) 884 + #define AFE_CONN4 (0x3050) 885 + #define AFE_CONN4_1 (0x3054) 886 + #define AFE_CONN4_2 (0x3058) 887 + #define AFE_CONN4_3 (0x305c) 888 + #define AFE_CONN4_4 (0x3060) 889 + #define AFE_CONN5 (0x3064) 890 + #define AFE_CONN5_1 (0x3068) 891 + #define AFE_CONN5_2 (0x306c) 892 + #define AFE_CONN5_3 (0x3070) 893 + #define AFE_CONN5_4 (0x3074) 894 + #define AFE_CONN6 (0x3078) 895 + #define AFE_CONN6_1 (0x307c) 896 + #define AFE_CONN6_2 (0x3080) 897 + #define AFE_CONN6_3 (0x3084) 898 + #define AFE_CONN6_4 (0x3088) 899 + #define AFE_CONN7 (0x308c) 900 + #define AFE_CONN7_1 (0x3090) 901 + #define AFE_CONN7_2 (0x3094) 902 + #define AFE_CONN7_3 (0x3098) 903 + #define AFE_CONN7_4 (0x309c) 904 + #define AFE_CONN8 (0x30a0) 905 + #define AFE_CONN8_1 (0x30a4) 906 + #define AFE_CONN8_2 (0x30a8) 907 + #define AFE_CONN8_3 (0x30ac) 908 + #define AFE_CONN8_4 (0x30b0) 909 + #define AFE_CONN9 (0x30b4) 910 + #define AFE_CONN9_1 (0x30b8) 911 + #define AFE_CONN9_2 (0x30bc) 912 + #define AFE_CONN9_3 (0x30c0) 913 + #define AFE_CONN9_4 (0x30c4) 914 + #define AFE_CONN10 (0x30c8) 915 + #define AFE_CONN10_1 (0x30cc) 916 + #define AFE_CONN10_2 (0x30d0) 917 + #define AFE_CONN10_3 (0x30d4) 918 + #define AFE_CONN10_4 (0x30d8) 919 + #define AFE_CONN11 (0x30dc) 920 + #define AFE_CONN11_1 (0x30e0) 921 + #define AFE_CONN11_2 (0x30e4) 922 + #define AFE_CONN11_3 (0x30e8) 923 + #define AFE_CONN11_4 (0x30ec) 924 + #define AFE_CONN12 (0x30f0) 925 + #define AFE_CONN12_1 (0x30f4) 926 + #define AFE_CONN12_2 (0x30f8) 927 + #define AFE_CONN12_3 (0x30fc) 928 + #define AFE_CONN12_4 (0x3100) 929 + #define AFE_CONN13 (0x3104) 930 + #define AFE_CONN13_1 (0x3108) 931 + #define AFE_CONN13_2 (0x310c) 932 + #define AFE_CONN13_3 (0x3110) 933 + #define AFE_CONN13_4 (0x3114) 934 + #define AFE_CONN14 (0x3118) 935 + #define AFE_CONN14_1 (0x311c) 936 + #define AFE_CONN14_2 (0x3120) 937 + #define AFE_CONN14_3 (0x3124) 938 + #define AFE_CONN14_4 (0x3128) 939 + #define AFE_CONN15 (0x312c) 940 + #define AFE_CONN15_1 (0x3130) 941 + #define AFE_CONN15_2 (0x3134) 942 + #define AFE_CONN15_3 (0x3138) 943 + #define AFE_CONN15_4 (0x313c) 944 + #define AFE_CONN16 (0x3140) 945 + #define AFE_CONN16_1 (0x3144) 946 + #define AFE_CONN16_2 (0x3148) 947 + #define AFE_CONN16_3 (0x314c) 948 + #define AFE_CONN16_4 (0x3150) 949 + #define AFE_CONN17 (0x3154) 950 + #define AFE_CONN17_1 (0x3158) 951 + #define AFE_CONN17_2 (0x315c) 952 + #define AFE_CONN17_3 (0x3160) 953 + #define AFE_CONN17_4 (0x3164) 954 + #define AFE_CONN18 (0x3168) 955 + #define AFE_CONN18_1 (0x316c) 956 + #define AFE_CONN18_2 (0x3170) 957 + #define AFE_CONN18_3 (0x3174) 958 + #define AFE_CONN18_4 (0x3178) 959 + #define AFE_CONN19 (0x317c) 960 + #define AFE_CONN19_1 (0x3180) 961 + #define AFE_CONN19_2 (0x3184) 962 + #define AFE_CONN19_3 (0x3188) 963 + #define AFE_CONN19_4 (0x318c) 964 + #define AFE_CONN20 (0x3190) 965 + #define AFE_CONN20_1 (0x3194) 966 + #define AFE_CONN20_2 (0x3198) 967 + #define AFE_CONN20_3 (0x319c) 968 + #define AFE_CONN20_4 (0x31a0) 969 + #define AFE_CONN21 (0x31a4) 970 + #define AFE_CONN21_1 (0x31a8) 971 + #define AFE_CONN21_2 (0x31ac) 972 + #define AFE_CONN21_3 (0x31b0) 973 + #define AFE_CONN21_4 (0x31b4) 974 + #define AFE_CONN22 (0x31b8) 975 + #define AFE_CONN22_1 (0x31bc) 976 + #define AFE_CONN22_2 (0x31c0) 977 + #define AFE_CONN22_3 (0x31c4) 978 + #define AFE_CONN22_4 (0x31c8) 979 + #define AFE_CONN23 (0x31cc) 980 + #define AFE_CONN23_1 (0x31d0) 981 + #define AFE_CONN23_2 (0x31d4) 982 + #define AFE_CONN23_3 (0x31d8) 983 + #define AFE_CONN23_4 (0x31dc) 984 + #define AFE_CONN24 (0x31e0) 985 + #define AFE_CONN24_1 (0x31e4) 986 + #define AFE_CONN24_2 (0x31e8) 987 + #define AFE_CONN24_3 (0x31ec) 988 + #define AFE_CONN24_4 (0x31f0) 989 + #define AFE_CONN25 (0x31f4) 990 + #define AFE_CONN25_1 (0x31f8) 991 + #define AFE_CONN25_2 (0x31fc) 992 + #define AFE_CONN25_3 (0x3200) 993 + #define AFE_CONN25_4 (0x3204) 994 + #define AFE_CONN26 (0x3208) 995 + #define AFE_CONN26_1 (0x320c) 996 + #define AFE_CONN26_2 (0x3210) 997 + #define AFE_CONN26_3 (0x3214) 998 + #define AFE_CONN26_4 (0x3218) 999 + #define AFE_CONN27 (0x321c) 1000 + #define AFE_CONN27_1 (0x3220) 1001 + #define AFE_CONN27_2 (0x3224) 1002 + #define AFE_CONN27_3 (0x3228) 1003 + #define AFE_CONN27_4 (0x322c) 1004 + #define AFE_CONN28 (0x3230) 1005 + #define AFE_CONN28_1 (0x3234) 1006 + #define AFE_CONN28_2 (0x3238) 1007 + #define AFE_CONN28_3 (0x323c) 1008 + #define AFE_CONN28_4 (0x3240) 1009 + #define AFE_CONN29 (0x3244) 1010 + #define AFE_CONN29_1 (0x3248) 1011 + #define AFE_CONN29_2 (0x324c) 1012 + #define AFE_CONN29_3 (0x3250) 1013 + #define AFE_CONN29_4 (0x3254) 1014 + #define AFE_CONN30 (0x3258) 1015 + #define AFE_CONN30_1 (0x325c) 1016 + #define AFE_CONN30_2 (0x3260) 1017 + #define AFE_CONN30_3 (0x3264) 1018 + #define AFE_CONN30_4 (0x3268) 1019 + #define AFE_CONN31 (0x326c) 1020 + #define AFE_CONN31_1 (0x3270) 1021 + #define AFE_CONN31_2 (0x3274) 1022 + #define AFE_CONN31_3 (0x3278) 1023 + #define AFE_CONN31_4 (0x327c) 1024 + #define AFE_CONN32 (0x3280) 1025 + #define AFE_CONN32_1 (0x3284) 1026 + #define AFE_CONN32_2 (0x3288) 1027 + #define AFE_CONN32_3 (0x328c) 1028 + #define AFE_CONN32_4 (0x3290) 1029 + #define AFE_CONN33 (0x3294) 1030 + #define AFE_CONN33_1 (0x3298) 1031 + #define AFE_CONN33_2 (0x329c) 1032 + #define AFE_CONN33_3 (0x32a0) 1033 + #define AFE_CONN33_4 (0x32a4) 1034 + #define AFE_CONN34 (0x32a8) 1035 + #define AFE_CONN34_1 (0x32ac) 1036 + #define AFE_CONN34_2 (0x32b0) 1037 + #define AFE_CONN34_3 (0x32b4) 1038 + #define AFE_CONN34_4 (0x32b8) 1039 + #define AFE_CONN35 (0x32bc) 1040 + #define AFE_CONN35_1 (0x32c0) 1041 + #define AFE_CONN35_2 (0x32c4) 1042 + #define AFE_CONN35_3 (0x32c8) 1043 + #define AFE_CONN35_4 (0x32cc) 1044 + #define AFE_CONN36 (0x32d0) 1045 + #define AFE_CONN36_1 (0x32d4) 1046 + #define AFE_CONN36_2 (0x32d8) 1047 + #define AFE_CONN36_3 (0x32dc) 1048 + #define AFE_CONN36_4 (0x32e0) 1049 + #define AFE_CONN37 (0x32e4) 1050 + #define AFE_CONN37_1 (0x32e8) 1051 + #define AFE_CONN37_2 (0x32ec) 1052 + #define AFE_CONN37_3 (0x32f0) 1053 + #define AFE_CONN37_4 (0x32f4) 1054 + #define AFE_CONN38 (0x32f8) 1055 + #define AFE_CONN38_1 (0x32fc) 1056 + #define AFE_CONN38_2 (0x3300) 1057 + #define AFE_CONN38_3 (0x3304) 1058 + #define AFE_CONN38_4 (0x3308) 1059 + #define AFE_CONN39 (0x330c) 1060 + #define AFE_CONN39_1 (0x3310) 1061 + #define AFE_CONN39_2 (0x3314) 1062 + #define AFE_CONN39_3 (0x3318) 1063 + #define AFE_CONN39_4 (0x331c) 1064 + #define AFE_CONN40 (0x3320) 1065 + #define AFE_CONN40_1 (0x3324) 1066 + #define AFE_CONN40_2 (0x3328) 1067 + #define AFE_CONN40_3 (0x332c) 1068 + #define AFE_CONN40_4 (0x3330) 1069 + #define AFE_CONN41 (0x3334) 1070 + #define AFE_CONN41_1 (0x3338) 1071 + #define AFE_CONN41_2 (0x333c) 1072 + #define AFE_CONN41_3 (0x3340) 1073 + #define AFE_CONN41_4 (0x3344) 1074 + #define AFE_CONN42 (0x3348) 1075 + #define AFE_CONN42_1 (0x334c) 1076 + #define AFE_CONN42_2 (0x3350) 1077 + #define AFE_CONN42_3 (0x3354) 1078 + #define AFE_CONN42_4 (0x3358) 1079 + #define AFE_CONN43 (0x335c) 1080 + #define AFE_CONN43_1 (0x3360) 1081 + #define AFE_CONN43_2 (0x3364) 1082 + #define AFE_CONN43_3 (0x3368) 1083 + #define AFE_CONN43_4 (0x336c) 1084 + #define AFE_CONN44 (0x3370) 1085 + #define AFE_CONN44_1 (0x3374) 1086 + #define AFE_CONN44_2 (0x3378) 1087 + #define AFE_CONN44_3 (0x337c) 1088 + #define AFE_CONN44_4 (0x3380) 1089 + #define AFE_CONN45 (0x3384) 1090 + #define AFE_CONN45_1 (0x3388) 1091 + #define AFE_CONN45_2 (0x338c) 1092 + #define AFE_CONN45_3 (0x3390) 1093 + #define AFE_CONN45_4 (0x3394) 1094 + #define AFE_CONN46 (0x3398) 1095 + #define AFE_CONN46_1 (0x339c) 1096 + #define AFE_CONN46_2 (0x33a0) 1097 + #define AFE_CONN46_3 (0x33a4) 1098 + #define AFE_CONN46_4 (0x33a8) 1099 + #define AFE_CONN47 (0x33ac) 1100 + #define AFE_CONN47_1 (0x33b0) 1101 + #define AFE_CONN47_2 (0x33b4) 1102 + #define AFE_CONN47_3 (0x33b8) 1103 + #define AFE_CONN47_4 (0x33bc) 1104 + #define AFE_CONN48 (0x33c0) 1105 + #define AFE_CONN48_1 (0x33c4) 1106 + #define AFE_CONN48_2 (0x33c8) 1107 + #define AFE_CONN48_3 (0x33cc) 1108 + #define AFE_CONN48_4 (0x33d0) 1109 + #define AFE_CONN49 (0x33d4) 1110 + #define AFE_CONN49_1 (0x33d8) 1111 + #define AFE_CONN49_2 (0x33dc) 1112 + #define AFE_CONN49_3 (0x33e0) 1113 + #define AFE_CONN49_4 (0x33e4) 1114 + #define AFE_CONN50 (0x33e8) 1115 + #define AFE_CONN50_1 (0x33ec) 1116 + #define AFE_CONN50_2 (0x33f0) 1117 + #define AFE_CONN50_3 (0x33f4) 1118 + #define AFE_CONN50_4 (0x33f8) 1119 + #define AFE_CONN51 (0x33fc) 1120 + #define AFE_CONN51_1 (0x3400) 1121 + #define AFE_CONN51_2 (0x3404) 1122 + #define AFE_CONN51_3 (0x3408) 1123 + #define AFE_CONN51_4 (0x340c) 1124 + #define AFE_CONN52 (0x3410) 1125 + #define AFE_CONN52_1 (0x3414) 1126 + #define AFE_CONN52_2 (0x3418) 1127 + #define AFE_CONN52_3 (0x341c) 1128 + #define AFE_CONN52_4 (0x3420) 1129 + #define AFE_CONN53 (0x3424) 1130 + #define AFE_CONN53_1 (0x3428) 1131 + #define AFE_CONN53_2 (0x342c) 1132 + #define AFE_CONN53_3 (0x3430) 1133 + #define AFE_CONN53_4 (0x3434) 1134 + #define AFE_CONN54 (0x3438) 1135 + #define AFE_CONN54_1 (0x343c) 1136 + #define AFE_CONN54_2 (0x3440) 1137 + #define AFE_CONN54_3 (0x3444) 1138 + #define AFE_CONN54_4 (0x3448) 1139 + #define AFE_CONN55 (0x344c) 1140 + #define AFE_CONN55_1 (0x3450) 1141 + #define AFE_CONN55_2 (0x3454) 1142 + #define AFE_CONN55_3 (0x3458) 1143 + #define AFE_CONN55_4 (0x345c) 1144 + #define AFE_CONN56 (0x3460) 1145 + #define AFE_CONN56_1 (0x3464) 1146 + #define AFE_CONN56_2 (0x3468) 1147 + #define AFE_CONN56_3 (0x346c) 1148 + #define AFE_CONN56_4 (0x3470) 1149 + #define AFE_CONN57 (0x3474) 1150 + #define AFE_CONN57_1 (0x3478) 1151 + #define AFE_CONN57_2 (0x347c) 1152 + #define AFE_CONN57_3 (0x3480) 1153 + #define AFE_CONN57_4 (0x3484) 1154 + #define AFE_CONN58 (0x3488) 1155 + #define AFE_CONN58_1 (0x348c) 1156 + #define AFE_CONN58_2 (0x3490) 1157 + #define AFE_CONN58_3 (0x3494) 1158 + #define AFE_CONN58_4 (0x3498) 1159 + #define AFE_CONN59 (0x349c) 1160 + #define AFE_CONN59_1 (0x34a0) 1161 + #define AFE_CONN59_2 (0x34a4) 1162 + #define AFE_CONN59_3 (0x34a8) 1163 + #define AFE_CONN59_4 (0x34ac) 1164 + #define AFE_CONN60 (0x34b0) 1165 + #define AFE_CONN60_1 (0x34b4) 1166 + #define AFE_CONN60_2 (0x34b8) 1167 + #define AFE_CONN60_3 (0x34bc) 1168 + #define AFE_CONN60_4 (0x34c0) 1169 + #define AFE_CONN61 (0x34c4) 1170 + #define AFE_CONN61_1 (0x34c8) 1171 + #define AFE_CONN61_2 (0x34cc) 1172 + #define AFE_CONN61_3 (0x34d0) 1173 + #define AFE_CONN61_4 (0x34d4) 1174 + #define AFE_CONN62 (0x34d8) 1175 + #define AFE_CONN62_1 (0x34dc) 1176 + #define AFE_CONN62_2 (0x34e0) 1177 + #define AFE_CONN62_3 (0x34e4) 1178 + #define AFE_CONN62_4 (0x34e8) 1179 + #define AFE_CONN63 (0x34ec) 1180 + #define AFE_CONN63_1 (0x34f0) 1181 + #define AFE_CONN63_2 (0x34f4) 1182 + #define AFE_CONN63_3 (0x34f8) 1183 + #define AFE_CONN63_4 (0x34fc) 1184 + #define AFE_CONN64 (0x3500) 1185 + #define AFE_CONN64_1 (0x3504) 1186 + #define AFE_CONN64_2 (0x3508) 1187 + #define AFE_CONN64_3 (0x350c) 1188 + #define AFE_CONN64_4 (0x3510) 1189 + #define AFE_CONN65 (0x3514) 1190 + #define AFE_CONN65_1 (0x3518) 1191 + #define AFE_CONN65_2 (0x351c) 1192 + #define AFE_CONN65_3 (0x3520) 1193 + #define AFE_CONN65_4 (0x3524) 1194 + #define AFE_CONN66 (0x3528) 1195 + #define AFE_CONN66_1 (0x352c) 1196 + #define AFE_CONN66_2 (0x3530) 1197 + #define AFE_CONN66_3 (0x3534) 1198 + #define AFE_CONN66_4 (0x3538) 1199 + #define AFE_CONN67 (0x353c) 1200 + #define AFE_CONN67_1 (0x3540) 1201 + #define AFE_CONN67_2 (0x3544) 1202 + #define AFE_CONN67_3 (0x3548) 1203 + #define AFE_CONN67_4 (0x354c) 1204 + #define AFE_CONN68 (0x3550) 1205 + #define AFE_CONN68_1 (0x3554) 1206 + #define AFE_CONN68_2 (0x3558) 1207 + #define AFE_CONN68_3 (0x355c) 1208 + #define AFE_CONN68_4 (0x3560) 1209 + #define AFE_CONN69 (0x3564) 1210 + #define AFE_CONN69_1 (0x3568) 1211 + #define AFE_CONN69_2 (0x356c) 1212 + #define AFE_CONN69_3 (0x3570) 1213 + #define AFE_CONN69_4 (0x3574) 1214 + #define AFE_CONN70 (0x3578) 1215 + #define AFE_CONN70_1 (0x357c) 1216 + #define AFE_CONN70_2 (0x3580) 1217 + #define AFE_CONN70_3 (0x3584) 1218 + #define AFE_CONN70_4 (0x3588) 1219 + #define AFE_CONN71 (0x358c) 1220 + #define AFE_CONN71_1 (0x3590) 1221 + #define AFE_CONN71_2 (0x3594) 1222 + #define AFE_CONN71_3 (0x3598) 1223 + #define AFE_CONN71_4 (0x359c) 1224 + #define AFE_CONN72 (0x35a0) 1225 + #define AFE_CONN72_1 (0x35a4) 1226 + #define AFE_CONN72_2 (0x35a8) 1227 + #define AFE_CONN72_3 (0x35ac) 1228 + #define AFE_CONN72_4 (0x35b0) 1229 + #define AFE_CONN73 (0x35b4) 1230 + #define AFE_CONN73_1 (0x35b8) 1231 + #define AFE_CONN73_2 (0x35bc) 1232 + #define AFE_CONN73_3 (0x35c0) 1233 + #define AFE_CONN73_4 (0x35c4) 1234 + #define AFE_CONN74 (0x35c8) 1235 + #define AFE_CONN74_1 (0x35cc) 1236 + #define AFE_CONN74_2 (0x35d0) 1237 + #define AFE_CONN74_3 (0x35d4) 1238 + #define AFE_CONN74_4 (0x35d8) 1239 + #define AFE_CONN75 (0x35dc) 1240 + #define AFE_CONN75_1 (0x35e0) 1241 + #define AFE_CONN75_2 (0x35e4) 1242 + #define AFE_CONN75_3 (0x35e8) 1243 + #define AFE_CONN75_4 (0x35ec) 1244 + #define AFE_CONN76 (0x35f0) 1245 + #define AFE_CONN76_1 (0x35f4) 1246 + #define AFE_CONN76_2 (0x35f8) 1247 + #define AFE_CONN76_3 (0x35fc) 1248 + #define AFE_CONN76_4 (0x3600) 1249 + #define AFE_CONN77 (0x3604) 1250 + #define AFE_CONN77_1 (0x3608) 1251 + #define AFE_CONN77_2 (0x360c) 1252 + #define AFE_CONN77_3 (0x3610) 1253 + #define AFE_CONN77_4 (0x3614) 1254 + #define AFE_CONN78 (0x3618) 1255 + #define AFE_CONN78_1 (0x361c) 1256 + #define AFE_CONN78_2 (0x3620) 1257 + #define AFE_CONN78_3 (0x3624) 1258 + #define AFE_CONN78_4 (0x3628) 1259 + #define AFE_CONN79 (0x362c) 1260 + #define AFE_CONN79_1 (0x3630) 1261 + #define AFE_CONN79_2 (0x3634) 1262 + #define AFE_CONN79_3 (0x3638) 1263 + #define AFE_CONN79_4 (0x363c) 1264 + #define AFE_CONN80 (0x3640) 1265 + #define AFE_CONN80_1 (0x3644) 1266 + #define AFE_CONN80_2 (0x3648) 1267 + #define AFE_CONN80_3 (0x364c) 1268 + #define AFE_CONN80_4 (0x3650) 1269 + #define AFE_CONN81 (0x3654) 1270 + #define AFE_CONN81_1 (0x3658) 1271 + #define AFE_CONN81_2 (0x365c) 1272 + #define AFE_CONN81_3 (0x3660) 1273 + #define AFE_CONN81_4 (0x3664) 1274 + #define AFE_CONN82 (0x3668) 1275 + #define AFE_CONN82_1 (0x366c) 1276 + #define AFE_CONN82_2 (0x3670) 1277 + #define AFE_CONN82_3 (0x3674) 1278 + #define AFE_CONN82_4 (0x3678) 1279 + #define AFE_CONN83 (0x367c) 1280 + #define AFE_CONN83_1 (0x3680) 1281 + #define AFE_CONN83_2 (0x3684) 1282 + #define AFE_CONN83_3 (0x3688) 1283 + #define AFE_CONN83_4 (0x368c) 1284 + #define AFE_CONN84 (0x3690) 1285 + #define AFE_CONN84_1 (0x3694) 1286 + #define AFE_CONN84_2 (0x3698) 1287 + #define AFE_CONN84_3 (0x369c) 1288 + #define AFE_CONN84_4 (0x36a0) 1289 + #define AFE_CONN85 (0x36a4) 1290 + #define AFE_CONN85_1 (0x36a8) 1291 + #define AFE_CONN85_2 (0x36ac) 1292 + #define AFE_CONN85_3 (0x36b0) 1293 + #define AFE_CONN85_4 (0x36b4) 1294 + #define AFE_CONN86 (0x36b8) 1295 + #define AFE_CONN86_1 (0x36bc) 1296 + #define AFE_CONN86_2 (0x36c0) 1297 + #define AFE_CONN86_3 (0x36c4) 1298 + #define AFE_CONN86_4 (0x36c8) 1299 + #define AFE_CONN87 (0x36cc) 1300 + #define AFE_CONN87_1 (0x36d0) 1301 + #define AFE_CONN87_2 (0x36d4) 1302 + #define AFE_CONN87_3 (0x36d8) 1303 + #define AFE_CONN87_4 (0x36dc) 1304 + #define AFE_CONN88 (0x36e0) 1305 + #define AFE_CONN88_1 (0x36e4) 1306 + #define AFE_CONN88_2 (0x36e8) 1307 + #define AFE_CONN88_3 (0x36ec) 1308 + #define AFE_CONN88_4 (0x36f0) 1309 + #define AFE_CONN89 (0x36f4) 1310 + #define AFE_CONN89_1 (0x36f8) 1311 + #define AFE_CONN89_2 (0x36fc) 1312 + #define AFE_CONN89_3 (0x3700) 1313 + #define AFE_CONN89_4 (0x3704) 1314 + #define AFE_CONN90 (0x3708) 1315 + #define AFE_CONN90_1 (0x370c) 1316 + #define AFE_CONN90_2 (0x3710) 1317 + #define AFE_CONN90_3 (0x3714) 1318 + #define AFE_CONN90_4 (0x3718) 1319 + #define AFE_CONN91 (0x371c) 1320 + #define AFE_CONN91_1 (0x3720) 1321 + #define AFE_CONN91_2 (0x3724) 1322 + #define AFE_CONN91_3 (0x3728) 1323 + #define AFE_CONN91_4 (0x372c) 1324 + #define AFE_CONN92 (0x3730) 1325 + #define AFE_CONN92_1 (0x3734) 1326 + #define AFE_CONN92_2 (0x3738) 1327 + #define AFE_CONN92_3 (0x373c) 1328 + #define AFE_CONN92_4 (0x3740) 1329 + #define AFE_CONN93 (0x3744) 1330 + #define AFE_CONN93_1 (0x3748) 1331 + #define AFE_CONN93_2 (0x374c) 1332 + #define AFE_CONN93_3 (0x3750) 1333 + #define AFE_CONN93_4 (0x3754) 1334 + #define AFE_CONN94 (0x3758) 1335 + #define AFE_CONN94_1 (0x375c) 1336 + #define AFE_CONN94_2 (0x3760) 1337 + #define AFE_CONN94_3 (0x3764) 1338 + #define AFE_CONN94_4 (0x3768) 1339 + #define AFE_CONN95 (0x376c) 1340 + #define AFE_CONN95_1 (0x3770) 1341 + #define AFE_CONN95_2 (0x3774) 1342 + #define AFE_CONN95_3 (0x3778) 1343 + #define AFE_CONN95_4 (0x377c) 1344 + #define AFE_CONN96 (0x3780) 1345 + #define AFE_CONN96_1 (0x3784) 1346 + #define AFE_CONN96_2 (0x3788) 1347 + #define AFE_CONN96_3 (0x378c) 1348 + #define AFE_CONN96_4 (0x3790) 1349 + #define AFE_CONN97 (0x3794) 1350 + #define AFE_CONN97_1 (0x3798) 1351 + #define AFE_CONN97_2 (0x379c) 1352 + #define AFE_CONN97_3 (0x37a0) 1353 + #define AFE_CONN97_4 (0x37a4) 1354 + #define AFE_CONN98 (0x37a8) 1355 + #define AFE_CONN98_1 (0x37ac) 1356 + #define AFE_CONN98_2 (0x37b0) 1357 + #define AFE_CONN98_3 (0x37b4) 1358 + #define AFE_CONN98_4 (0x37b8) 1359 + #define AFE_CONN99 (0x37bc) 1360 + #define AFE_CONN99_1 (0x37c0) 1361 + #define AFE_CONN99_2 (0x37c4) 1362 + #define AFE_CONN99_3 (0x37c8) 1363 + #define AFE_CONN99_4 (0x37cc) 1364 + #define AFE_CONN100 (0x37d0) 1365 + #define AFE_CONN100_1 (0x37d4) 1366 + #define AFE_CONN100_2 (0x37d8) 1367 + #define AFE_CONN100_3 (0x37dc) 1368 + #define AFE_CONN100_4 (0x37e0) 1369 + #define AFE_CONN101 (0x37e4) 1370 + #define AFE_CONN101_1 (0x37e8) 1371 + #define AFE_CONN101_2 (0x37ec) 1372 + #define AFE_CONN101_3 (0x37f0) 1373 + #define AFE_CONN101_4 (0x37f4) 1374 + #define AFE_CONN102 (0x37f8) 1375 + #define AFE_CONN102_1 (0x37fc) 1376 + #define AFE_CONN102_2 (0x3800) 1377 + #define AFE_CONN102_3 (0x3804) 1378 + #define AFE_CONN102_4 (0x3808) 1379 + #define AFE_CONN103 (0x380c) 1380 + #define AFE_CONN103_1 (0x3810) 1381 + #define AFE_CONN103_2 (0x3814) 1382 + #define AFE_CONN103_3 (0x3818) 1383 + #define AFE_CONN103_4 (0x381c) 1384 + #define AFE_CONN104 (0x3820) 1385 + #define AFE_CONN104_1 (0x3824) 1386 + #define AFE_CONN104_2 (0x3828) 1387 + #define AFE_CONN104_3 (0x382c) 1388 + #define AFE_CONN104_4 (0x3830) 1389 + #define AFE_CONN105 (0x3834) 1390 + #define AFE_CONN105_1 (0x3838) 1391 + #define AFE_CONN105_2 (0x383c) 1392 + #define AFE_CONN105_3 (0x3840) 1393 + #define AFE_CONN105_4 (0x3844) 1394 + #define AFE_CONN106 (0x3848) 1395 + #define AFE_CONN106_1 (0x384c) 1396 + #define AFE_CONN106_2 (0x3850) 1397 + #define AFE_CONN106_3 (0x3854) 1398 + #define AFE_CONN106_4 (0x3858) 1399 + #define AFE_CONN107 (0x385c) 1400 + #define AFE_CONN107_1 (0x3860) 1401 + #define AFE_CONN107_2 (0x3864) 1402 + #define AFE_CONN107_3 (0x3868) 1403 + #define AFE_CONN107_4 (0x386c) 1404 + #define AFE_CONN108 (0x3870) 1405 + #define AFE_CONN108_1 (0x3874) 1406 + #define AFE_CONN108_2 (0x3878) 1407 + #define AFE_CONN108_3 (0x387c) 1408 + #define AFE_CONN108_4 (0x3880) 1409 + #define AFE_CONN109 (0x3884) 1410 + #define AFE_CONN109_1 (0x3888) 1411 + #define AFE_CONN109_2 (0x388c) 1412 + #define AFE_CONN109_3 (0x3890) 1413 + #define AFE_CONN109_4 (0x3894) 1414 + #define AFE_CONN110 (0x3898) 1415 + #define AFE_CONN110_1 (0x389c) 1416 + #define AFE_CONN110_2 (0x38a0) 1417 + #define AFE_CONN110_3 (0x38a4) 1418 + #define AFE_CONN110_4 (0x38a8) 1419 + #define AFE_CONN111 (0x38ac) 1420 + #define AFE_CONN111_1 (0x38b0) 1421 + #define AFE_CONN111_2 (0x38b4) 1422 + #define AFE_CONN111_3 (0x38b8) 1423 + #define AFE_CONN111_4 (0x38bc) 1424 + #define AFE_CONN112 (0x38c0) 1425 + #define AFE_CONN112_1 (0x38c4) 1426 + #define AFE_CONN112_2 (0x38c8) 1427 + #define AFE_CONN112_3 (0x38cc) 1428 + #define AFE_CONN112_4 (0x38d0) 1429 + #define AFE_CONN113 (0x38d4) 1430 + #define AFE_CONN113_1 (0x38d8) 1431 + #define AFE_CONN113_2 (0x38dc) 1432 + #define AFE_CONN113_3 (0x38e0) 1433 + #define AFE_CONN113_4 (0x38e4) 1434 + #define AFE_CONN114 (0x38e8) 1435 + #define AFE_CONN114_1 (0x38ec) 1436 + #define AFE_CONN114_2 (0x38f0) 1437 + #define AFE_CONN114_3 (0x38f4) 1438 + #define AFE_CONN114_4 (0x38f8) 1439 + #define AFE_CONN115 (0x38fc) 1440 + #define AFE_CONN115_1 (0x3900) 1441 + #define AFE_CONN115_2 (0x3904) 1442 + #define AFE_CONN115_3 (0x3908) 1443 + #define AFE_CONN115_4 (0x390c) 1444 + #define AFE_CONN116 (0x3910) 1445 + #define AFE_CONN116_1 (0x3914) 1446 + #define AFE_CONN116_2 (0x3918) 1447 + #define AFE_CONN116_3 (0x391c) 1448 + #define AFE_CONN116_4 (0x3920) 1449 + #define AFE_CONN117 (0x3924) 1450 + #define AFE_CONN117_1 (0x3928) 1451 + #define AFE_CONN117_2 (0x392c) 1452 + #define AFE_CONN117_3 (0x3930) 1453 + #define AFE_CONN117_4 (0x3934) 1454 + #define AFE_CONN118 (0x3938) 1455 + #define AFE_CONN118_1 (0x393c) 1456 + #define AFE_CONN118_2 (0x3940) 1457 + #define AFE_CONN118_3 (0x3944) 1458 + #define AFE_CONN118_4 (0x3948) 1459 + #define AFE_CONN119 (0x394c) 1460 + #define AFE_CONN119_1 (0x3950) 1461 + #define AFE_CONN119_2 (0x3954) 1462 + #define AFE_CONN119_3 (0x3958) 1463 + #define AFE_CONN119_4 (0x395c) 1464 + #define AFE_CONN120 (0x3960) 1465 + #define AFE_CONN120_1 (0x3964) 1466 + #define AFE_CONN120_2 (0x3968) 1467 + #define AFE_CONN120_3 (0x396c) 1468 + #define AFE_CONN120_4 (0x3970) 1469 + #define AFE_CONN121 (0x3974) 1470 + #define AFE_CONN121_1 (0x3978) 1471 + #define AFE_CONN121_2 (0x397c) 1472 + #define AFE_CONN121_3 (0x3980) 1473 + #define AFE_CONN121_4 (0x3984) 1474 + #define AFE_CONN122 (0x3988) 1475 + #define AFE_CONN122_1 (0x398c) 1476 + #define AFE_CONN122_2 (0x3990) 1477 + #define AFE_CONN122_3 (0x3994) 1478 + #define AFE_CONN122_4 (0x3998) 1479 + #define AFE_CONN123 (0x399c) 1480 + #define AFE_CONN123_1 (0x39a0) 1481 + #define AFE_CONN123_2 (0x39a4) 1482 + #define AFE_CONN123_3 (0x39a8) 1483 + #define AFE_CONN123_4 (0x39ac) 1484 + #define AFE_CONN124 (0x39b0) 1485 + #define AFE_CONN124_1 (0x39b4) 1486 + #define AFE_CONN124_2 (0x39b8) 1487 + #define AFE_CONN124_3 (0x39bc) 1488 + #define AFE_CONN124_4 (0x39c0) 1489 + #define AFE_CONN125 (0x39c4) 1490 + #define AFE_CONN125_1 (0x39c8) 1491 + #define AFE_CONN125_2 (0x39cc) 1492 + #define AFE_CONN125_3 (0x39d0) 1493 + #define AFE_CONN125_4 (0x39d4) 1494 + #define AFE_CONN126 (0x39d8) 1495 + #define AFE_CONN126_1 (0x39dc) 1496 + #define AFE_CONN126_2 (0x39e0) 1497 + #define AFE_CONN126_3 (0x39e4) 1498 + #define AFE_CONN126_4 (0x39e8) 1499 + #define AFE_CONN127 (0x39ec) 1500 + #define AFE_CONN127_1 (0x39f0) 1501 + #define AFE_CONN127_2 (0x39f4) 1502 + #define AFE_CONN127_3 (0x39f8) 1503 + #define AFE_CONN127_4 (0x39fc) 1504 + #define AFE_CONN128 (0x3a00) 1505 + #define AFE_CONN128_1 (0x3a04) 1506 + #define AFE_CONN128_2 (0x3a08) 1507 + #define AFE_CONN128_3 (0x3a0c) 1508 + #define AFE_CONN128_4 (0x3a10) 1509 + #define AFE_CONN129 (0x3a14) 1510 + #define AFE_CONN129_1 (0x3a18) 1511 + #define AFE_CONN129_2 (0x3a1c) 1512 + #define AFE_CONN129_3 (0x3a20) 1513 + #define AFE_CONN129_4 (0x3a24) 1514 + #define AFE_CONN130 (0x3a28) 1515 + #define AFE_CONN130_1 (0x3a2c) 1516 + #define AFE_CONN130_2 (0x3a30) 1517 + #define AFE_CONN130_3 (0x3a34) 1518 + #define AFE_CONN130_4 (0x3a38) 1519 + #define AFE_CONN131 (0x3a3c) 1520 + #define AFE_CONN131_1 (0x3a40) 1521 + #define AFE_CONN131_2 (0x3a44) 1522 + #define AFE_CONN131_3 (0x3a48) 1523 + #define AFE_CONN131_4 (0x3a4c) 1524 + #define AFE_CONN132 (0x3a50) 1525 + #define AFE_CONN132_1 (0x3a54) 1526 + #define AFE_CONN132_2 (0x3a58) 1527 + #define AFE_CONN132_3 (0x3a5c) 1528 + #define AFE_CONN132_4 (0x3a60) 1529 + #define AFE_CONN133 (0x3a64) 1530 + #define AFE_CONN133_1 (0x3a68) 1531 + #define AFE_CONN133_2 (0x3a6c) 1532 + #define AFE_CONN133_3 (0x3a70) 1533 + #define AFE_CONN133_4 (0x3a74) 1534 + #define AFE_CONN134 (0x3a78) 1535 + #define AFE_CONN134_1 (0x3a7c) 1536 + #define AFE_CONN134_2 (0x3a80) 1537 + #define AFE_CONN134_3 (0x3a84) 1538 + #define AFE_CONN134_4 (0x3a88) 1539 + #define AFE_CONN135 (0x3a8c) 1540 + #define AFE_CONN135_1 (0x3a90) 1541 + #define AFE_CONN135_2 (0x3a94) 1542 + #define AFE_CONN135_3 (0x3a98) 1543 + #define AFE_CONN135_4 (0x3a9c) 1544 + #define AFE_CONN136 (0x3aa0) 1545 + #define AFE_CONN136_1 (0x3aa4) 1546 + #define AFE_CONN136_2 (0x3aa8) 1547 + #define AFE_CONN136_3 (0x3aac) 1548 + #define AFE_CONN136_4 (0x3ab0) 1549 + #define AFE_CONN137 (0x3ab4) 1550 + #define AFE_CONN137_1 (0x3ab8) 1551 + #define AFE_CONN137_2 (0x3abc) 1552 + #define AFE_CONN137_3 (0x3ac0) 1553 + #define AFE_CONN137_4 (0x3ac4) 1554 + #define AFE_CONN138 (0x3ac8) 1555 + #define AFE_CONN138_1 (0x3acc) 1556 + #define AFE_CONN138_2 (0x3ad0) 1557 + #define AFE_CONN138_3 (0x3ad4) 1558 + #define AFE_CONN138_4 (0x3ad8) 1559 + #define AFE_CONN139 (0x3adc) 1560 + #define AFE_CONN139_1 (0x3ae0) 1561 + #define AFE_CONN139_2 (0x3ae4) 1562 + #define AFE_CONN139_3 (0x3ae8) 1563 + #define AFE_CONN139_4 (0x3aec) 1564 + #define AFE_CONN_RS (0x3af0) 1565 + #define AFE_CONN_RS_1 (0x3af4) 1566 + #define AFE_CONN_RS_2 (0x3af8) 1567 + #define AFE_CONN_RS_3 (0x3afc) 1568 + #define AFE_CONN_RS_4 (0x3b00) 1569 + #define AFE_CONN_16BIT (0x3b04) 1570 + #define AFE_CONN_16BIT_1 (0x3b08) 1571 + #define AFE_CONN_16BIT_2 (0x3b0c) 1572 + #define AFE_CONN_16BIT_3 (0x3b10) 1573 + #define AFE_CONN_16BIT_4 (0x3b14) 1574 + #define AFE_CONN_24BIT (0x3b18) 1575 + #define AFE_CONN_24BIT_1 (0x3b1c) 1576 + #define AFE_CONN_24BIT_2 (0x3b20) 1577 + #define AFE_CONN_24BIT_3 (0x3b24) 1578 + #define AFE_CONN_24BIT_4 (0x3b28) 1579 + #define AFE_CONN_DI (0x3b2c) 1580 + #define AFE_CONN_DI_1 (0x3b30) 1581 + #define AFE_CONN_DI_2 (0x3b34) 1582 + #define AFE_CONN_DI_3 (0x3b38) 1583 + #define AFE_CONN_DI_4 (0x3b3c) 1584 + #define AFE_CONN176 (0x3ea0) 1585 + #define AFE_CONN176_1 (0x3ea4) 1586 + #define AFE_CONN176_2 (0x3ea8) 1587 + #define AFE_CONN176_3 (0x3eac) 1588 + #define AFE_CONN176_4 (0x3eb0) 1589 + #define AFE_CONN176_5 (0x3eb4) 1590 + #define AFE_CONN177 (0x3eb8) 1591 + #define AFE_CONN177_1 (0x3ebc) 1592 + #define AFE_CONN177_2 (0x3ec0) 1593 + #define AFE_CONN177_3 (0x3ec4) 1594 + #define AFE_CONN177_4 (0x3ec8) 1595 + #define AFE_CONN177_5 (0x3ecc) 1596 + #define AFE_CONN182 (0x3f30) 1597 + #define AFE_CONN182_1 (0x3f34) 1598 + #define AFE_CONN182_2 (0x3f38) 1599 + #define AFE_CONN182_3 (0x3f3c) 1600 + #define AFE_CONN182_4 (0x3f40) 1601 + #define AFE_CONN182_5 (0x3f44) 1602 + #define AFE_CONN183 (0x3f48) 1603 + #define AFE_CONN183_1 (0x3f4c) 1604 + #define AFE_CONN183_2 (0x3f50) 1605 + #define AFE_CONN183_3 (0x3f54) 1606 + #define AFE_CONN183_4 (0x3f58) 1607 + #define AFE_CONN183_5 (0x3f5c) 1608 + #define AFE_SECURE_MASK_CONN0 (0x4000) 1609 + #define AFE_SECURE_MASK_CONN0_1 (0x4004) 1610 + #define AFE_SECURE_MASK_CONN0_2 (0x4008) 1611 + #define AFE_SECURE_MASK_CONN0_3 (0x400c) 1612 + #define AFE_SECURE_MASK_CONN0_4 (0x4010) 1613 + #define AFE_SECURE_MASK_CONN1 (0x4014) 1614 + #define AFE_SECURE_MASK_CONN1_1 (0x4018) 1615 + #define AFE_SECURE_MASK_CONN1_2 (0x401c) 1616 + #define AFE_SECURE_MASK_CONN1_3 (0x4020) 1617 + #define AFE_SECURE_MASK_CONN1_4 (0x4024) 1618 + #define AFE_SECURE_MASK_CONN2 (0x4028) 1619 + #define AFE_SECURE_MASK_CONN2_1 (0x402c) 1620 + #define AFE_SECURE_MASK_CONN2_2 (0x4030) 1621 + #define AFE_SECURE_MASK_CONN2_3 (0x4034) 1622 + #define AFE_SECURE_MASK_CONN2_4 (0x4038) 1623 + #define AFE_SECURE_MASK_CONN3 (0x403c) 1624 + #define AFE_SECURE_MASK_CONN3_1 (0x4040) 1625 + #define AFE_SECURE_MASK_CONN3_2 (0x4044) 1626 + #define AFE_SECURE_MASK_CONN3_3 (0x4048) 1627 + #define AFE_SECURE_MASK_CONN3_4 (0x404c) 1628 + #define AFE_SECURE_MASK_CONN4 (0x4050) 1629 + #define AFE_SECURE_MASK_CONN4_1 (0x4054) 1630 + #define AFE_SECURE_MASK_CONN4_2 (0x4058) 1631 + #define AFE_SECURE_MASK_CONN4_3 (0x405c) 1632 + #define AFE_SECURE_MASK_CONN4_4 (0x4060) 1633 + #define AFE_SECURE_MASK_CONN5 (0x4064) 1634 + #define AFE_SECURE_MASK_CONN5_1 (0x4068) 1635 + #define AFE_SECURE_MASK_CONN5_2 (0x406c) 1636 + #define AFE_SECURE_MASK_CONN5_3 (0x4070) 1637 + #define AFE_SECURE_MASK_CONN5_4 (0x4074) 1638 + #define AFE_SECURE_MASK_CONN6 (0x4078) 1639 + #define AFE_SECURE_MASK_CONN6_1 (0x407c) 1640 + #define AFE_SECURE_MASK_CONN6_2 (0x4080) 1641 + #define AFE_SECURE_MASK_CONN6_3 (0x4084) 1642 + #define AFE_SECURE_MASK_CONN6_4 (0x4088) 1643 + #define AFE_SECURE_MASK_CONN7 (0x408c) 1644 + #define AFE_SECURE_MASK_CONN7_1 (0x4090) 1645 + #define AFE_SECURE_MASK_CONN7_2 (0x4094) 1646 + #define AFE_SECURE_MASK_CONN7_3 (0x4098) 1647 + #define AFE_SECURE_MASK_CONN7_4 (0x409c) 1648 + #define AFE_SECURE_MASK_CONN8 (0x40a0) 1649 + #define AFE_SECURE_MASK_CONN8_1 (0x40a4) 1650 + #define AFE_SECURE_MASK_CONN8_2 (0x40a8) 1651 + #define AFE_SECURE_MASK_CONN8_3 (0x40ac) 1652 + #define AFE_SECURE_MASK_CONN8_4 (0x40b0) 1653 + #define AFE_SECURE_MASK_CONN9 (0x40b4) 1654 + #define AFE_SECURE_MASK_CONN9_1 (0x40b8) 1655 + #define AFE_SECURE_MASK_CONN9_2 (0x40bc) 1656 + #define AFE_SECURE_MASK_CONN9_3 (0x40c0) 1657 + #define AFE_SECURE_MASK_CONN9_4 (0x40c4) 1658 + #define AFE_SECURE_MASK_CONN10 (0x40c8) 1659 + #define AFE_SECURE_MASK_CONN10_1 (0x40cc) 1660 + #define AFE_SECURE_MASK_CONN10_2 (0x40d0) 1661 + #define AFE_SECURE_MASK_CONN10_3 (0x40d4) 1662 + #define AFE_SECURE_MASK_CONN10_4 (0x40d8) 1663 + #define AFE_SECURE_MASK_CONN11 (0x40dc) 1664 + #define AFE_SECURE_MASK_CONN11_1 (0x40e0) 1665 + #define AFE_SECURE_MASK_CONN11_2 (0x40e4) 1666 + #define AFE_SECURE_MASK_CONN11_3 (0x40e8) 1667 + #define AFE_SECURE_MASK_CONN11_4 (0x40ec) 1668 + #define AFE_SECURE_MASK_CONN12 (0x40f0) 1669 + #define AFE_SECURE_MASK_CONN12_1 (0x40f4) 1670 + #define AFE_SECURE_MASK_CONN12_2 (0x40f8) 1671 + #define AFE_SECURE_MASK_CONN12_3 (0x40fc) 1672 + #define AFE_SECURE_MASK_CONN12_4 (0x4100) 1673 + #define AFE_SECURE_MASK_CONN13 (0x4104) 1674 + #define AFE_SECURE_MASK_CONN13_1 (0x4108) 1675 + #define AFE_SECURE_MASK_CONN13_2 (0x410c) 1676 + #define AFE_SECURE_MASK_CONN13_3 (0x4110) 1677 + #define AFE_SECURE_MASK_CONN13_4 (0x4114) 1678 + #define AFE_SECURE_MASK_CONN14 (0x4118) 1679 + #define AFE_SECURE_MASK_CONN14_1 (0x411c) 1680 + #define AFE_SECURE_MASK_CONN14_2 (0x4120) 1681 + #define AFE_SECURE_MASK_CONN14_3 (0x4124) 1682 + #define AFE_SECURE_MASK_CONN14_4 (0x4128) 1683 + #define AFE_SECURE_MASK_CONN15 (0x412c) 1684 + #define AFE_SECURE_MASK_CONN15_1 (0x4130) 1685 + #define AFE_SECURE_MASK_CONN15_2 (0x4134) 1686 + #define AFE_SECURE_MASK_CONN15_3 (0x4138) 1687 + #define AFE_SECURE_MASK_CONN15_4 (0x413c) 1688 + #define AFE_SECURE_MASK_CONN16 (0x4140) 1689 + #define AFE_SECURE_MASK_CONN16_1 (0x4144) 1690 + #define AFE_SECURE_MASK_CONN16_2 (0x4148) 1691 + #define AFE_SECURE_MASK_CONN16_3 (0x414c) 1692 + #define AFE_SECURE_MASK_CONN16_4 (0x4150) 1693 + #define AFE_SECURE_MASK_CONN17 (0x4154) 1694 + #define AFE_SECURE_MASK_CONN17_1 (0x4158) 1695 + #define AFE_SECURE_MASK_CONN17_2 (0x415c) 1696 + #define AFE_SECURE_MASK_CONN17_3 (0x4160) 1697 + #define AFE_SECURE_MASK_CONN17_4 (0x4164) 1698 + #define AFE_SECURE_MASK_CONN18 (0x4168) 1699 + #define AFE_SECURE_MASK_CONN18_1 (0x416c) 1700 + #define AFE_SECURE_MASK_CONN18_2 (0x4170) 1701 + #define AFE_SECURE_MASK_CONN18_3 (0x4174) 1702 + #define AFE_SECURE_MASK_CONN18_4 (0x4178) 1703 + #define AFE_SECURE_MASK_CONN19 (0x417c) 1704 + #define AFE_SECURE_MASK_CONN19_1 (0x4180) 1705 + #define AFE_SECURE_MASK_CONN19_2 (0x4184) 1706 + #define AFE_SECURE_MASK_CONN19_3 (0x4188) 1707 + #define AFE_SECURE_MASK_CONN19_4 (0x418c) 1708 + #define AFE_SECURE_MASK_CONN20 (0x4190) 1709 + #define AFE_SECURE_MASK_CONN20_1 (0x4194) 1710 + #define AFE_SECURE_MASK_CONN20_2 (0x4198) 1711 + #define AFE_SECURE_MASK_CONN20_3 (0x419c) 1712 + #define AFE_SECURE_MASK_CONN20_4 (0x41a0) 1713 + #define AFE_SECURE_MASK_CONN21 (0x41a4) 1714 + #define AFE_SECURE_MASK_CONN21_1 (0x41a8) 1715 + #define AFE_SECURE_MASK_CONN21_2 (0x41ac) 1716 + #define AFE_SECURE_MASK_CONN21_3 (0x41b0) 1717 + #define AFE_SECURE_MASK_CONN21_4 (0x41b4) 1718 + #define AFE_SECURE_MASK_CONN22 (0x41b8) 1719 + #define AFE_SECURE_MASK_CONN22_1 (0x41bc) 1720 + #define AFE_SECURE_MASK_CONN22_2 (0x41c0) 1721 + #define AFE_SECURE_MASK_CONN22_3 (0x41c4) 1722 + #define AFE_SECURE_MASK_CONN22_4 (0x41c8) 1723 + #define AFE_SECURE_MASK_CONN23 (0x41cc) 1724 + #define AFE_SECURE_MASK_CONN23_1 (0x41d0) 1725 + #define AFE_SECURE_MASK_CONN23_2 (0x41d4) 1726 + #define AFE_SECURE_MASK_CONN23_3 (0x41d8) 1727 + #define AFE_SECURE_MASK_CONN23_4 (0x41dc) 1728 + #define AFE_SECURE_MASK_CONN24 (0x41e0) 1729 + #define AFE_SECURE_MASK_CONN24_1 (0x41e4) 1730 + #define AFE_SECURE_MASK_CONN24_2 (0x41e8) 1731 + #define AFE_SECURE_MASK_CONN24_3 (0x41ec) 1732 + #define AFE_SECURE_MASK_CONN24_4 (0x41f0) 1733 + #define AFE_SECURE_MASK_CONN25 (0x41f4) 1734 + #define AFE_SECURE_MASK_CONN25_1 (0x41f8) 1735 + #define AFE_SECURE_MASK_CONN25_2 (0x41fc) 1736 + #define AFE_SECURE_MASK_CONN25_3 (0x4200) 1737 + #define AFE_SECURE_MASK_CONN25_4 (0x4204) 1738 + #define AFE_SECURE_MASK_CONN26 (0x4208) 1739 + #define AFE_SECURE_MASK_CONN26_1 (0x420c) 1740 + #define AFE_SECURE_MASK_CONN26_2 (0x4210) 1741 + #define AFE_SECURE_MASK_CONN26_3 (0x4214) 1742 + #define AFE_SECURE_MASK_CONN26_4 (0x4218) 1743 + #define AFE_SECURE_MASK_CONN27 (0x421c) 1744 + #define AFE_SECURE_MASK_CONN27_1 (0x4220) 1745 + #define AFE_SECURE_MASK_CONN27_2 (0x4224) 1746 + #define AFE_SECURE_MASK_CONN27_3 (0x4228) 1747 + #define AFE_SECURE_MASK_CONN27_4 (0x422c) 1748 + #define AFE_SECURE_MASK_CONN28 (0x4230) 1749 + #define AFE_SECURE_MASK_CONN28_1 (0x4234) 1750 + #define AFE_SECURE_MASK_CONN28_2 (0x4238) 1751 + #define AFE_SECURE_MASK_CONN28_3 (0x423c) 1752 + #define AFE_SECURE_MASK_CONN28_4 (0x4240) 1753 + #define AFE_SECURE_MASK_CONN29 (0x4244) 1754 + #define AFE_SECURE_MASK_CONN29_1 (0x4248) 1755 + #define AFE_SECURE_MASK_CONN29_2 (0x424c) 1756 + #define AFE_SECURE_MASK_CONN29_3 (0x4250) 1757 + #define AFE_SECURE_MASK_CONN29_4 (0x4254) 1758 + #define AFE_SECURE_MASK_CONN30 (0x4258) 1759 + #define AFE_SECURE_MASK_CONN30_1 (0x425c) 1760 + #define AFE_SECURE_MASK_CONN30_2 (0x4260) 1761 + #define AFE_SECURE_MASK_CONN30_3 (0x4264) 1762 + #define AFE_SECURE_MASK_CONN30_4 (0x4268) 1763 + #define AFE_SECURE_MASK_CONN31 (0x426c) 1764 + #define AFE_SECURE_MASK_CONN31_1 (0x4270) 1765 + #define AFE_SECURE_MASK_CONN31_2 (0x4274) 1766 + #define AFE_SECURE_MASK_CONN31_3 (0x4278) 1767 + #define AFE_SECURE_MASK_CONN31_4 (0x427c) 1768 + #define AFE_SECURE_MASK_CONN32 (0x4280) 1769 + #define AFE_SECURE_MASK_CONN32_1 (0x4284) 1770 + #define AFE_SECURE_MASK_CONN32_2 (0x4288) 1771 + #define AFE_SECURE_MASK_CONN32_3 (0x428c) 1772 + #define AFE_SECURE_MASK_CONN32_4 (0x4290) 1773 + #define AFE_SECURE_MASK_CONN33 (0x4294) 1774 + #define AFE_SECURE_MASK_CONN33_1 (0x4298) 1775 + #define AFE_SECURE_MASK_CONN33_2 (0x429c) 1776 + #define AFE_SECURE_MASK_CONN33_3 (0x42a0) 1777 + #define AFE_SECURE_MASK_CONN33_4 (0x42a4) 1778 + #define AFE_SECURE_MASK_CONN34 (0x42a8) 1779 + #define AFE_SECURE_MASK_CONN34_1 (0x42ac) 1780 + #define AFE_SECURE_MASK_CONN34_2 (0x42b0) 1781 + #define AFE_SECURE_MASK_CONN34_3 (0x42b4) 1782 + #define AFE_SECURE_MASK_CONN34_4 (0x42b8) 1783 + #define AFE_SECURE_MASK_CONN35 (0x42bc) 1784 + #define AFE_SECURE_MASK_CONN35_1 (0x42c0) 1785 + #define AFE_SECURE_MASK_CONN35_2 (0x42c4) 1786 + #define AFE_SECURE_MASK_CONN35_3 (0x42c8) 1787 + #define AFE_SECURE_MASK_CONN35_4 (0x42cc) 1788 + #define AFE_SECURE_MASK_CONN36 (0x42d0) 1789 + #define AFE_SECURE_MASK_CONN36_1 (0x42d4) 1790 + #define AFE_SECURE_MASK_CONN36_2 (0x42d8) 1791 + #define AFE_SECURE_MASK_CONN36_3 (0x42dc) 1792 + #define AFE_SECURE_MASK_CONN36_4 (0x42e0) 1793 + #define AFE_SECURE_MASK_CONN37 (0x42e4) 1794 + #define AFE_SECURE_MASK_CONN37_1 (0x42e8) 1795 + #define AFE_SECURE_MASK_CONN37_2 (0x42ec) 1796 + #define AFE_SECURE_MASK_CONN37_3 (0x42f0) 1797 + #define AFE_SECURE_MASK_CONN37_4 (0x42f4) 1798 + #define AFE_SECURE_MASK_CONN38 (0x42f8) 1799 + #define AFE_SECURE_MASK_CONN38_1 (0x42fc) 1800 + #define AFE_SECURE_MASK_CONN38_2 (0x4300) 1801 + #define AFE_SECURE_MASK_CONN38_3 (0x4304) 1802 + #define AFE_SECURE_MASK_CONN38_4 (0x4308) 1803 + #define AFE_SECURE_MASK_CONN39 (0x430c) 1804 + #define AFE_SECURE_MASK_CONN39_1 (0x4310) 1805 + #define AFE_SECURE_MASK_CONN39_2 (0x4314) 1806 + #define AFE_SECURE_MASK_CONN39_3 (0x4318) 1807 + #define AFE_SECURE_MASK_CONN39_4 (0x431c) 1808 + #define AFE_SECURE_MASK_CONN40 (0x4320) 1809 + #define AFE_SECURE_MASK_CONN40_1 (0x4324) 1810 + #define AFE_SECURE_MASK_CONN40_2 (0x4328) 1811 + #define AFE_SECURE_MASK_CONN40_3 (0x432c) 1812 + #define AFE_SECURE_MASK_CONN40_4 (0x4330) 1813 + #define AFE_SECURE_MASK_CONN41 (0x4334) 1814 + #define AFE_SECURE_MASK_CONN41_1 (0x4338) 1815 + #define AFE_SECURE_MASK_CONN41_2 (0x433c) 1816 + #define AFE_SECURE_MASK_CONN41_3 (0x4340) 1817 + #define AFE_SECURE_MASK_CONN41_4 (0x4344) 1818 + #define AFE_SECURE_MASK_CONN42 (0x4348) 1819 + #define AFE_SECURE_MASK_CONN42_1 (0x434c) 1820 + #define AFE_SECURE_MASK_CONN42_2 (0x4350) 1821 + #define AFE_SECURE_MASK_CONN42_3 (0x4354) 1822 + #define AFE_SECURE_MASK_CONN42_4 (0x4358) 1823 + #define AFE_SECURE_MASK_CONN43 (0x435c) 1824 + #define AFE_SECURE_MASK_CONN43_1 (0x4360) 1825 + #define AFE_SECURE_MASK_CONN43_2 (0x4364) 1826 + #define AFE_SECURE_MASK_CONN43_3 (0x4368) 1827 + #define AFE_SECURE_MASK_CONN43_4 (0x436c) 1828 + #define AFE_SECURE_MASK_CONN44 (0x4370) 1829 + #define AFE_SECURE_MASK_CONN44_1 (0x4374) 1830 + #define AFE_SECURE_MASK_CONN44_2 (0x4378) 1831 + #define AFE_SECURE_MASK_CONN44_3 (0x437c) 1832 + #define AFE_SECURE_MASK_CONN44_4 (0x4380) 1833 + #define AFE_SECURE_MASK_CONN45 (0x4384) 1834 + #define AFE_SECURE_MASK_CONN45_1 (0x4388) 1835 + #define AFE_SECURE_MASK_CONN45_2 (0x438c) 1836 + #define AFE_SECURE_MASK_CONN45_3 (0x4390) 1837 + #define AFE_SECURE_MASK_CONN45_4 (0x4394) 1838 + #define AFE_SECURE_MASK_CONN46 (0x4398) 1839 + #define AFE_SECURE_MASK_CONN46_1 (0x439c) 1840 + #define AFE_SECURE_MASK_CONN46_2 (0x43a0) 1841 + #define AFE_SECURE_MASK_CONN46_3 (0x43a4) 1842 + #define AFE_SECURE_MASK_CONN46_4 (0x43a8) 1843 + #define AFE_SECURE_MASK_CONN47 (0x43ac) 1844 + #define AFE_SECURE_MASK_CONN47_1 (0x43b0) 1845 + #define AFE_SECURE_MASK_CONN47_2 (0x43b4) 1846 + #define AFE_SECURE_MASK_CONN47_3 (0x43b8) 1847 + #define AFE_SECURE_MASK_CONN47_4 (0x43bc) 1848 + #define AFE_SECURE_MASK_CONN48 (0x43c0) 1849 + #define AFE_SECURE_MASK_CONN48_1 (0x43c4) 1850 + #define AFE_SECURE_MASK_CONN48_2 (0x43c8) 1851 + #define AFE_SECURE_MASK_CONN48_3 (0x43cc) 1852 + #define AFE_SECURE_MASK_CONN48_4 (0x43d0) 1853 + #define AFE_SECURE_MASK_CONN49 (0x43d4) 1854 + #define AFE_SECURE_MASK_CONN49_1 (0x43d8) 1855 + #define AFE_SECURE_MASK_CONN49_2 (0x43dc) 1856 + #define AFE_SECURE_MASK_CONN49_3 (0x43e0) 1857 + #define AFE_SECURE_MASK_CONN49_4 (0x43e4) 1858 + #define AFE_SECURE_MASK_CONN50 (0x43e8) 1859 + #define AFE_SECURE_MASK_CONN50_1 (0x43ec) 1860 + #define AFE_SECURE_MASK_CONN50_2 (0x43f0) 1861 + #define AFE_SECURE_MASK_CONN50_3 (0x43f4) 1862 + #define AFE_SECURE_MASK_CONN50_4 (0x43f8) 1863 + #define AFE_SECURE_MASK_CONN51 (0x43fc) 1864 + #define AFE_SECURE_MASK_CONN51_1 (0x4400) 1865 + #define AFE_SECURE_MASK_CONN51_2 (0x4404) 1866 + #define AFE_SECURE_MASK_CONN51_3 (0x4408) 1867 + #define AFE_SECURE_MASK_CONN51_4 (0x440c) 1868 + #define AFE_SECURE_MASK_CONN52 (0x4410) 1869 + #define AFE_SECURE_MASK_CONN52_1 (0x4414) 1870 + #define AFE_SECURE_MASK_CONN52_2 (0x4418) 1871 + #define AFE_SECURE_MASK_CONN52_3 (0x441c) 1872 + #define AFE_SECURE_MASK_CONN52_4 (0x4420) 1873 + #define AFE_SECURE_MASK_CONN53 (0x4424) 1874 + #define AFE_SECURE_MASK_CONN53_1 (0x4428) 1875 + #define AFE_SECURE_MASK_CONN53_2 (0x442c) 1876 + #define AFE_SECURE_MASK_CONN53_3 (0x4430) 1877 + #define AFE_SECURE_MASK_CONN53_4 (0x4434) 1878 + #define AFE_SECURE_MASK_CONN54 (0x4438) 1879 + #define AFE_SECURE_MASK_CONN54_1 (0x443c) 1880 + #define AFE_SECURE_MASK_CONN54_2 (0x4440) 1881 + #define AFE_SECURE_MASK_CONN54_3 (0x4444) 1882 + #define AFE_SECURE_MASK_CONN54_4 (0x4448) 1883 + #define AFE_SECURE_MASK_CONN55 (0x444c) 1884 + #define AFE_SECURE_MASK_CONN55_1 (0x4450) 1885 + #define AFE_SECURE_MASK_CONN55_2 (0x4454) 1886 + #define AFE_SECURE_MASK_CONN55_3 (0x4458) 1887 + #define AFE_SECURE_MASK_CONN55_4 (0x445c) 1888 + #define AFE_SECURE_MASK_CONN56 (0x4460) 1889 + #define AFE_SECURE_MASK_CONN56_1 (0x4464) 1890 + #define AFE_SECURE_MASK_CONN56_2 (0x4468) 1891 + #define AFE_SECURE_MASK_CONN56_3 (0x446c) 1892 + #define AFE_SECURE_MASK_CONN56_4 (0x4470) 1893 + #define AFE_SECURE_MASK_CONN57 (0x4474) 1894 + #define AFE_SECURE_MASK_CONN57_1 (0x4478) 1895 + #define AFE_SECURE_MASK_CONN57_2 (0x447c) 1896 + #define AFE_SECURE_MASK_CONN57_3 (0x4480) 1897 + #define AFE_SECURE_MASK_CONN57_4 (0x4484) 1898 + #define AFE_SECURE_MASK_CONN58 (0x4488) 1899 + #define AFE_SECURE_MASK_CONN58_1 (0x448c) 1900 + #define AFE_SECURE_MASK_CONN58_2 (0x4490) 1901 + #define AFE_SECURE_MASK_CONN58_3 (0x4494) 1902 + #define AFE_SECURE_MASK_CONN58_4 (0x4498) 1903 + #define AFE_SECURE_MASK_CONN59 (0x449c) 1904 + #define AFE_SECURE_MASK_CONN59_1 (0x44a0) 1905 + #define AFE_SECURE_MASK_CONN59_2 (0x44a4) 1906 + #define AFE_SECURE_MASK_CONN59_3 (0x44a8) 1907 + #define AFE_SECURE_MASK_CONN59_4 (0x44ac) 1908 + #define AFE_SECURE_MASK_CONN60 (0x44b0) 1909 + #define AFE_SECURE_MASK_CONN60_1 (0x44b4) 1910 + #define AFE_SECURE_MASK_CONN60_2 (0x44b8) 1911 + #define AFE_SECURE_MASK_CONN60_3 (0x44bc) 1912 + #define AFE_SECURE_MASK_CONN60_4 (0x44c0) 1913 + #define AFE_SECURE_MASK_CONN61 (0x44c4) 1914 + #define AFE_SECURE_MASK_CONN61_1 (0x44c8) 1915 + #define AFE_SECURE_MASK_CONN61_2 (0x44cc) 1916 + #define AFE_SECURE_MASK_CONN61_3 (0x44d0) 1917 + #define AFE_SECURE_MASK_CONN61_4 (0x44d4) 1918 + #define AFE_SECURE_MASK_CONN62 (0x44d8) 1919 + #define AFE_SECURE_MASK_CONN62_1 (0x44dc) 1920 + #define AFE_SECURE_MASK_CONN62_2 (0x44e0) 1921 + #define AFE_SECURE_MASK_CONN62_3 (0x44e4) 1922 + #define AFE_SECURE_MASK_CONN62_4 (0x44e8) 1923 + #define AFE_SECURE_MASK_CONN63 (0x44ec) 1924 + #define AFE_SECURE_MASK_CONN63_1 (0x44f0) 1925 + #define AFE_SECURE_MASK_CONN63_2 (0x44f4) 1926 + #define AFE_SECURE_MASK_CONN63_3 (0x44f8) 1927 + #define AFE_SECURE_MASK_CONN63_4 (0x44fc) 1928 + #define AFE_SECURE_MASK_CONN64 (0x4500) 1929 + #define AFE_SECURE_MASK_CONN64_1 (0x4504) 1930 + #define AFE_SECURE_MASK_CONN64_2 (0x4508) 1931 + #define AFE_SECURE_MASK_CONN64_3 (0x450c) 1932 + #define AFE_SECURE_MASK_CONN64_4 (0x4510) 1933 + #define AFE_SECURE_MASK_CONN65 (0x4514) 1934 + #define AFE_SECURE_MASK_CONN65_1 (0x4518) 1935 + #define AFE_SECURE_MASK_CONN65_2 (0x451c) 1936 + #define AFE_SECURE_MASK_CONN65_3 (0x4520) 1937 + #define AFE_SECURE_MASK_CONN65_4 (0x4524) 1938 + #define AFE_SECURE_MASK_CONN66 (0x4528) 1939 + #define AFE_SECURE_MASK_CONN66_1 (0x452c) 1940 + #define AFE_SECURE_MASK_CONN66_2 (0x4530) 1941 + #define AFE_SECURE_MASK_CONN66_3 (0x4534) 1942 + #define AFE_SECURE_MASK_CONN66_4 (0x4538) 1943 + #define AFE_SECURE_MASK_CONN67 (0x453c) 1944 + #define AFE_SECURE_MASK_CONN67_1 (0x4540) 1945 + #define AFE_SECURE_MASK_CONN67_2 (0x4544) 1946 + #define AFE_SECURE_MASK_CONN67_3 (0x4548) 1947 + #define AFE_SECURE_MASK_CONN67_4 (0x454c) 1948 + #define AFE_SECURE_MASK_CONN68 (0x4550) 1949 + #define AFE_SECURE_MASK_CONN68_1 (0x4554) 1950 + #define AFE_SECURE_MASK_CONN68_2 (0x4558) 1951 + #define AFE_SECURE_MASK_CONN68_3 (0x455c) 1952 + #define AFE_SECURE_MASK_CONN68_4 (0x4560) 1953 + #define AFE_SECURE_MASK_CONN69 (0x4564) 1954 + #define AFE_SECURE_MASK_CONN69_1 (0x4568) 1955 + #define AFE_SECURE_MASK_CONN69_2 (0x456c) 1956 + #define AFE_SECURE_MASK_CONN69_3 (0x4570) 1957 + #define AFE_SECURE_MASK_CONN69_4 (0x4574) 1958 + #define AFE_SECURE_MASK_CONN70 (0x4578) 1959 + #define AFE_SECURE_MASK_CONN70_1 (0x457c) 1960 + #define AFE_SECURE_MASK_CONN70_2 (0x4580) 1961 + #define AFE_SECURE_MASK_CONN70_3 (0x4584) 1962 + #define AFE_SECURE_MASK_CONN70_4 (0x4588) 1963 + #define AFE_SECURE_MASK_CONN71 (0x458c) 1964 + #define AFE_SECURE_MASK_CONN71_1 (0x4590) 1965 + #define AFE_SECURE_MASK_CONN71_2 (0x4594) 1966 + #define AFE_SECURE_MASK_CONN71_3 (0x4598) 1967 + #define AFE_SECURE_MASK_CONN71_4 (0x459c) 1968 + #define AFE_SECURE_MASK_CONN72 (0x45a0) 1969 + #define AFE_SECURE_MASK_CONN72_1 (0x45a4) 1970 + #define AFE_SECURE_MASK_CONN72_2 (0x45a8) 1971 + #define AFE_SECURE_MASK_CONN72_3 (0x45ac) 1972 + #define AFE_SECURE_MASK_CONN72_4 (0x45b0) 1973 + #define AFE_SECURE_MASK_CONN73 (0x45b4) 1974 + #define AFE_SECURE_MASK_CONN73_1 (0x45b8) 1975 + #define AFE_SECURE_MASK_CONN73_2 (0x45bc) 1976 + #define AFE_SECURE_MASK_CONN73_3 (0x45c0) 1977 + #define AFE_SECURE_MASK_CONN73_4 (0x45c4) 1978 + #define AFE_SECURE_MASK_CONN74 (0x45c8) 1979 + #define AFE_SECURE_MASK_CONN74_1 (0x45cc) 1980 + #define AFE_SECURE_MASK_CONN74_2 (0x45d0) 1981 + #define AFE_SECURE_MASK_CONN74_3 (0x45d4) 1982 + #define AFE_SECURE_MASK_CONN74_4 (0x45d8) 1983 + #define AFE_SECURE_MASK_CONN75 (0x45dc) 1984 + #define AFE_SECURE_MASK_CONN75_1 (0x45e0) 1985 + #define AFE_SECURE_MASK_CONN75_2 (0x45e4) 1986 + #define AFE_SECURE_MASK_CONN75_3 (0x45e8) 1987 + #define AFE_SECURE_MASK_CONN75_4 (0x45ec) 1988 + #define AFE_SECURE_MASK_CONN76 (0x45f0) 1989 + #define AFE_SECURE_MASK_CONN76_1 (0x45f4) 1990 + #define AFE_SECURE_MASK_CONN76_2 (0x45f8) 1991 + #define AFE_SECURE_MASK_CONN76_3 (0x45fc) 1992 + #define AFE_SECURE_MASK_CONN76_4 (0x4600) 1993 + #define AFE_SECURE_MASK_CONN77 (0x4604) 1994 + #define AFE_SECURE_MASK_CONN77_1 (0x4608) 1995 + #define AFE_SECURE_MASK_CONN77_2 (0x460c) 1996 + #define AFE_SECURE_MASK_CONN77_3 (0x4610) 1997 + #define AFE_SECURE_MASK_CONN77_4 (0x4614) 1998 + #define AFE_SECURE_MASK_CONN78 (0x4618) 1999 + #define AFE_SECURE_MASK_CONN78_1 (0x461c) 2000 + #define AFE_SECURE_MASK_CONN78_2 (0x4620) 2001 + #define AFE_SECURE_MASK_CONN78_3 (0x4624) 2002 + #define AFE_SECURE_MASK_CONN78_4 (0x4628) 2003 + #define AFE_SECURE_MASK_CONN79 (0x462c) 2004 + #define AFE_SECURE_MASK_CONN79_1 (0x4630) 2005 + #define AFE_SECURE_MASK_CONN79_2 (0x4634) 2006 + #define AFE_SECURE_MASK_CONN79_3 (0x4638) 2007 + #define AFE_SECURE_MASK_CONN79_4 (0x463c) 2008 + #define AFE_SECURE_MASK_CONN80 (0x4640) 2009 + #define AFE_SECURE_MASK_CONN80_1 (0x4644) 2010 + #define AFE_SECURE_MASK_CONN80_2 (0x4648) 2011 + #define AFE_SECURE_MASK_CONN80_3 (0x464c) 2012 + #define AFE_SECURE_MASK_CONN80_4 (0x4650) 2013 + #define AFE_SECURE_MASK_CONN81 (0x4654) 2014 + #define AFE_SECURE_MASK_CONN81_1 (0x4658) 2015 + #define AFE_SECURE_MASK_CONN81_2 (0x465c) 2016 + #define AFE_SECURE_MASK_CONN81_3 (0x4660) 2017 + #define AFE_SECURE_MASK_CONN81_4 (0x4664) 2018 + #define AFE_SECURE_MASK_CONN82 (0x4668) 2019 + #define AFE_SECURE_MASK_CONN82_1 (0x466c) 2020 + #define AFE_SECURE_MASK_CONN82_2 (0x4670) 2021 + #define AFE_SECURE_MASK_CONN82_3 (0x4674) 2022 + #define AFE_SECURE_MASK_CONN82_4 (0x4678) 2023 + #define AFE_SECURE_MASK_CONN83 (0x467c) 2024 + #define AFE_SECURE_MASK_CONN83_1 (0x4680) 2025 + #define AFE_SECURE_MASK_CONN83_2 (0x4684) 2026 + #define AFE_SECURE_MASK_CONN83_3 (0x4688) 2027 + #define AFE_SECURE_MASK_CONN83_4 (0x468c) 2028 + #define AFE_SECURE_MASK_CONN84 (0x4690) 2029 + #define AFE_SECURE_MASK_CONN84_1 (0x4694) 2030 + #define AFE_SECURE_MASK_CONN84_2 (0x4698) 2031 + #define AFE_SECURE_MASK_CONN84_3 (0x469c) 2032 + #define AFE_SECURE_MASK_CONN84_4 (0x46a0) 2033 + #define AFE_SECURE_MASK_CONN85 (0x46a4) 2034 + #define AFE_SECURE_MASK_CONN85_1 (0x46a8) 2035 + #define AFE_SECURE_MASK_CONN85_2 (0x46ac) 2036 + #define AFE_SECURE_MASK_CONN85_3 (0x46b0) 2037 + #define AFE_SECURE_MASK_CONN85_4 (0x46b4) 2038 + #define AFE_SECURE_MASK_CONN86 (0x46b8) 2039 + #define AFE_SECURE_MASK_CONN86_1 (0x46bc) 2040 + #define AFE_SECURE_MASK_CONN86_2 (0x46c0) 2041 + #define AFE_SECURE_MASK_CONN86_3 (0x46c4) 2042 + #define AFE_SECURE_MASK_CONN86_4 (0x46c8) 2043 + #define AFE_SECURE_MASK_CONN87 (0x46cc) 2044 + #define AFE_SECURE_MASK_CONN87_1 (0x46d0) 2045 + #define AFE_SECURE_MASK_CONN87_2 (0x46d4) 2046 + #define AFE_SECURE_MASK_CONN87_3 (0x46d8) 2047 + #define AFE_SECURE_MASK_CONN87_4 (0x46dc) 2048 + #define AFE_SECURE_MASK_CONN88 (0x46e0) 2049 + #define AFE_SECURE_MASK_CONN88_1 (0x46e4) 2050 + #define AFE_SECURE_MASK_CONN88_2 (0x46e8) 2051 + #define AFE_SECURE_MASK_CONN88_3 (0x46ec) 2052 + #define AFE_SECURE_MASK_CONN88_4 (0x46f0) 2053 + #define AFE_SECURE_MASK_CONN89 (0x46f4) 2054 + #define AFE_SECURE_MASK_CONN89_1 (0x46f8) 2055 + #define AFE_SECURE_MASK_CONN89_2 (0x46fc) 2056 + #define AFE_SECURE_MASK_CONN89_3 (0x4700) 2057 + #define AFE_SECURE_MASK_CONN89_4 (0x4704) 2058 + #define AFE_SECURE_MASK_CONN90 (0x4708) 2059 + #define AFE_SECURE_MASK_CONN90_1 (0x470c) 2060 + #define AFE_SECURE_MASK_CONN90_2 (0x4710) 2061 + #define AFE_SECURE_MASK_CONN90_3 (0x4714) 2062 + #define AFE_SECURE_MASK_CONN90_4 (0x4718) 2063 + #define AFE_SECURE_MASK_CONN91 (0x471c) 2064 + #define AFE_SECURE_MASK_CONN91_1 (0x4720) 2065 + #define AFE_SECURE_MASK_CONN91_2 (0x4724) 2066 + #define AFE_SECURE_MASK_CONN91_3 (0x4728) 2067 + #define AFE_SECURE_MASK_CONN91_4 (0x472c) 2068 + #define AFE_SECURE_MASK_CONN92 (0x4730) 2069 + #define AFE_SECURE_MASK_CONN92_1 (0x4734) 2070 + #define AFE_SECURE_MASK_CONN92_2 (0x4738) 2071 + #define AFE_SECURE_MASK_CONN92_3 (0x473c) 2072 + #define AFE_SECURE_MASK_CONN92_4 (0x4740) 2073 + #define AFE_SECURE_MASK_CONN93 (0x4744) 2074 + #define AFE_SECURE_MASK_CONN93_1 (0x4748) 2075 + #define AFE_SECURE_MASK_CONN93_2 (0x474c) 2076 + #define AFE_SECURE_MASK_CONN93_3 (0x4750) 2077 + #define AFE_SECURE_MASK_CONN93_4 (0x4754) 2078 + #define AFE_SECURE_MASK_CONN94 (0x4758) 2079 + #define AFE_SECURE_MASK_CONN94_1 (0x475c) 2080 + #define AFE_SECURE_MASK_CONN94_2 (0x4760) 2081 + #define AFE_SECURE_MASK_CONN94_3 (0x4764) 2082 + #define AFE_SECURE_MASK_CONN94_4 (0x4768) 2083 + #define AFE_SECURE_MASK_CONN95 (0x476c) 2084 + #define AFE_SECURE_MASK_CONN95_1 (0x4770) 2085 + #define AFE_SECURE_MASK_CONN95_2 (0x4774) 2086 + #define AFE_SECURE_MASK_CONN95_3 (0x4778) 2087 + #define AFE_SECURE_MASK_CONN95_4 (0x477c) 2088 + #define AFE_SECURE_MASK_CONN96 (0x4780) 2089 + #define AFE_SECURE_MASK_CONN96_1 (0x4784) 2090 + #define AFE_SECURE_MASK_CONN96_2 (0x4788) 2091 + #define AFE_SECURE_MASK_CONN96_3 (0x478c) 2092 + #define AFE_SECURE_MASK_CONN96_4 (0x4790) 2093 + #define AFE_SECURE_MASK_CONN97 (0x4794) 2094 + #define AFE_SECURE_MASK_CONN97_1 (0x4798) 2095 + #define AFE_SECURE_MASK_CONN97_2 (0x479c) 2096 + #define AFE_SECURE_MASK_CONN97_3 (0x47a0) 2097 + #define AFE_SECURE_MASK_CONN97_4 (0x47a4) 2098 + #define AFE_SECURE_MASK_CONN98 (0x47a8) 2099 + #define AFE_SECURE_MASK_CONN98_1 (0x47ac) 2100 + #define AFE_SECURE_MASK_CONN98_2 (0x47b0) 2101 + #define AFE_SECURE_MASK_CONN98_3 (0x47b4) 2102 + #define AFE_SECURE_MASK_CONN98_4 (0x47b8) 2103 + #define AFE_SECURE_MASK_CONN99 (0x47bc) 2104 + #define AFE_SECURE_MASK_CONN99_1 (0x47c0) 2105 + #define AFE_SECURE_MASK_CONN99_2 (0x47c4) 2106 + #define AFE_SECURE_MASK_CONN99_3 (0x47c8) 2107 + #define AFE_SECURE_MASK_CONN99_4 (0x47cc) 2108 + #define AFE_SECURE_MASK_CONN100 (0x47d0) 2109 + #define AFE_SECURE_MASK_CONN100_1 (0x47d4) 2110 + #define AFE_SECURE_MASK_CONN100_2 (0x47d8) 2111 + #define AFE_SECURE_MASK_CONN100_3 (0x47dc) 2112 + #define AFE_SECURE_MASK_CONN100_4 (0x47e0) 2113 + #define AFE_SECURE_MASK_CONN101 (0x47e4) 2114 + #define AFE_SECURE_MASK_CONN101_1 (0x47e8) 2115 + #define AFE_SECURE_MASK_CONN101_2 (0x47ec) 2116 + #define AFE_SECURE_MASK_CONN101_3 (0x47f0) 2117 + #define AFE_SECURE_MASK_CONN101_4 (0x47f4) 2118 + #define AFE_SECURE_MASK_CONN102 (0x47f8) 2119 + #define AFE_SECURE_MASK_CONN102_1 (0x47fc) 2120 + #define AFE_SECURE_MASK_CONN102_2 (0x4800) 2121 + #define AFE_SECURE_MASK_CONN102_3 (0x4804) 2122 + #define AFE_SECURE_MASK_CONN102_4 (0x4808) 2123 + #define AFE_SECURE_MASK_CONN103 (0x480c) 2124 + #define AFE_SECURE_MASK_CONN103_1 (0x4810) 2125 + #define AFE_SECURE_MASK_CONN103_2 (0x4814) 2126 + #define AFE_SECURE_MASK_CONN103_3 (0x4818) 2127 + #define AFE_SECURE_MASK_CONN103_4 (0x481c) 2128 + #define AFE_SECURE_MASK_CONN104 (0x4820) 2129 + #define AFE_SECURE_MASK_CONN104_1 (0x4824) 2130 + #define AFE_SECURE_MASK_CONN104_2 (0x4828) 2131 + #define AFE_SECURE_MASK_CONN104_3 (0x482c) 2132 + #define AFE_SECURE_MASK_CONN104_4 (0x4830) 2133 + #define AFE_SECURE_MASK_CONN105 (0x4834) 2134 + #define AFE_SECURE_MASK_CONN105_1 (0x4838) 2135 + #define AFE_SECURE_MASK_CONN105_2 (0x483c) 2136 + #define AFE_SECURE_MASK_CONN105_3 (0x4840) 2137 + #define AFE_SECURE_MASK_CONN105_4 (0x4844) 2138 + #define AFE_SECURE_MASK_CONN106 (0x4848) 2139 + #define AFE_SECURE_MASK_CONN106_1 (0x484c) 2140 + #define AFE_SECURE_MASK_CONN106_2 (0x4850) 2141 + #define AFE_SECURE_MASK_CONN106_3 (0x4854) 2142 + #define AFE_SECURE_MASK_CONN106_4 (0x4858) 2143 + #define AFE_SECURE_MASK_CONN107 (0x485c) 2144 + #define AFE_SECURE_MASK_CONN107_1 (0x4860) 2145 + #define AFE_SECURE_MASK_CONN107_2 (0x4864) 2146 + #define AFE_SECURE_MASK_CONN107_3 (0x4868) 2147 + #define AFE_SECURE_MASK_CONN107_4 (0x486c) 2148 + #define AFE_SECURE_MASK_CONN108 (0x4870) 2149 + #define AFE_SECURE_MASK_CONN108_1 (0x4874) 2150 + #define AFE_SECURE_MASK_CONN108_2 (0x4878) 2151 + #define AFE_SECURE_MASK_CONN108_3 (0x487c) 2152 + #define AFE_SECURE_MASK_CONN108_4 (0x4880) 2153 + #define AFE_SECURE_MASK_CONN109 (0x4884) 2154 + #define AFE_SECURE_MASK_CONN109_1 (0x4888) 2155 + #define AFE_SECURE_MASK_CONN109_2 (0x488c) 2156 + #define AFE_SECURE_MASK_CONN109_3 (0x4890) 2157 + #define AFE_SECURE_MASK_CONN109_4 (0x4894) 2158 + #define AFE_SECURE_MASK_CONN110 (0x4898) 2159 + #define AFE_SECURE_MASK_CONN110_1 (0x489c) 2160 + #define AFE_SECURE_MASK_CONN110_2 (0x48a0) 2161 + #define AFE_SECURE_MASK_CONN110_3 (0x48a4) 2162 + #define AFE_SECURE_MASK_CONN110_4 (0x48a8) 2163 + #define AFE_SECURE_MASK_CONN111 (0x48ac) 2164 + #define AFE_SECURE_MASK_CONN111_1 (0x48b0) 2165 + #define AFE_SECURE_MASK_CONN111_2 (0x48b4) 2166 + #define AFE_SECURE_MASK_CONN111_3 (0x48b8) 2167 + #define AFE_SECURE_MASK_CONN111_4 (0x48bc) 2168 + #define AFE_SECURE_MASK_CONN112 (0x48c0) 2169 + #define AFE_SECURE_MASK_CONN112_1 (0x48c4) 2170 + #define AFE_SECURE_MASK_CONN112_2 (0x48c8) 2171 + #define AFE_SECURE_MASK_CONN112_3 (0x48cc) 2172 + #define AFE_SECURE_MASK_CONN112_4 (0x48d0) 2173 + #define AFE_SECURE_MASK_CONN113 (0x48d4) 2174 + #define AFE_SECURE_MASK_CONN113_1 (0x48d8) 2175 + #define AFE_SECURE_MASK_CONN113_2 (0x48dc) 2176 + #define AFE_SECURE_MASK_CONN113_3 (0x48e0) 2177 + #define AFE_SECURE_MASK_CONN113_4 (0x48e4) 2178 + #define AFE_SECURE_MASK_CONN114 (0x48e8) 2179 + #define AFE_SECURE_MASK_CONN114_1 (0x48ec) 2180 + #define AFE_SECURE_MASK_CONN114_2 (0x48f0) 2181 + #define AFE_SECURE_MASK_CONN114_3 (0x48f4) 2182 + #define AFE_SECURE_MASK_CONN114_4 (0x48f8) 2183 + #define AFE_SECURE_MASK_CONN115 (0x48fc) 2184 + #define AFE_SECURE_MASK_CONN115_1 (0x4900) 2185 + #define AFE_SECURE_MASK_CONN115_2 (0x4904) 2186 + #define AFE_SECURE_MASK_CONN115_3 (0x4908) 2187 + #define AFE_SECURE_MASK_CONN115_4 (0x490c) 2188 + #define AFE_SECURE_MASK_CONN116 (0x4910) 2189 + #define AFE_SECURE_MASK_CONN116_1 (0x4914) 2190 + #define AFE_SECURE_MASK_CONN116_2 (0x4918) 2191 + #define AFE_SECURE_MASK_CONN116_3 (0x491c) 2192 + #define AFE_SECURE_MASK_CONN116_4 (0x4920) 2193 + #define AFE_SECURE_MASK_CONN117 (0x4924) 2194 + #define AFE_SECURE_MASK_CONN117_1 (0x4928) 2195 + #define AFE_SECURE_MASK_CONN117_2 (0x492c) 2196 + #define AFE_SECURE_MASK_CONN117_3 (0x4930) 2197 + #define AFE_SECURE_MASK_CONN117_4 (0x4934) 2198 + #define AFE_SECURE_MASK_CONN118 (0x4938) 2199 + #define AFE_SECURE_MASK_CONN118_1 (0x493c) 2200 + #define AFE_SECURE_MASK_CONN118_2 (0x4940) 2201 + #define AFE_SECURE_MASK_CONN118_3 (0x4944) 2202 + #define AFE_SECURE_MASK_CONN118_4 (0x4948) 2203 + #define AFE_SECURE_MASK_CONN119 (0x494c) 2204 + #define AFE_SECURE_MASK_CONN119_1 (0x4950) 2205 + #define AFE_SECURE_MASK_CONN119_2 (0x4954) 2206 + #define AFE_SECURE_MASK_CONN119_3 (0x4958) 2207 + #define AFE_SECURE_MASK_CONN119_4 (0x495c) 2208 + #define AFE_SECURE_MASK_CONN120 (0x4960) 2209 + #define AFE_SECURE_MASK_CONN120_1 (0x4964) 2210 + #define AFE_SECURE_MASK_CONN120_2 (0x4968) 2211 + #define AFE_SECURE_MASK_CONN120_3 (0x496c) 2212 + #define AFE_SECURE_MASK_CONN120_4 (0x4970) 2213 + #define AFE_SECURE_MASK_CONN121 (0x4974) 2214 + #define AFE_SECURE_MASK_CONN121_1 (0x4978) 2215 + #define AFE_SECURE_MASK_CONN121_2 (0x497c) 2216 + #define AFE_SECURE_MASK_CONN121_3 (0x4980) 2217 + #define AFE_SECURE_MASK_CONN121_4 (0x4984) 2218 + #define AFE_SECURE_MASK_CONN122 (0x4988) 2219 + #define AFE_SECURE_MASK_CONN122_1 (0x498c) 2220 + #define AFE_SECURE_MASK_CONN122_2 (0x4990) 2221 + #define AFE_SECURE_MASK_CONN122_3 (0x4994) 2222 + #define AFE_SECURE_MASK_CONN122_4 (0x4998) 2223 + #define AFE_SECURE_MASK_CONN123 (0x499c) 2224 + #define AFE_SECURE_MASK_CONN123_1 (0x49a0) 2225 + #define AFE_SECURE_MASK_CONN123_2 (0x49a4) 2226 + #define AFE_SECURE_MASK_CONN123_3 (0x49a8) 2227 + #define AFE_SECURE_MASK_CONN123_4 (0x49ac) 2228 + #define AFE_SECURE_MASK_CONN124 (0x49b0) 2229 + #define AFE_SECURE_MASK_CONN124_1 (0x49b4) 2230 + #define AFE_SECURE_MASK_CONN124_2 (0x49b8) 2231 + #define AFE_SECURE_MASK_CONN124_3 (0x49bc) 2232 + #define AFE_SECURE_MASK_CONN124_4 (0x49c0) 2233 + #define AFE_SECURE_MASK_CONN125 (0x49c4) 2234 + #define AFE_SECURE_MASK_CONN125_1 (0x49c8) 2235 + #define AFE_SECURE_MASK_CONN125_2 (0x49cc) 2236 + #define AFE_SECURE_MASK_CONN125_3 (0x49d0) 2237 + #define AFE_SECURE_MASK_CONN125_4 (0x49d4) 2238 + #define AFE_SECURE_MASK_CONN126 (0x49d8) 2239 + #define AFE_SECURE_MASK_CONN126_1 (0x49dc) 2240 + #define AFE_SECURE_MASK_CONN126_2 (0x49e0) 2241 + #define AFE_SECURE_MASK_CONN126_3 (0x49e4) 2242 + #define AFE_SECURE_MASK_CONN126_4 (0x49e8) 2243 + #define AFE_SECURE_MASK_CONN127 (0x49ec) 2244 + #define AFE_SECURE_MASK_CONN127_1 (0x49f0) 2245 + #define AFE_SECURE_MASK_CONN127_2 (0x49f4) 2246 + #define AFE_SECURE_MASK_CONN127_3 (0x49f8) 2247 + #define AFE_SECURE_MASK_CONN127_4 (0x49fc) 2248 + #define AFE_SECURE_MASK_CONN128 (0x4a00) 2249 + #define AFE_SECURE_MASK_CONN128_1 (0x4a04) 2250 + #define AFE_SECURE_MASK_CONN128_2 (0x4a08) 2251 + #define AFE_SECURE_MASK_CONN128_3 (0x4a0c) 2252 + #define AFE_SECURE_MASK_CONN128_4 (0x4a10) 2253 + #define AFE_SECURE_MASK_CONN129 (0x4a14) 2254 + #define AFE_SECURE_MASK_CONN129_1 (0x4a18) 2255 + #define AFE_SECURE_MASK_CONN129_2 (0x4a1c) 2256 + #define AFE_SECURE_MASK_CONN129_3 (0x4a20) 2257 + #define AFE_SECURE_MASK_CONN129_4 (0x4a24) 2258 + #define AFE_SECURE_MASK_CONN130 (0x4a28) 2259 + #define AFE_SECURE_MASK_CONN130_1 (0x4a2c) 2260 + #define AFE_SECURE_MASK_CONN130_2 (0x4a30) 2261 + #define AFE_SECURE_MASK_CONN130_3 (0x4a34) 2262 + #define AFE_SECURE_MASK_CONN130_4 (0x4a38) 2263 + #define AFE_SECURE_MASK_CONN131 (0x4a3c) 2264 + #define AFE_SECURE_MASK_CONN131_1 (0x4a40) 2265 + #define AFE_SECURE_MASK_CONN131_2 (0x4a44) 2266 + #define AFE_SECURE_MASK_CONN131_3 (0x4a48) 2267 + #define AFE_SECURE_MASK_CONN131_4 (0x4a4c) 2268 + #define AFE_SECURE_MASK_CONN132 (0x4a50) 2269 + #define AFE_SECURE_MASK_CONN132_1 (0x4a54) 2270 + #define AFE_SECURE_MASK_CONN132_2 (0x4a58) 2271 + #define AFE_SECURE_MASK_CONN132_3 (0x4a5c) 2272 + #define AFE_SECURE_MASK_CONN132_4 (0x4a60) 2273 + #define AFE_SECURE_MASK_CONN133 (0x4a64) 2274 + #define AFE_SECURE_MASK_CONN133_1 (0x4a68) 2275 + #define AFE_SECURE_MASK_CONN133_2 (0x4a6c) 2276 + #define AFE_SECURE_MASK_CONN133_3 (0x4a70) 2277 + #define AFE_SECURE_MASK_CONN133_4 (0x4a74) 2278 + #define AFE_SECURE_MASK_CONN134 (0x4a78) 2279 + #define AFE_SECURE_MASK_CONN134_1 (0x4a7c) 2280 + #define AFE_SECURE_MASK_CONN134_2 (0x4a80) 2281 + #define AFE_SECURE_MASK_CONN134_3 (0x4a84) 2282 + #define AFE_SECURE_MASK_CONN134_4 (0x4a88) 2283 + #define AFE_SECURE_MASK_CONN135 (0x4a8c) 2284 + #define AFE_SECURE_MASK_CONN135_1 (0x4a90) 2285 + #define AFE_SECURE_MASK_CONN135_2 (0x4a94) 2286 + #define AFE_SECURE_MASK_CONN135_3 (0x4a98) 2287 + #define AFE_SECURE_MASK_CONN135_4 (0x4a9c) 2288 + #define AFE_SECURE_MASK_CONN136 (0x4aa0) 2289 + #define AFE_SECURE_MASK_CONN136_1 (0x4aa4) 2290 + #define AFE_SECURE_MASK_CONN136_2 (0x4aa8) 2291 + #define AFE_SECURE_MASK_CONN136_3 (0x4aac) 2292 + #define AFE_SECURE_MASK_CONN136_4 (0x4ab0) 2293 + #define AFE_SECURE_MASK_CONN137 (0x4ab4) 2294 + #define AFE_SECURE_MASK_CONN137_1 (0x4ab8) 2295 + #define AFE_SECURE_MASK_CONN137_2 (0x4abc) 2296 + #define AFE_SECURE_MASK_CONN137_3 (0x4ac0) 2297 + #define AFE_SECURE_MASK_CONN137_4 (0x4ac4) 2298 + #define AFE_SECURE_MASK_CONN138 (0x4ac8) 2299 + #define AFE_SECURE_MASK_CONN138_1 (0x4acc) 2300 + #define AFE_SECURE_MASK_CONN138_2 (0x4ad0) 2301 + #define AFE_SECURE_MASK_CONN138_3 (0x4ad4) 2302 + #define AFE_SECURE_MASK_CONN138_4 (0x4ad8) 2303 + #define AFE_SECURE_MASK_CONN139 (0x4adc) 2304 + #define AFE_SECURE_MASK_CONN139_1 (0x4ae0) 2305 + #define AFE_SECURE_MASK_CONN139_2 (0x4ae4) 2306 + #define AFE_SECURE_MASK_CONN139_3 (0x4ae8) 2307 + #define AFE_SECURE_MASK_CONN139_4 (0x4aec) 2308 + #define AFE_SECURE_MASK_CONN_RS (0x4af0) 2309 + #define AFE_SECURE_MASK_CONN_RS_1 (0x4af4) 2310 + #define AFE_SECURE_MASK_CONN_RS_2 (0x4af8) 2311 + #define AFE_SECURE_MASK_CONN_RS_3 (0x4afc) 2312 + #define AFE_SECURE_MASK_CONN_RS_4 (0x4b00) 2313 + #define AFE_SECURE_MASK_CONN_16BIT (0x4b04) 2314 + #define AFE_SECURE_MASK_CONN_16BIT_1 (0x4b08) 2315 + #define AFE_SECURE_MASK_CONN_16BIT_2 (0x4b0c) 2316 + #define AFE_SECURE_MASK_CONN_16BIT_3 (0x4b10) 2317 + #define AFE_SECURE_MASK_CONN_16BIT_4 (0x4b14) 2318 + #define AFE_SECURE_MASK_CONN_24BIT (0x4b18) 2319 + #define AFE_SECURE_MASK_CONN_24BIT_1 (0x4b1c) 2320 + #define AFE_SECURE_MASK_CONN_24BIT_2 (0x4b20) 2321 + #define AFE_SECURE_MASK_CONN_24BIT_3 (0x4b24) 2322 + #define AFE_SECURE_MASK_CONN_24BIT_4 (0x4b28) 2323 + #define AFE_SECURE_MASK_CONN0_5 (0x4b2c) 2324 + #define AFE_SECURE_MASK_CONN1_5 (0x4b30) 2325 + #define AFE_SECURE_MASK_CONN2_5 (0x4b34) 2326 + #define AFE_SECURE_MASK_CONN3_5 (0x4b38) 2327 + #define AFE_SECURE_MASK_CONN4_5 (0x4b3c) 2328 + #define AFE_SECURE_MASK_CONN5_5 (0x4b40) 2329 + #define AFE_SECURE_MASK_CONN6_5 (0x4b44) 2330 + #define AFE_SECURE_MASK_CONN7_5 (0x4b48) 2331 + #define AFE_SECURE_MASK_CONN8_5 (0x4b4c) 2332 + #define AFE_SECURE_MASK_CONN9_5 (0x4b50) 2333 + #define AFE_SECURE_MASK_CONN10_5 (0x4b54) 2334 + #define AFE_SECURE_MASK_CONN11_5 (0x4b58) 2335 + #define AFE_SECURE_MASK_CONN12_5 (0x4b5c) 2336 + #define AFE_SECURE_MASK_CONN13_5 (0x4b60) 2337 + #define AFE_SECURE_MASK_CONN14_5 (0x4b64) 2338 + #define AFE_SECURE_MASK_CONN15_5 (0x4b68) 2339 + #define AFE_SECURE_MASK_CONN16_5 (0x4b6c) 2340 + #define AFE_SECURE_MASK_CONN17_5 (0x4b70) 2341 + #define AFE_SECURE_MASK_CONN18_5 (0x4b74) 2342 + #define AFE_SECURE_MASK_CONN19_5 (0x4b78) 2343 + #define AFE_SECURE_MASK_CONN20_5 (0x4b7c) 2344 + #define AFE_SECURE_MASK_CONN21_5 (0x4b80) 2345 + #define AFE_SECURE_MASK_CONN22_5 (0x4b84) 2346 + #define AFE_SECURE_MASK_CONN23_5 (0x4b88) 2347 + #define AFE_SECURE_MASK_CONN24_5 (0x4b8c) 2348 + #define AFE_SECURE_MASK_CONN25_5 (0x4b90) 2349 + #define AFE_SECURE_MASK_CONN26_5 (0x4b94) 2350 + #define AFE_SECURE_MASK_CONN27_5 (0x4b98) 2351 + #define AFE_SECURE_MASK_CONN28_5 (0x4b9c) 2352 + #define AFE_SECURE_MASK_CONN29_5 (0x4ba0) 2353 + #define AFE_SECURE_MASK_CONN30_5 (0x4ba4) 2354 + #define AFE_SECURE_MASK_CONN31_5 (0x4ba8) 2355 + #define AFE_SECURE_MASK_CONN32_5 (0x4bac) 2356 + #define AFE_SECURE_MASK_CONN33_5 (0x4bb0) 2357 + #define AFE_SECURE_MASK_CONN34_5 (0x4bb4) 2358 + #define AFE_SECURE_MASK_CONN35_5 (0x4bb8) 2359 + #define AFE_SECURE_MASK_CONN36_5 (0x4bbc) 2360 + #define AFE_SECURE_MASK_CONN37_5 (0x4bc0) 2361 + #define AFE_SECURE_MASK_CONN38_5 (0x4bc4) 2362 + #define AFE_SECURE_MASK_CONN39_5 (0x4bc8) 2363 + #define AFE_SECURE_MASK_CONN40_5 (0x4bcc) 2364 + #define AFE_SECURE_MASK_CONN41_5 (0x4bd0) 2365 + #define AFE_SECURE_MASK_CONN42_5 (0x4bd4) 2366 + #define AFE_SECURE_MASK_CONN43_5 (0x4bd8) 2367 + #define AFE_SECURE_MASK_CONN44_5 (0x4bdc) 2368 + #define AFE_SECURE_MASK_CONN45_5 (0x4be0) 2369 + #define AFE_SECURE_MASK_CONN46_5 (0x4be4) 2370 + #define AFE_SECURE_MASK_CONN47_5 (0x4be8) 2371 + #define AFE_SECURE_MASK_CONN48_5 (0x4bec) 2372 + #define AFE_SECURE_MASK_CONN49_5 (0x4bf0) 2373 + #define AFE_SECURE_MASK_CONN50_5 (0x4bf4) 2374 + #define AFE_SECURE_MASK_CONN51_5 (0x4bf8) 2375 + #define AFE_SECURE_MASK_CONN52_5 (0x4bfc) 2376 + #define AFE_GASRC0_NEW_CON0 (0x4c40) 2377 + #define AFE_GASRC0_NEW_CON1 (0x4c44) 2378 + #define AFE_GASRC0_NEW_CON2 (0x4c48) 2379 + #define AFE_GASRC0_NEW_CON3 (0x4c4c) 2380 + #define AFE_GASRC0_NEW_CON4 (0x4c50) 2381 + #define AFE_GASRC0_NEW_CON5 (0x4c54) 2382 + #define AFE_GASRC0_NEW_CON6 (0x4c58) 2383 + #define AFE_GASRC0_NEW_CON7 (0x4c5c) 2384 + #define AFE_GASRC0_NEW_CON8 (0x4c60) 2385 + #define AFE_GASRC0_NEW_CON9 (0x4c64) 2386 + #define AFE_GASRC0_NEW_CON10 (0x4c68) 2387 + #define AFE_GASRC0_NEW_CON11 (0x4c6c) 2388 + #define AFE_GASRC0_NEW_CON12 (0x4c70) 2389 + #define AFE_GASRC0_NEW_CON13 (0x4c74) 2390 + #define AFE_GASRC0_NEW_CON14 (0x4c78) 2391 + #define AFE_GASRC1_NEW_CON0 (0x4c80) 2392 + #define AFE_GASRC1_NEW_CON1 (0x4c84) 2393 + #define AFE_GASRC1_NEW_CON2 (0x4c88) 2394 + #define AFE_GASRC1_NEW_CON3 (0x4c8c) 2395 + #define AFE_GASRC1_NEW_CON4 (0x4c90) 2396 + #define AFE_GASRC1_NEW_CON5 (0x4c94) 2397 + #define AFE_GASRC1_NEW_CON6 (0x4c98) 2398 + #define AFE_GASRC1_NEW_CON7 (0x4c9c) 2399 + #define AFE_GASRC1_NEW_CON8 (0x4ca0) 2400 + #define AFE_GASRC1_NEW_CON9 (0x4ca4) 2401 + #define AFE_GASRC1_NEW_CON10 (0x4ca8) 2402 + #define AFE_GASRC1_NEW_CON11 (0x4cac) 2403 + #define AFE_GASRC1_NEW_CON12 (0x4cb0) 2404 + #define AFE_GASRC1_NEW_CON13 (0x4cb4) 2405 + #define AFE_GASRC1_NEW_CON14 (0x4cb8) 2406 + #define AFE_GASRC2_NEW_CON0 (0x4cc0) 2407 + #define AFE_GASRC2_NEW_CON1 (0x4cc4) 2408 + #define AFE_GASRC2_NEW_CON2 (0x4cc8) 2409 + #define AFE_GASRC2_NEW_CON3 (0x4ccc) 2410 + #define AFE_GASRC2_NEW_CON4 (0x4cd0) 2411 + #define AFE_GASRC2_NEW_CON5 (0x4cd4) 2412 + #define AFE_GASRC2_NEW_CON6 (0x4cd8) 2413 + #define AFE_GASRC2_NEW_CON7 (0x4cdc) 2414 + #define AFE_GASRC2_NEW_CON8 (0x4ce0) 2415 + #define AFE_GASRC2_NEW_CON9 (0x4ce4) 2416 + #define AFE_GASRC2_NEW_CON10 (0x4ce8) 2417 + #define AFE_GASRC2_NEW_CON11 (0x4cec) 2418 + #define AFE_GASRC2_NEW_CON12 (0x4cf0) 2419 + #define AFE_GASRC2_NEW_CON13 (0x4cf4) 2420 + #define AFE_GASRC2_NEW_CON14 (0x4cf8) 2421 + #define AFE_GASRC3_NEW_CON0 (0x4d00) 2422 + #define AFE_GASRC3_NEW_CON1 (0x4d04) 2423 + #define AFE_GASRC3_NEW_CON2 (0x4d08) 2424 + #define AFE_GASRC3_NEW_CON3 (0x4d0c) 2425 + #define AFE_GASRC3_NEW_CON4 (0x4d10) 2426 + #define AFE_GASRC3_NEW_CON5 (0x4d14) 2427 + #define AFE_GASRC3_NEW_CON6 (0x4d18) 2428 + #define AFE_GASRC3_NEW_CON7 (0x4d1c) 2429 + #define AFE_GASRC3_NEW_CON8 (0x4d20) 2430 + #define AFE_GASRC3_NEW_CON9 (0x4d24) 2431 + #define AFE_GASRC3_NEW_CON10 (0x4d28) 2432 + #define AFE_GASRC3_NEW_CON11 (0x4d2c) 2433 + #define AFE_GASRC3_NEW_CON12 (0x4d30) 2434 + #define AFE_GASRC3_NEW_CON13 (0x4d34) 2435 + #define AFE_GASRC3_NEW_CON14 (0x4d38) 2436 + #define AFE_GASRC4_NEW_CON0 (0x4d40) 2437 + #define AFE_GASRC4_NEW_CON1 (0x4d44) 2438 + #define AFE_GASRC4_NEW_CON2 (0x4d48) 2439 + #define AFE_GASRC4_NEW_CON3 (0x4d4c) 2440 + #define AFE_GASRC4_NEW_CON4 (0x4d50) 2441 + #define AFE_GASRC4_NEW_CON5 (0x4d54) 2442 + #define AFE_GASRC4_NEW_CON6 (0x4d58) 2443 + #define AFE_GASRC4_NEW_CON7 (0x4d5c) 2444 + #define AFE_GASRC4_NEW_CON8 (0x4d60) 2445 + #define AFE_GASRC4_NEW_CON9 (0x4d64) 2446 + #define AFE_GASRC4_NEW_CON10 (0x4d68) 2447 + #define AFE_GASRC4_NEW_CON11 (0x4d6c) 2448 + #define AFE_GASRC4_NEW_CON12 (0x4d70) 2449 + #define AFE_GASRC4_NEW_CON13 (0x4d74) 2450 + #define AFE_GASRC4_NEW_CON14 (0x4d78) 2451 + #define AFE_GASRC5_NEW_CON0 (0x4d80) 2452 + #define AFE_GASRC5_NEW_CON1 (0x4d84) 2453 + #define AFE_GASRC5_NEW_CON2 (0x4d88) 2454 + #define AFE_GASRC5_NEW_CON3 (0x4d8c) 2455 + #define AFE_GASRC5_NEW_CON4 (0x4d90) 2456 + #define AFE_GASRC5_NEW_CON5 (0x4d94) 2457 + #define AFE_GASRC5_NEW_CON6 (0x4d98) 2458 + #define AFE_GASRC5_NEW_CON7 (0x4d9c) 2459 + #define AFE_GASRC5_NEW_CON8 (0x4da0) 2460 + #define AFE_GASRC5_NEW_CON9 (0x4da4) 2461 + #define AFE_GASRC5_NEW_CON10 (0x4da8) 2462 + #define AFE_GASRC5_NEW_CON11 (0x4dac) 2463 + #define AFE_GASRC5_NEW_CON12 (0x4db0) 2464 + #define AFE_GASRC5_NEW_CON13 (0x4db4) 2465 + #define AFE_GASRC5_NEW_CON14 (0x4db8) 2466 + #define AFE_GASRC6_NEW_CON0 (0x4dc0) 2467 + #define AFE_GASRC6_NEW_CON1 (0x4dc4) 2468 + #define AFE_GASRC6_NEW_CON2 (0x4dc8) 2469 + #define AFE_GASRC6_NEW_CON3 (0x4dcc) 2470 + #define AFE_GASRC6_NEW_CON4 (0x4dd0) 2471 + #define AFE_GASRC6_NEW_CON5 (0x4dd4) 2472 + #define AFE_GASRC6_NEW_CON6 (0x4dd8) 2473 + #define AFE_GASRC6_NEW_CON7 (0x4ddc) 2474 + #define AFE_GASRC6_NEW_CON8 (0x4de0) 2475 + #define AFE_GASRC6_NEW_CON9 (0x4de4) 2476 + #define AFE_GASRC6_NEW_CON10 (0x4de8) 2477 + #define AFE_GASRC6_NEW_CON11 (0x4dec) 2478 + #define AFE_GASRC6_NEW_CON12 (0x4df0) 2479 + #define AFE_GASRC6_NEW_CON13 (0x4df4) 2480 + #define AFE_GASRC6_NEW_CON14 (0x4df8) 2481 + #define AFE_GASRC7_NEW_CON0 (0x4e00) 2482 + #define AFE_GASRC7_NEW_CON1 (0x4e04) 2483 + #define AFE_GASRC7_NEW_CON2 (0x4e08) 2484 + #define AFE_GASRC7_NEW_CON3 (0x4e0c) 2485 + #define AFE_GASRC7_NEW_CON4 (0x4e10) 2486 + #define AFE_GASRC7_NEW_CON5 (0x4e14) 2487 + #define AFE_GASRC7_NEW_CON6 (0x4e18) 2488 + #define AFE_GASRC7_NEW_CON7 (0x4e1c) 2489 + #define AFE_GASRC7_NEW_CON8 (0x4e20) 2490 + #define AFE_GASRC7_NEW_CON9 (0x4e24) 2491 + #define AFE_GASRC7_NEW_CON10 (0x4e28) 2492 + #define AFE_GASRC7_NEW_CON11 (0x4e2c) 2493 + #define AFE_GASRC7_NEW_CON12 (0x4e30) 2494 + #define AFE_GASRC7_NEW_CON13 (0x4e34) 2495 + #define AFE_GASRC7_NEW_CON14 (0x4e38) 2496 + #define AFE_GASRC8_NEW_CON0 (0x4e40) 2497 + #define AFE_GASRC8_NEW_CON1 (0x4e44) 2498 + #define AFE_GASRC8_NEW_CON2 (0x4e48) 2499 + #define AFE_GASRC8_NEW_CON3 (0x4e4c) 2500 + #define AFE_GASRC8_NEW_CON4 (0x4e50) 2501 + #define AFE_GASRC8_NEW_CON5 (0x4e54) 2502 + #define AFE_GASRC8_NEW_CON6 (0x4e58) 2503 + #define AFE_GASRC8_NEW_CON7 (0x4e5c) 2504 + #define AFE_GASRC8_NEW_CON8 (0x4e60) 2505 + #define AFE_GASRC8_NEW_CON9 (0x4e64) 2506 + #define AFE_GASRC8_NEW_CON10 (0x4e68) 2507 + #define AFE_GASRC8_NEW_CON11 (0x4e6c) 2508 + #define AFE_GASRC8_NEW_CON12 (0x4e70) 2509 + #define AFE_GASRC8_NEW_CON13 (0x4e74) 2510 + #define AFE_GASRC8_NEW_CON14 (0x4e78) 2511 + #define AFE_GASRC9_NEW_CON0 (0x4e80) 2512 + #define AFE_GASRC9_NEW_CON1 (0x4e84) 2513 + #define AFE_GASRC9_NEW_CON2 (0x4e88) 2514 + #define AFE_GASRC9_NEW_CON3 (0x4e8c) 2515 + #define AFE_GASRC9_NEW_CON4 (0x4e90) 2516 + #define AFE_GASRC9_NEW_CON5 (0x4e94) 2517 + #define AFE_GASRC9_NEW_CON6 (0x4e98) 2518 + #define AFE_GASRC9_NEW_CON7 (0x4e9c) 2519 + #define AFE_GASRC9_NEW_CON8 (0x4ea0) 2520 + #define AFE_GASRC9_NEW_CON9 (0x4ea4) 2521 + #define AFE_GASRC9_NEW_CON10 (0x4ea8) 2522 + #define AFE_GASRC9_NEW_CON11 (0x4eac) 2523 + #define AFE_GASRC9_NEW_CON12 (0x4eb0) 2524 + #define AFE_GASRC9_NEW_CON13 (0x4eb4) 2525 + #define AFE_GASRC9_NEW_CON14 (0x4eb8) 2526 + #define AFE_GASRC10_NEW_CON0 (0x4ec0) 2527 + #define AFE_GASRC10_NEW_CON1 (0x4ec4) 2528 + #define AFE_GASRC10_NEW_CON2 (0x4ec8) 2529 + #define AFE_GASRC10_NEW_CON3 (0x4ecc) 2530 + #define AFE_GASRC10_NEW_CON4 (0x4ed0) 2531 + #define AFE_GASRC10_NEW_CON5 (0x4ed4) 2532 + #define AFE_GASRC10_NEW_CON6 (0x4ed8) 2533 + #define AFE_GASRC10_NEW_CON7 (0x4edc) 2534 + #define AFE_GASRC10_NEW_CON8 (0x4ee0) 2535 + #define AFE_GASRC10_NEW_CON9 (0x4ee4) 2536 + #define AFE_GASRC10_NEW_CON10 (0x4ee8) 2537 + #define AFE_GASRC10_NEW_CON11 (0x4eec) 2538 + #define AFE_GASRC10_NEW_CON12 (0x4ef0) 2539 + #define AFE_GASRC10_NEW_CON13 (0x4ef4) 2540 + #define AFE_GASRC10_NEW_CON14 (0x4ef8) 2541 + #define AFE_GASRC11_NEW_CON0 (0x4f00) 2542 + #define AFE_GASRC11_NEW_CON1 (0x4f04) 2543 + #define AFE_GASRC11_NEW_CON2 (0x4f08) 2544 + #define AFE_GASRC11_NEW_CON3 (0x4f0c) 2545 + #define AFE_GASRC11_NEW_CON4 (0x4f10) 2546 + #define AFE_GASRC11_NEW_CON5 (0x4f14) 2547 + #define AFE_GASRC11_NEW_CON6 (0x4f18) 2548 + #define AFE_GASRC11_NEW_CON7 (0x4f1c) 2549 + #define AFE_GASRC11_NEW_CON8 (0x4f20) 2550 + #define AFE_GASRC11_NEW_CON9 (0x4f24) 2551 + #define AFE_GASRC11_NEW_CON10 (0x4f28) 2552 + #define AFE_GASRC11_NEW_CON11 (0x4f2c) 2553 + #define AFE_GASRC11_NEW_CON12 (0x4f30) 2554 + #define AFE_GASRC11_NEW_CON13 (0x4f34) 2555 + #define AFE_GASRC11_NEW_CON14 (0x4f38) 2556 + 2557 + #define AFE_IEC_BURST_INFO_MON (0x64b0) 2558 + #define AFE_SPDIFOUT_IP_VERSION (0x64b4) 2559 + #define AFE_SPDIF_OUT_CFG0 (0x64b8) 2560 + #define AFE_SPDIF_OUT_CFG1 (0x64bc) 2561 + #define AFE_SPDIF_OUT_CHSTS1 (0x64c0) 2562 + #define AFE_SPDIF_OUT_CHSTS2 (0x64c4) 2563 + #define AFE_SPDIF_OUT_CHSTS3 (0x64c8) 2564 + #define AFE_SPDIF_OUT_CHSTS4 (0x64cc) 2565 + #define AFE_SPDIF_OUT_CHSTS5 (0x64d0) 2566 + #define AFE_SPDIF_OUT_CHSTS6 (0x64d4) 2567 + #define AFE_SPDIF_OUT_USERCODE1 (0x64d8) 2568 + #define AFE_SPDIF_OUT_USERCODE2 (0x64dc) 2569 + #define AFE_SPDIF_OUT_USERCODE3 (0x64e0) 2570 + #define AFE_SPDIF_OUT_USERCODE4 (0x64e4) 2571 + #define AFE_SPDIF_OUT_USERCODE5 (0x64e8) 2572 + #define AFE_SPDIF_OUT_USERCODE6 (0x64ec) 2573 + #define AFE_SPDIF_OUT_BURST_PRE0 (0x64f0) 2574 + #define AFE_SPDIF_OUT_BURST_PRE1 (0x64f4) 2575 + #define AFE_SPDIF_OUT_MON0 (0x64f8) 2576 + #define AFE_SPDIF_OUT_MON1 (0x64fc) 2577 + #define AFE_SPDIF_OUT_MON2 (0x6500) 2578 + #define AFE_SPDIF_OUT_MON3 (0x6504) 2579 + #define AFE_SPDIF_OUT_MON4 (0x6508) 2580 + #define AFE_SPDIF_OUT_MON5 (0x650c) 2581 + #define AFE_CONN0_6 (0x7000) 2582 + #define AFE_CONN1_6 (0x7004) 2583 + #define AFE_CONN2_6 (0x7008) 2584 + #define AFE_CONN3_6 (0x700c) 2585 + #define AFE_CONN4_6 (0x7010) 2586 + #define AFE_CONN5_6 (0x7014) 2587 + #define AFE_CONN6_6 (0x7018) 2588 + #define AFE_CONN7_6 (0x701c) 2589 + #define AFE_CONN8_6 (0x7020) 2590 + #define AFE_CONN9_6 (0x7024) 2591 + #define AFE_CONN10_6 (0x7028) 2592 + #define AFE_CONN11_6 (0x702c) 2593 + #define AFE_CONN12_6 (0x7030) 2594 + #define AFE_CONN13_6 (0x7034) 2595 + #define AFE_CONN14_6 (0x7038) 2596 + #define AFE_CONN15_6 (0x703c) 2597 + #define AFE_CONN16_6 (0x7040) 2598 + #define AFE_CONN17_6 (0x7044) 2599 + #define AFE_CONN18_6 (0x7048) 2600 + #define AFE_CONN19_6 (0x704c) 2601 + #define AFE_CONN20_6 (0x7050) 2602 + #define AFE_CONN21_6 (0x7054) 2603 + #define AFE_CONN22_6 (0x7058) 2604 + #define AFE_CONN23_6 (0x705c) 2605 + #define AFE_CONN24_6 (0x7060) 2606 + #define AFE_CONN25_6 (0x7064) 2607 + #define AFE_CONN26_6 (0x7068) 2608 + #define AFE_CONN27_6 (0x706c) 2609 + #define AFE_CONN28_6 (0x7070) 2610 + #define AFE_CONN29_6 (0x7074) 2611 + #define AFE_CONN30_6 (0x7078) 2612 + #define AFE_CONN31_6 (0x707c) 2613 + #define AFE_CONN32_6 (0x7080) 2614 + #define AFE_CONN33_6 (0x7084) 2615 + #define AFE_CONN34_6 (0x7088) 2616 + #define AFE_CONN35_6 (0x708c) 2617 + #define AFE_CONN36_6 (0x7090) 2618 + #define AFE_CONN37_6 (0x7094) 2619 + #define AFE_CONN38_6 (0x7098) 2620 + #define AFE_CONN39_6 (0x709c) 2621 + #define AFE_CONN40_6 (0x70a0) 2622 + #define AFE_CONN41_6 (0x70a4) 2623 + #define AFE_CONN42_6 (0x70a8) 2624 + #define AFE_CONN43_6 (0x70ac) 2625 + #define AFE_CONN44_6 (0x70b0) 2626 + #define AFE_CONN45_6 (0x70b4) 2627 + #define AFE_CONN46_6 (0x70b8) 2628 + #define AFE_CONN47_6 (0x70bc) 2629 + #define AFE_CONN48_6 (0x70c0) 2630 + #define AFE_CONN49_6 (0x70c4) 2631 + #define AFE_CONN50_6 (0x70c8) 2632 + #define AFE_CONN51_6 (0x70cc) 2633 + #define AFE_CONN52_6 (0x70d0) 2634 + #define AFE_CONN53_6 (0x70d4) 2635 + #define AFE_CONN54_6 (0x70d8) 2636 + #define AFE_CONN55_6 (0x70dc) 2637 + #define AFE_CONN56_6 (0x70e0) 2638 + #define AFE_CONN57_6 (0x70e4) 2639 + #define AFE_CONN58_6 (0x70e8) 2640 + #define AFE_CONN59_6 (0x70ec) 2641 + #define AFE_CONN60_6 (0x70f0) 2642 + #define AFE_CONN61_6 (0x70f4) 2643 + #define AFE_CONN62_6 (0x70f8) 2644 + #define AFE_CONN63_6 (0x70fc) 2645 + #define AFE_CONN64_6 (0x7100) 2646 + #define AFE_CONN65_6 (0x7104) 2647 + #define AFE_CONN66_6 (0x7108) 2648 + #define AFE_CONN67_6 (0x710c) 2649 + #define AFE_CONN68_6 (0x7110) 2650 + #define AFE_CONN69_6 (0x7114) 2651 + #define AFE_CONN70_6 (0x7118) 2652 + #define AFE_CONN71_6 (0x711c) 2653 + #define AFE_CONN72_6 (0x7120) 2654 + #define AFE_CONN73_6 (0x7124) 2655 + #define AFE_CONN74_6 (0x7128) 2656 + #define AFE_CONN75_6 (0x712c) 2657 + #define AFE_CONN76_6 (0x7130) 2658 + #define AFE_CONN77_6 (0x7134) 2659 + #define AFE_CONN78_6 (0x7138) 2660 + #define AFE_CONN79_6 (0x713c) 2661 + #define AFE_CONN80_6 (0x7140) 2662 + #define AFE_CONN81_6 (0x7144) 2663 + #define AFE_CONN82_6 (0x7148) 2664 + #define AFE_CONN83_6 (0x714c) 2665 + #define AFE_CONN84_6 (0x7150) 2666 + #define AFE_CONN85_6 (0x7154) 2667 + #define AFE_CONN86_6 (0x7158) 2668 + #define AFE_CONN87_6 (0x715c) 2669 + #define AFE_CONN88_6 (0x7160) 2670 + #define AFE_CONN89_6 (0x7164) 2671 + #define AFE_CONN90_6 (0x7168) 2672 + #define AFE_CONN91_6 (0x716c) 2673 + #define AFE_CONN92_6 (0x7170) 2674 + #define AFE_CONN93_6 (0x7174) 2675 + #define AFE_CONN94_6 (0x7178) 2676 + #define AFE_CONN95_6 (0x717c) 2677 + #define AFE_CONN96_6 (0x7180) 2678 + #define AFE_CONN97_6 (0x7184) 2679 + #define AFE_CONN98_6 (0x7188) 2680 + #define AFE_CONN99_6 (0x718c) 2681 + #define AFE_CONN100_6 (0x7190) 2682 + #define AFE_CONN101_6 (0x7194) 2683 + #define AFE_CONN102_6 (0x7198) 2684 + #define AFE_CONN103_6 (0x719c) 2685 + #define AFE_CONN104_6 (0x71a0) 2686 + #define AFE_CONN105_6 (0x71a4) 2687 + #define AFE_CONN106_6 (0x71a8) 2688 + #define AFE_CONN107_6 (0x71ac) 2689 + #define AFE_CONN108_6 (0x71b0) 2690 + #define AFE_CONN109_6 (0x71b4) 2691 + #define AFE_CONN110_6 (0x71b8) 2692 + #define AFE_CONN111_6 (0x71bc) 2693 + #define AFE_CONN112_6 (0x71c0) 2694 + #define AFE_CONN113_6 (0x71c4) 2695 + #define AFE_CONN114_6 (0x71c8) 2696 + #define AFE_CONN115_6 (0x71cc) 2697 + #define AFE_CONN116_6 (0x71d0) 2698 + #define AFE_CONN117_6 (0x71d4) 2699 + #define AFE_CONN118_6 (0x71d8) 2700 + #define AFE_CONN119_6 (0x71dc) 2701 + #define AFE_CONN120_6 (0x71e0) 2702 + #define AFE_CONN121_6 (0x71e4) 2703 + #define AFE_CONN122_6 (0x71e8) 2704 + #define AFE_CONN123_6 (0x71ec) 2705 + #define AFE_CONN124_6 (0x71f0) 2706 + #define AFE_CONN125_6 (0x71f4) 2707 + #define AFE_CONN126_6 (0x71f8) 2708 + #define AFE_CONN127_6 (0x71fc) 2709 + #define AFE_CONN128_6 (0x7200) 2710 + #define AFE_CONN129_6 (0x7204) 2711 + #define AFE_CONN130_6 (0x7208) 2712 + #define AFE_CONN131_6 (0x720c) 2713 + #define AFE_CONN132_6 (0x7210) 2714 + #define AFE_CONN133_6 (0x7214) 2715 + #define AFE_CONN134_6 (0x7218) 2716 + #define AFE_CONN135_6 (0x721c) 2717 + #define AFE_CONN136_6 (0x7220) 2718 + #define AFE_CONN137_6 (0x7224) 2719 + #define AFE_CONN138_6 (0x7228) 2720 + #define AFE_CONN139_6 (0x722c) 2721 + #define AFE_CONN176_6 (0x72c0) 2722 + #define AFE_CONN177_6 (0x72c4) 2723 + #define AFE_CONN182_6 (0x72d8) 2724 + #define AFE_CONN183_6 (0x72dc) 2725 + 2726 + #define AFE_MAX_REGISTER (AFE_CONN183_6) 2727 + 2728 + /* PWR1_ASM_CON1 */ 2729 + #define PWR1_ASM_CON1_GASRC0_CALI_CK_SEL_MASK BIT(2) 2730 + #define PWR1_ASM_CON1_GASRC1_CALI_CK_SEL_MASK BIT(5) 2731 + #define PWR1_ASM_CON1_GASRC2_CALI_CK_SEL_MASK BIT(20) 2732 + #define PWR1_ASM_CON1_GASRC3_CALI_CK_SEL_MASK BIT(23) 2733 + 2734 + /* PWR1_ASM_CON2 */ 2735 + #define PWR1_ASM_CON2_GASRC4_CALI_CK_SEL_MASK BIT(2) 2736 + #define PWR1_ASM_CON2_GASRC5_CALI_CK_SEL_MASK BIT(7) 2737 + #define PWR1_ASM_CON2_GASRC6_CALI_CK_SEL_MASK BIT(12) 2738 + #define PWR1_ASM_CON2_GASRC7_CALI_CK_SEL_MASK BIT(17) 2739 + #define PWR1_ASM_CON2_GASRC8_CALI_CK_SEL_MASK BIT(22) 2740 + #define PWR1_ASM_CON2_GASRC9_CALI_CK_SEL_MASK BIT(27) 2741 + 2742 + /* PWR1_ASM_CON3 */ 2743 + #define PWR1_ASM_CON3_GASRC10_CALI_CK_SEL_MASK BIT(2) 2744 + #define PWR1_ASM_CON3_GASRC11_CALI_CK_SEL_MASK BIT(7) 2745 + 2746 + /* AUDIO_TOP_CON0 */ 2747 + #define AUDIO_TOP_CON0_PDN_AFE BIT(2) 2748 + #define AUDIO_TOP_CON0_PDN_APLL BIT(23) 2749 + #define AUDIO_TOP_CON0_PDN_APLL_TUNER BIT(19) 2750 + #define AUDIO_TOP_CON0_PDN_APLL2 BIT(24) 2751 + #define AUDIO_TOP_CON0_PDN_APLL2_TUNER BIT(20) 2752 + #define AUDIO_TOP_CON0_PDN_DAC BIT(25) 2753 + #define AUDIO_TOP_CON0_PDN_DAC_HIRES BIT(31) 2754 + #define AUDIO_TOP_CON0_PDN_DAC_PREDIS BIT(26) 2755 + #define AUDIO_TOP_CON0_PDN_SPDIFIN_TUNER BIT(10) 2756 + #define AUDIO_TOP_CON0_PDN_ADC BIT(28) 2757 + #define AUDIO_TOP_CON0_PDN_SPDF BIT(21) 2758 + #define AUDIO_TOP_CON0_PDN_TML BIT(27) 2759 + #define AUDIO_TOP_CON0_PDN_UL_TML BIT(18) 2760 + 2761 + /* AUDIO_TOP_CON1 */ 2762 + #define AUDIO_TOP_CON1_PDN_ADC_HIRES BIT(17) 2763 + #define AUDIO_TOP_CON1_PDN_ADDA6_ADC BIT(18) 2764 + #define AUDIO_TOP_CON1_PDN_ADDA6_HIRES BIT(19) 2765 + #define AUDIO_TOP_CON1_PDN_UL_TML_HIRES BIT(16) 2766 + #define AUDIO_TOP_CON1_PDN_DMIC_TML BIT(14) 2767 + #define AUDIO_TOP_CON1_PDN_A1SYS_HOPING BIT(2) 2768 + #define AUDIO_TOP_CON1_PDN_DMIC0 BIT(10) 2769 + #define AUDIO_TOP_CON1_PDN_DMIC1 BIT(11) 2770 + #define AUDIO_TOP_CON1_PDN_DMIC2 BIT(12) 2771 + #define AUDIO_TOP_CON1_PDN_DMIC3 BIT(13) 2772 + 2773 + /* AUDIO_TOP_CON3 */ 2774 + #define AUDIO_TOP_CON3_PDN_EARC_TUNER BIT(7) 2775 + #define AUDIO_TOP_CON3_PDN_LINEIN_TUNER BIT(5) 2776 + 2777 + /* AUDIO_TOP_CON4 */ 2778 + #define AUDIO_TOP_CON4_PDN_I2S_IN BIT(0) 2779 + #define AUDIO_TOP_CON4_PDN_TDM_IN BIT(1) 2780 + #define AUDIO_TOP_CON4_PDN_I2S_OUT BIT(6) 2781 + #define AUDIO_TOP_CON4_PDN_TDM_OUT BIT(7) 2782 + #define AUDIO_TOP_CON4_PDN_HDMI_OUT BIT(8) 2783 + #define AUDIO_TOP_CON4_PDN_ASRC11 BIT(16) 2784 + #define AUDIO_TOP_CON4_PDN_ASRC12 BIT(17) 2785 + #define AUDIO_TOP_CON4_PDN_A1SYS BIT(21) 2786 + #define AUDIO_TOP_CON4_PDN_A2SYS BIT(22) 2787 + #define AUDIO_TOP_CON4_PDN_A3SYS BIT(30) 2788 + #define AUDIO_TOP_CON4_PDN_A4SYS BIT(31) 2789 + #define AUDIO_TOP_CON4_PDN_PCMIF BIT(24) 2790 + #define AUDIO_TOP_CON4_PDN_INTDIR BIT(20) 2791 + #define AUDIO_TOP_CON4_PDN_MULTI_IN BIT(19) 2792 + 2793 + /* AUDIO_TOP_CON6 */ 2794 + #define AUDIO_TOP_CON6_PDN_GASRC11 BIT(11) 2795 + #define AUDIO_TOP_CON6_PDN_GASRC10 BIT(10) 2796 + #define AUDIO_TOP_CON6_PDN_GASRC9 BIT(9) 2797 + #define AUDIO_TOP_CON6_PDN_GASRC8 BIT(8) 2798 + #define AUDIO_TOP_CON6_PDN_GASRC7 BIT(7) 2799 + #define AUDIO_TOP_CON6_PDN_GASRC6 BIT(6) 2800 + #define AUDIO_TOP_CON6_PDN_GASRC5 BIT(5) 2801 + #define AUDIO_TOP_CON6_PDN_GASRC4 BIT(4) 2802 + #define AUDIO_TOP_CON6_PDN_GASRC3 BIT(3) 2803 + #define AUDIO_TOP_CON6_PDN_GASRC2 BIT(2) 2804 + #define AUDIO_TOP_CON6_PDN_GASRC1 BIT(1) 2805 + #define AUDIO_TOP_CON6_PDN_GASRC0 BIT(0) 2806 + 2807 + /* AFE_GAINx_CON0 */ 2808 + #define AFE_GAIN_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8) 2809 + #define AFE_GAIN_CON0_GAIN_MODE_MASK GENMASK(7, 3) 2810 + #define AFE_GAIN_CON0_GAIN_ON_MASK BIT(0) 2811 + 2812 + /* AFE_GAINx_CON1 */ 2813 + #define AFE_GAIN_CON1_TARGET_MASK GENMASK(19, 0) 2814 + 2815 + /* AFE_GAINx_CON2 */ 2816 + #define AFE_GAIN_CON2_DOWN_STEP_MASK GENMASK(19, 0) 2817 + 2818 + /* AFE_GAINx_CON3 */ 2819 + #define AFE_GAIN_CON3_UP_STEP_MASK GENMASK(19, 0) 2820 + 2821 + /* AFE_GAINx_CUR */ 2822 + #define AFE_GAIN_CUR_GAIN_MASK GENMASK(19, 0) 2823 + 2824 + /* ASYS_TOP_CON */ 2825 + #define ASYS_TOP_CON_A1SYS_TIMING_ON BIT(0) 2826 + #define ASYS_TOP_CON_A2SYS_TIMING_ON BIT(1) 2827 + #define ASYS_TOP_CON_A3SYS_TIMING_ON BIT(4) 2828 + #define ASYS_TOP_CON_A4SYS_TIMING_ON BIT(5) 2829 + #define ASYS_TOP_CON_26M_TIMING_ON BIT(2) 2830 + 2831 + /* PWR2_TOP_CON0 */ 2832 + #define PWR2_TOP_CON_DMIC8_SRC_SEL_MASK GENMASK(31, 29) 2833 + #define PWR2_TOP_CON_DMIC7_SRC_SEL_MASK GENMASK(28, 26) 2834 + #define PWR2_TOP_CON_DMIC6_SRC_SEL_MASK GENMASK(25, 23) 2835 + #define PWR2_TOP_CON_DMIC5_SRC_SEL_MASK GENMASK(22, 20) 2836 + #define PWR2_TOP_CON_DMIC4_SRC_SEL_MASK GENMASK(19, 17) 2837 + #define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK GENMASK(16, 14) 2838 + #define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK GENMASK(13, 11) 2839 + #define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK GENMASK(10, 8) 2840 + 2841 + /* PWR2_TOP_CON1 */ 2842 + #define PWR2_TOP_CON1_DMIC_CKDIV_ON BIT(1) 2843 + 2844 + /* PCM_INTF_CON1 */ 2845 + #define PCM_INTF_CON1_SYNC_OUT_INV BIT(23) 2846 + #define PCM_INTF_CON1_BCLK_OUT_INV BIT(22) 2847 + #define PCM_INTF_CON1_CLK_OUT_INV_MASK GENMASK(23, 22) 2848 + #define PCM_INTF_CON1_SYNC_IN_INV BIT(21) 2849 + #define PCM_INTF_CON1_BCLK_IN_INV BIT(20) 2850 + #define PCM_INTF_CON1_CLK_IN_INV_MASK GENMASK(21, 20) 2851 + #define PCM_INTF_CON1_PCM_24BIT BIT(16) 2852 + #define PCM_INTF_CON1_PCM_16BIT (0 << 16) 2853 + #define PCM_INTF_CON1_PCM_BIT_MASK BIT(16) 2854 + #define PCM_INTF_CON1_PCM_WLEN_32BCK (0 << 14) 2855 + #define PCM_INTF_CON1_PCM_WLEN_64BCK BIT(14) 2856 + #define PCM_INTF_CON1_PCM_WLEN_MASK BIT(14) 2857 + #define PCM_INTF_CON1_SYNC_LENGTH_MASK GENMASK(13, 9) 2858 + #define PCM_INTF_CON1_PCM_SLAVE BIT(5) 2859 + #define PCM_INTF_CON1_PCM_MASTER (0 << 5) 2860 + #define PCM_INTF_CON1_PCM_M_S_MASK BIT(5) 2861 + #define PCM_INTF_CON1_PCM_MODE_MASK GENMASK(4, 3) 2862 + #define PCM_INTF_CON1_PCM_FMT_MASK GENMASK(2, 1) 2863 + #define PCM_INTF_CON1_PCM_EN BIT(0) 2864 + 2865 + /* PCM_INTF_CON2 */ 2866 + #define PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK GENMASK(24, 23) 2867 + #define PCM_INTF_CON2_SYNC_FREQ_MODE_MASK GENMASK(16, 12) 2868 + #define PCM_INTF_CON2_PCM_TX2RX_LPBK BIT(8) 2869 + 2870 + /* AFE_MPHONE_MULTIx_CON0 */ 2871 + #define AFE_MPHONE_MULTI_CON0_16BIT_SWAP BIT(3) 2872 + #define AFE_MPHONE_MULTI_CON0_16BIT_SWAP_MASK BIT(3) 2873 + #define AFE_MPHONE_MULTI_CON0_24BIT_DATA (0x1 << 1) 2874 + #define AFE_MPHONE_MULTI_CON0_16BIT_DATA (0x0 << 1) 2875 + #define AFE_MPHONE_MULIT_CON0_24BIT_DATA_MASK BIT(1) 2876 + #define AFE_MPHONE_MULTI_CON0_EN BIT(0) 2877 + 2878 + /* AFE_MPHONE_MULTIx_CON1 */ 2879 + #define AFE_MPHONE_MULTI_CON1_SYNC_ON BIT(24) 2880 + #define AFE_MPHONE_MULTI_CON1_24BIT_SWAP_BYPASS BIT(22) 2881 + #define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE (0x1 << 19) 2882 + #define AFE_MPHONE_MULTI_CON1_COMPACT_MODE (0x0 << 19) 2883 + #define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE_MASK BIT(19) 2884 + #define AFE_MPHONE_MULTI_CON1_HBR_MODE BIT(18) 2885 + #define AFE_MPHONE_MULTI_CON1_LRCK_32_CYCLE (0x2 << 16) 2886 + #define AFE_MPHONE_MULTI_CON1_LRCK_24_CYCLE (0x1 << 16) 2887 + #define AFE_MPHONE_MULTI_CON1_LRCK_16_CYCLE (0x0 << 16) 2888 + #define AFE_MPHONE_MULTI_CON1_LRCK_CYCLE_SEL_MASK GENMASK(17, 16) 2889 + #define AFE_MPHONE_MULTI_CON1_LRCK_INV BIT(15) 2890 + #define AFE_MPHONE_MULTI_CON1_DELAY_DATA BIT(14) 2891 + #define AFE_MPHONE_MULTI_CON1_LEFT_ALIGN BIT(13) 2892 + #define AFE_MPHONE_MULTI_CON1_BIT_NUM_MASK GENMASK(12, 8) 2893 + #define AFE_MPHONE_MULTI_CON1_BCK_INV BIT(6) 2894 + #define AFE_MPHONE_MULTI_CON1_CH_NUM_MASK GENMASK(1, 0) 2895 + 2896 + /* AFE_MPHONE_MULTIx_CON2 */ 2897 + #define AFE_MPHONE_MULTI_CON2_SEL_SPDIFIN BIT(19) 2898 + /* AFE_AUD_PAD_TOP */ 2899 + #define RG_RX_PROTOCOL2 BIT(3) 2900 + #define RG_RX_FIFO_ON BIT(0) 2901 + 2902 + /* AFE_ADDA_MTKAIF_CFG0 */ 2903 + #define MTKAIF_RXIF_CLKINV_ADC BIT(31) 2904 + #define MTKAIF_RXIF_PROTOCOL2 BIT(16) 2905 + #define MTKAIF_TXIF_PROTOCOL2 BIT(4) 2906 + #define MTKAIF_TXIF_8TO5 BIT(2) 2907 + #define MTKAIF_RXIF_8TO5 BIT(1) 2908 + #define MTKAIF_IF_LOOPBACK1 BIT(0) 2909 + 2910 + /* AFE_ADDA_MTKAIF_RX_CFG2 */ 2911 + #define MTKAIF_RXIF_DELAY_CYCLE_MASK GENMASK(15, 12) 2912 + #define MTKAIF_RXIF_DELAY_DATA BIT(8) 2913 + 2914 + /* AFE_ADDA_MTKAIF_SYNCWORD_CFG */ 2915 + #define ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE BIT(23) 2916 + 2917 + /* AFE_DMICx_UL_SRC_CON0 */ 2918 + #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH1(x) (((x) & 0x7) << 27) 2919 + #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(x) (((x) & 0x7) << 24) 2920 + #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK GENMASK(29, 24) 2921 + #define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL BIT(23) 2922 + #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL BIT(22) 2923 + #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL BIT(21) 2924 + 2925 + #define AFE_DMIC_UL_VOICE_MODE_MASK GENMASK(19, 17) 2926 + #define AFE_DMIC_UL_CON0_VOCIE_MODE_8K AFE_DMIC_UL_VOICE_MODE(0) 2927 + #define AFE_DMIC_UL_CON0_VOCIE_MODE_16K AFE_DMIC_UL_VOICE_MODE(1) 2928 + #define AFE_DMIC_UL_CON0_VOCIE_MODE_32K AFE_DMIC_UL_VOICE_MODE(2) 2929 + #define AFE_DMIC_UL_CON0_VOCIE_MODE_48K AFE_DMIC_UL_VOICE_MODE(3) 2930 + #define AFE_DMIC_UL_CON0_VOCIE_MODE_96K AFE_DMIC_UL_VOICE_MODE(4) 2931 + #define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK GENMASK(9, 7) 2932 + #define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL BIT(10) 2933 + #define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL BIT(1) 2934 + #define AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL BIT(0) 2935 + 2936 + /* DMIC_BYPASS_HW_GAIN */ 2937 + #define DMIC_BYPASS_HW_GAIN4_ONE_HEART BIT(10) 2938 + #define DMIC_BYPASS_HW_GAIN3_ONE_HEART BIT(9) 2939 + #define DMIC_BYPASS_HW_GAIN2_ONE_HEART BIT(8) 2940 + #define DMIC_BYPASS_HW_GAIN_DMIC4_BYPASS BIT(4) 2941 + #define DMIC_BYPASS_HW_GAIN_DMIC3_BYPASS BIT(3) 2942 + #define DMIC_BYPASS_HW_GAIN_DMIC2_BYPASS BIT(2) 2943 + #define DMIC_BYPASS_HW_GAIN_DMIC1_BYPASS BIT(1) 2944 + 2945 + /* DMIC_GAINx_CON0 */ 2946 + #define DMIC_GAIN_CON0_GAIN_ON BIT(0) 2947 + #define DMIC_GAIN_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8) 2948 + 2949 + /* DMIC_GAINx_CON1 */ 2950 + #define DMIC_GAIN_CON1_TARGET_MASK GENMASK(27, 0) 2951 + 2952 + /* DMIC_GAINx_CON2 */ 2953 + #define DMIC_GAIN_CON2_DOWN_STEP GENMASK(19, 0) 2954 + 2955 + /* DMIC_GAINx_CON3 */ 2956 + #define DMIC_GAIN_CON3_UP_STEP GENMASK(19, 0) 2957 + 2958 + /* DMIC_GAINx_CUR */ 2959 + #define DMIC_GAIN_CUR_GAIN_MASK GENMASK(27, 0) 2960 + 2961 + /* ETDM_INx_AFIFO_CON */ 2962 + #define ETDM_IN_USE_AFIFO BIT(8) 2963 + #define ETDM_IN_AFIFO_CLOCK_MASK GENMASK(7, 5) 2964 + #define ETDM_IN_AFIFO_MODE_MASK GENMASK(4, 0) 2965 + 2966 + /* ETDM_COWORK_CON0 */ 2967 + #define ETDM_OUT1_SLAVE_SEL_MASK GENMASK(23, 20) 2968 + #define ETDM_OUT1_SLAVE_SEL_SHIFT 20 2969 + #define ETDM_OUT1_SYNC_SEL_MASK GENMASK(19, 16) 2970 + #define ETDM_OUT1_SYNC_SEL_SHIFT 16 2971 + 2972 + /* ETDM_COWORK_CON1 */ 2973 + #define ETDM_IN1_SDATA_SEL_MASK GENMASK(23, 20) 2974 + #define ETDM_IN1_SDATA_SEL_SHIFT 20 2975 + #define ETDM_IN1_SDATA0_SEL_MASK GENMASK(19, 16) 2976 + #define ETDM_IN1_SDATA0_SEL_SHIFT 16 2977 + #define ETDM_IN1_SYNC_SEL_MASK GENMASK(15, 12) 2978 + #define ETDM_IN1_SYNC_SEL_SHIFT 12 2979 + #define ETDM_IN1_SLAVE_SEL_MASK GENMASK(11, 8) 2980 + #define ETDM_IN1_SLAVE_SEL_SHIFT 8 2981 + 2982 + /* ETDM_COWORK_CON2 */ 2983 + #define ETDM_IN2_SYNC_SEL_MASK GENMASK(31, 28) 2984 + #define ETDM_IN2_SYNC_SEL_SHIFT 28 2985 + #define ETDM_IN2_SLAVE_SEL_MASK GENMASK(27, 24) 2986 + #define ETDM_IN2_SLAVE_SEL_SHIFT 24 2987 + #define ETDM_OUT3_SLAVE_SEL_MASK GENMASK(23, 20) 2988 + #define ETDM_OUT3_SLAVE_SEL_SHIFT 20 2989 + #define ETDM_OUT3_SYNC_SEL_MASK GENMASK(19, 16) 2990 + #define ETDM_OUT3_SYNC_SEL_SHIFT 16 2991 + #define ETDM_OUT2_SLAVE_SEL_MASK GENMASK(11, 8) 2992 + #define ETDM_OUT2_SLAVE_SEL_SHIFT 8 2993 + #define ETDM_OUT2_SYNC_SEL_MASK GENMASK(7, 4) 2994 + #define ETDM_OUT2_SYNC_SEL_SHIFT 4 2995 + 2996 + /* ETDM_COWORK_CON3 */ 2997 + #define ETDM_IN2_SDATA_SEL_MASK GENMASK(7, 4) 2998 + #define ETDM_IN2_SDATA_SEL_SHIFT 4 2999 + #define ETDM_IN2_SDATA0_SEL_MASK GENMASK(3, 0) 3000 + #define ETDM_IN2_SDATA0_SEL_SHIFT 0 3001 + 3002 + /* ETDM_x_CONx */ 3003 + #define ETDM_CON0_CH_NUM_MASK GENMASK(27, 23) 3004 + #define ETDM_CON0_WORD_LEN_MASK GENMASK(20, 16) 3005 + #define ETDM_CON0_BIT_LEN_MASK GENMASK(15, 11) 3006 + #define ETDM_CON0_FORMAT_MASK GENMASK(8, 6) 3007 + #define ETDM_CON0_SLAVE_MODE BIT(5) 3008 + #define ETDM_CON0_SYNC_MODE BIT(1) 3009 + #define ETDM_CON0_EN BIT(0) 3010 + 3011 + #define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28) 3012 + 3013 + #define ETDM_CON1_MCLK_OUTPUT BIT(16) 3014 + 3015 + #define ETDM_IN_CON1_LRCK_AUTO_MODE BIT(31) 3016 + #define ETDM_IN_CON1_LRCK_WIDTH_MASK GENMASK(29, 20) 3017 + 3018 + #define ETDM_OUT_CON1_LRCK_AUTO_MODE BIT(29) 3019 + #define ETDM_OUT_CON1_LRCK_WIDTH_MASK GENMASK(28, 19) 3020 + 3021 + #define ETDM_IN_CON2_MULTI_IP_2CH_MODE BIT(31) 3022 + #define ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK GENMASK(19, 15) 3023 + #define ETDM_IN_CON2_CLOCK_MASK GENMASK(12, 10) 3024 + #define ETDM_IN_CON2_CLOCK_SHIFT 10 3025 + #define ETDM_IN_CON2_UPDATE_GAP_MASK GENMASK(9, 5) 3026 + 3027 + #define ETDM_OUT_CON2_LRCK_DELAY_BCK_INV BIT(30) 3028 + #define ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN BIT(29) 3029 + 3030 + #define ETDM_IN_CON3_FS_MASK GENMASK(30, 26) 3031 + #define ETDM_IN_CON3_DISABLE_OUT(x) BIT(((x) & 0xffff)) 3032 + #define ETDM_IN_CON3_DISABLE_OUT_MASK GENMASK(15, 0) 3033 + 3034 + #define ETDM_IN_CON4_MASTER_LRCK_INV BIT(19) 3035 + #define ETDM_IN_CON4_MASTER_BCK_INV BIT(18) 3036 + #define ETDM_IN_CON4_SLAVE_LRCK_INV BIT(17) 3037 + #define ETDM_IN_CON4_SLAVE_BCK_INV BIT(16) 3038 + 3039 + #define ETDM_OUT_CON4_RELATCH_EN_MASK GENMASK(28, 24) 3040 + #define ETDM_OUT_CON4_CLOCK_MASK GENMASK(8, 6) 3041 + #define ETDM_OUT_CON4_CLOCK_SHIFT 6 3042 + #define ETDM_OUT_CON4_FS_MASK GENMASK(4, 0) 3043 + 3044 + #define ETDM_IN_CON5_LR_SWAP(x) BIT(((x) & 0xffff) + 16) 3045 + #define ETDM_IN_CON5_LR_SWAP_MASK GENMASK(31, 16) 3046 + #define ETDM_IN_CON5_ENABLE_ODD(x) BIT(((x) & 0xffff)) 3047 + #define ETDM_IN_CON5_ENABLE_ODD_MASK GENMASK(15, 0) 3048 + 3049 + #define ETDM_OUT_CON5_MASTER_LRCK_INV BIT(10) 3050 + #define ETDM_OUT_CON5_MASTER_BCK_INV BIT(9) 3051 + #define ETDM_OUT_CON5_SLAVE_LRCK_INV BIT(8) 3052 + #define ETDM_OUT_CON5_SLAVE_BCK_INV BIT(7) 3053 + 3054 + /* GASRC_TIMING_CON0 */ 3055 + #define GASRC_TIMING_CON0_GASRC0_IN_MODE_MASK GENMASK(4, 0) 3056 + #define GASRC_TIMING_CON0_GASRC1_IN_MODE_MASK GENMASK(9, 5) 3057 + #define GASRC_TIMING_CON0_GASRC2_IN_MODE_MASK GENMASK(14, 10) 3058 + #define GASRC_TIMING_CON0_GASRC3_IN_MODE_MASK GENMASK(19, 15) 3059 + #define GASRC_TIMING_CON0_GASRC4_IN_MODE_MASK GENMASK(24, 20) 3060 + #define GASRC_TIMING_CON0_GASRC5_IN_MODE_MASK GENMASK(29, 25) 3061 + 3062 + /* GASRC_TIMING_CON1 */ 3063 + #define GASRC_TIMING_CON1_GASRC6_IN_MODE_MASK GENMASK(4, 0) 3064 + #define GASRC_TIMING_CON1_GASRC7_IN_MODE_MASK GENMASK(9, 5) 3065 + #define GASRC_TIMING_CON1_GASRC8_IN_MODE_MASK GENMASK(14, 10) 3066 + #define GASRC_TIMING_CON1_GASRC9_IN_MODE_MASK GENMASK(19, 15) 3067 + #define GASRC_TIMING_CON1_GASRC10_IN_MODE_MASK GENMASK(24, 20) 3068 + #define GASRC_TIMING_CON1_GASRC11_IN_MODE_MASK GENMASK(29, 25) 3069 + 3070 + /* GASRC_TIMING_CON2 */ 3071 + #define GASRC_TIMING_CON2_GASRC12_IN_MODE_MASK GENMASK(4, 0) 3072 + #define GASRC_TIMING_CON2_GASRC13_IN_MODE_MASK GENMASK(9, 5) 3073 + #define GASRC_TIMING_CON2_GASRC14_IN_MODE_MASK GENMASK(14, 10) 3074 + #define GASRC_TIMING_CON2_GASRC15_IN_MODE_MASK GENMASK(19, 15) 3075 + #define GASRC_TIMING_CON2_GASRC16_IN_MODE_MASK GENMASK(24, 20) 3076 + #define GASRC_TIMING_CON2_GASRC17_IN_MODE_MASK GENMASK(29, 25) 3077 + 3078 + /* GASRC_TIMING_CON3 */ 3079 + #define GASRC_TIMING_CON3_GASRC18_IN_MODE_MASK GENMASK(4, 0) 3080 + #define GASRC_TIMING_CON3_GASRC19_IN_MODE_MASK GENMASK(9, 5) 3081 + 3082 + /* GASRC_TIMING_CON4 */ 3083 + #define GASRC_TIMING_CON4_GASRC0_OUT_MODE_MASK GENMASK(4, 0) 3084 + #define GASRC_TIMING_CON4_GASRC1_OUT_MODE_MASK GENMASK(9, 5) 3085 + #define GASRC_TIMING_CON4_GASRC2_OUT_MODE_MASK GENMASK(14, 10) 3086 + #define GASRC_TIMING_CON4_GASRC3_OUT_MODE_MASK GENMASK(19, 15) 3087 + #define GASRC_TIMING_CON4_GASRC4_OUT_MODE_MASK GENMASK(24, 20) 3088 + #define GASRC_TIMING_CON4_GASRC5_OUT_MODE_MASK GENMASK(29, 25) 3089 + 3090 + /* GASRC_TIMING_CON5 */ 3091 + #define GASRC_TIMING_CON5_GASRC6_OUT_MODE_MASK GENMASK(4, 0) 3092 + #define GASRC_TIMING_CON5_GASRC7_OUT_MODE_MASK GENMASK(9, 5) 3093 + #define GASRC_TIMING_CON5_GASRC8_OUT_MODE_MASK GENMASK(14, 10) 3094 + #define GASRC_TIMING_CON5_GASRC9_OUT_MODE_MASK GENMASK(19, 15) 3095 + #define GASRC_TIMING_CON5_GASRC10_OUT_MODE_MASK GENMASK(24, 20) 3096 + #define GASRC_TIMING_CON5_GASRC11_OUT_MODE_MASK GENMASK(29, 25) 3097 + 3098 + /* AFE_DPTX_CON */ 3099 + #define AFE_DPTX_CON_CH_EN_2CH GENMASK(9, 8) 3100 + #define AFE_DPTX_CON_CH_EN_4CH GENMASK(11, 8) 3101 + #define AFE_DPTX_CON_CH_EN_6CH GENMASK(13, 8) 3102 + #define AFE_DPTX_CON_CH_EN_8CH GENMASK(15, 8) 3103 + #define AFE_DPTX_CON_CH_EN_MASK GENMASK(15, 8) 3104 + #define AFE_DPTX_CON_16BIT (0x1 << 2) 3105 + #define AFE_DPTX_CON_24BIT (0x0 << 2) 3106 + #define AFE_DPTX_CON_16BIT_MASK BIT(2) 3107 + #define AFE_DPTX_CON_CH_NUM_2CH (0x0 << 1) 3108 + #define AFE_DPTX_CON_CH_NUM_8CH (0x1 << 1) 3109 + #define AFE_DPTX_CON_CH_NUM_MASK BIT(1) 3110 + #define AFE_DPTX_CON_ON BIT(0) 3111 + 3112 + /* AFE_ADDA_DL_SRC2_CON0 */ 3113 + #define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28) 3114 + #define DL_2_CH1_SATURATION_EN_CTL BIT(27) 3115 + #define DL_2_CH2_SATURATION_EN_CTL BIT(26) 3116 + #define DL_2_MUTE_CH1_OFF_CTL_PRE BIT(12) 3117 + #define DL_2_MUTE_CH2_OFF_CTL_PRE BIT(11) 3118 + #define DL_2_VOICE_MODE_CTL_PRE BIT(5) 3119 + #define DL_2_GAIN_ON_CTL_PRE_SHIFT 1 3120 + #define DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT 0 3121 + 3122 + /* AFE_ADDA_DL_SRC2_CON1 */ 3123 + #define DL_2_GAIN_CTL_PRE_MASK GENMASK(31, 16) 3124 + #define DL_2_GAIN_CTL_PRE_SHIFT 16 3125 + 3126 + /* AFE_ADDA_TOP_CON0 */ 3127 + #define C_LOOPBACK_MODE_CTL_MASK GENMASK(15, 12) 3128 + #define DL_INPUT_FROM_SINEGEN (4 << 12) 3129 + 3130 + /* AFE_ADDA_UL_DL_CON0 */ 3131 + #define ADDA_AFE_ON_SHIFT 0 3132 + 3133 + /* AFE_ADDA_DL_SDM_DCCOMP_CON */ 3134 + #define DL_USE_NEW_2ND_SDM BIT(30) 3135 + #define ATTGAIN_CTL_MASK GENMASK(5, 0) 3136 + 3137 + /* AFE_ADDA_UL_SRC_CON0 */ 3138 + #define UL_MODE_3P25M_CH2_CTL BIT(22) 3139 + #define UL_MODE_3P25M_CH1_CTL BIT(21) 3140 + #define UL_VOICE_MODE_CTL_MASK GENMASK(19, 17) 3141 + #define UL_LOOPBACK_MODE_CTL BIT(2) 3142 + #define UL_SDM3_LEVEL_CTL BIT(1) 3143 + #define UL_SRC_ON_TMP_CTL_SHIFT 0 3144 + 3145 + /* AFE_GASRCx_NEW_CON0 */ 3146 + #define AFE_GASRC_NEW_CON0_ONE_HEART BIT(31) 3147 + #define AFE_GASRC_NEW_CON0_CHSET0_CLR_IIR_HISTORY BIT(17) 3148 + #define AFE_GASRC_NEW_CON0_CHSET0_OFS_SEL_MASK GENMASK(15, 14) 3149 + #define AFE_GASRC_NEW_CON0_CHSET0_OFS_SEL_TX (0 << 14) 3150 + #define AFE_GASRC_NEW_CON0_CHSET0_OFS_SEL_RX BIT(14) 3151 + #define AFE_GASRC_NEW_CON0_CHSET0_IFS_SEL_MASK GENMASK(13, 12) 3152 + #define AFE_GASRC_NEW_CON0_CHSET0_IFS_SEL_TX (3 << 12) 3153 + #define AFE_GASRC_NEW_CON0_CHSET0_IFS_SEL_RX (2 << 12) 3154 + #define AFE_GASRC_NEW_CON0_CHSET0_IIR_EN BIT(11) 3155 + #define AFE_GASRC_NEW_CON0_CHSET0_IIR_STAGE_MASK GENMASK(10, 8) 3156 + #define AFE_GASRC_NEW_CON0_CHSET_STR_CLR BIT(4) 3157 + #define AFE_GASRC_NEW_CON0_COEFF_SRAM_CTRL BIT(1) 3158 + #define AFE_GASRC_NEW_CON0_ASM_ON BIT(0) 3159 + 3160 + /* AFE_GASRCx_NEW_CON5 */ 3161 + #define AFE_GASRC_NEW_CON5_CALI_LRCK_SEL_MASK GENMASK(3, 1) 3162 + #define AFE_GASRC_NEW_CON5_SOFT_RESET BIT(0) 3163 + 3164 + /* AFE_GASRCx_NEW_CON6 */ 3165 + #define AFE_GASRC_NEW_CON6_FREQ_CALI_CYCLE_MASK GENMASK(31, 16) 3166 + #define AFE_GASRC_NEW_CON6_AUTO_TUNE_FREQ3 BIT(12) 3167 + #define AFE_GASRC_NEW_CON6_COMP_FREQ_RES_EN BIT(11) 3168 + #define AFE_GASRC_NEW_CON6_CALI_SIG_MUX_SEL_MASK GENMASK(9, 8) 3169 + #define AFE_GASRC_NEW_CON6_FREQ_CALI_BP_DGL BIT(7) 3170 + #define AFE_GASRC_NEW_CON6_AUTO_TUNE_FREQ2 BIT(3) 3171 + #define AFE_GASRC_NEW_CON6_FREQ_CALI_AUTO_RESTART BIT(2) 3172 + #define AFE_GASRC_NEW_CON6_CALI_USE_FREQ_OUT BIT(1) 3173 + #define AFE_GASRC_NEW_CON6_CALI_EN BIT(0) 3174 + 3175 + /* AFE_GASRCx_NEW_CON7 */ 3176 + #define AFE_GASRC_NEW_CON7_FREQ_CALC_DENOMINATOR_MASK GENMASK(23, 0) 3177 + #define AFE_GASRC_NEW_CON7_FREQ_CALC_DENOMINATOR_49M (0x3c00) 3178 + #define AFE_GASRC_NEW_CON7_FREQ_CALC_DENOMINATOR_45M (0x3720) 3179 + 3180 + #endif