tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits

Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tom St Denis and committed by
Alex Deucher 8d7fb7a1 651a1465

+109 -5
+2 -1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
··· 21 21 #ifndef _gc_10_1_0_OFFSET_HEADER 22 22 #define _gc_10_1_0_OFFSET_HEADER 23 23 24 - 24 + #define mmSQ_DEBUG_STS_GLOBAL 0x2309 25 + #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 25 26 26 27 // addressBlock: gc_sdma0_sdma0dec 27 28 // base address: 0x4980
+16
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
··· 42546 42546 42547 42547 42548 42548 // addressBlock: sqind 42549 + //SQ_DEBUG_STS_GLOBAL 42550 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 42551 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 42552 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 42553 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 42554 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L 42555 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 42556 + #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 42557 + #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 42558 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 42559 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 42560 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L 42561 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 42562 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L 42563 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 42564 + 42549 42565 //SQ_DEBUG_STS_LOCAL 42550 42566 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 42551 42567 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+2 -1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
··· 22 22 #ifndef _gc_10_3_0_OFFSET_HEADER 23 23 #define _gc_10_3_0_OFFSET_HEADER 24 24 25 - 25 + #define mmSQ_DEBUG_STS_GLOBAL 0x2309 26 + #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 26 27 27 28 // addressBlock: gc_sdma0_sdma0dec 28 29 // base address: 0x4980
+16
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
··· 46269 46269 46270 46270 46271 46271 // addressBlock: sqind 46272 + //SQ_DEBUG_STS_GLOBAL 46273 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 46274 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 46275 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 46276 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 46277 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L 46278 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 46279 + #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 46280 + #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 46281 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 46282 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 46283 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L 46284 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 46285 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L 46286 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 46287 + 46272 46288 //SQ_DEBUG_STS_LOCAL 46273 46289 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 46274 46290 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+3 -1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
··· 21 21 #ifndef _gc_9_0_OFFSET_HEADER 22 22 #define _gc_9_0_OFFSET_HEADER 23 23 24 - 24 + #define mmSQ_DEBUG_STS_GLOBAL 0x2309 25 + #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 26 + #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 25 27 26 28 // addressBlock: gc_grbmdec 27 29 // base address: 0x8000
+22
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
··· 28350 28350 28351 28351 28352 28352 // addressBlock: sqind 28353 + //SQ_DEBUG_STS_GLOBAL 28354 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 28355 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 28356 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 28357 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 28358 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L 28359 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 28360 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L 28361 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 28362 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL 28363 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 28364 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L 28365 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 28366 + #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 28367 + #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 28368 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 28369 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 28370 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L 28371 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 28372 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L 28373 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 28374 + 28353 28375 //SQ_DEBUG_STS_LOCAL 28354 28376 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 28355 28377 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+3 -1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
··· 21 21 #ifndef _gc_9_1_OFFSET_HEADER 22 22 #define _gc_9_1_OFFSET_HEADER 23 23 24 - 24 + #define mmSQ_DEBUG_STS_GLOBAL 0x2309 25 + #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 26 + #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 25 27 26 28 // addressBlock: gc_grbmdec 27 29 // base address: 0x8000
+21
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
··· 29571 29571 29572 29572 29573 29573 // addressBlock: sqind 29574 + //SQ_DEBUG_STS_GLOBAL 29575 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 29576 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 29577 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 29578 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 29579 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L 29580 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 29581 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L 29582 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 29583 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL 29584 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 29585 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L 29586 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 29587 + #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 29588 + #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 29589 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 29590 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 29591 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L 29592 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 29593 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L 29594 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 29574 29595 //SQ_DEBUG_STS_LOCAL 29575 29596 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 29576 29597 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+3 -1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
··· 21 21 #ifndef _gc_9_2_1_OFFSET_HEADER 22 22 #define _gc_9_2_1_OFFSET_HEADER 23 23 24 - 24 + #define mmSQ_DEBUG_STS_GLOBAL 0x2309 25 + #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 26 + #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 25 27 26 28 // addressBlock: gc_grbmdec 27 29 // base address: 0x8000
+21
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
··· 29893 29893 29894 29894 29895 29895 // addressBlock: sqind 29896 + //SQ_DEBUG_STS_GLOBAL 29897 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL 29898 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 29899 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L 29900 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 29901 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L 29902 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 29903 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L 29904 + #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 29905 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL 29906 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 29907 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L 29908 + #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 29909 + #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L 29910 + #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 29911 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L 29912 + #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 29913 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L 29914 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 29915 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L 29916 + #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 29896 29917 //SQ_DEBUG_STS_LOCAL 29897 29918 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L 29898 29919 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000