[PATCH] sh: drop maskpos from make_ipr_irq(), remove duplicate irq definitions

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Clean up some of the subtype IRQ definitions for IPR IRQ, and consolidate the
make_ipr_irq() definitions by dropping maskpos. SH-4A was the only thing
interested in the maskpos, and this should be handled through INTC2 rather
than IPR.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

authored by

Paul Mundt and committed by

Linus Torvalds 20 years ago 8d27e081 50373c1b

+38 -90

4 changed files

expand all

arch

kernel

cpu

irq

ipr.c

include

asm-sh

irq-sh73180.h

irq-sh7780.h

irq.h

+29 -30

arch/sh/kernel/cpu/irq/ipr.c

··· 108 108 enable_ipr_irq(irq); 109 109 } 110 110 111 - void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, 112 - int priority, int maskpos) 111 + void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 113 112 { 114 113 disable_irq_nosync(irq); 115 114 ipr_data[irq].addr = addr; ··· 122 123 void __init init_IRQ(void) 123 124 { 124 125 #ifndef CONFIG_CPU_SUBTYPE_SH7780 125 - make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY, 0); 126 - make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY, 0); 126 + make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); 127 + make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); 127 128 #if defined(CONFIG_SH_RTC) 128 - make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY, 0); 129 + make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); 129 130 #endif 130 131 131 132 #ifdef SCI_ERI_IRQ 132 - make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); 133 - make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); 134 - make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); 133 + make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 134 + make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 135 + make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 135 136 #endif 136 137 137 138 #ifdef SCIF1_ERI_IRQ 138 - make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); 139 - make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); 140 - make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); 141 - make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); 139 + make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 140 + make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 141 + make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 142 + make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 142 143 #endif 143 144 144 145 #if defined(CONFIG_CPU_SUBTYPE_SH7300) 145 - make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY, 0); 146 - make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0); 147 - make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0); 148 - make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY, 0); 146 + make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); 147 + make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 148 + make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 149 + make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 149 150 #endif 150 151 151 152 #ifdef SCIF_ERI_IRQ 152 - make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); 153 - make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); 154 - make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); 155 - make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); 153 + make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 154 + make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 155 + make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 156 + make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 156 157 #endif 157 158 158 159 #ifdef IRDA_ERI_IRQ 159 - make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); 160 - make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); 161 - make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); 162 - make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); 160 + make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 161 + make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 162 + make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 163 + make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 163 164 #endif 164 165 165 166 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ ··· 174 175 * You should set corresponding bits of PFC to "00" 175 176 * to enable these interrupts. 176 177 */ 177 - make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY, 0); 178 - make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY, 0); 179 - make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY, 0); 180 - make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY, 0); 181 - make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY, 0); 182 - make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY, 0); 178 + make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); 179 + make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 180 + make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 181 + make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); 182 + make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); 183 + make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); 183 184 #endif 184 185 #endif 185 186

+1 -35

include/asm-sh/irq-sh73180.h

··· 25 25 #undef DMA_IPR_POS 26 26 #undef DMA_PRIORITY 27 27 28 - #undef NR_IRQS 29 - 30 - #undef __irq_demux 31 - #undef irq_demux 32 - 33 28 #undef INTC_IMCR0 34 29 #undef INTC_IMCR1 35 30 #undef INTC_IMCR2 ··· 224 229 #define SIU_IPR_POS 1 225 230 #define SIU_PRIORITY 3 226 231 227 - 228 - /* ONCHIP_NR_IRQS */ 229 - #define NR_IRQS 109 230 - 231 - /* In a generic kernel, NR_IRQS is an upper bound, and we should use 232 - * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. 233 - */ 234 - #define ACTUAL_NR_IRQS NR_IRQS 235 - 236 - 237 - extern void disable_irq(unsigned int); 238 - extern void disable_irq_nosync(unsigned int); 239 - extern void enable_irq(unsigned int); 240 - 241 - /* 242 - * Simple Mask Register Support 243 - */ 244 - extern void make_maskreg_irq(unsigned int irq); 245 - extern unsigned short *irq_mask_register; 246 - 247 - /* 248 - * Function for "on chip support modules". 249 - */ 250 - extern void make_ipr_irq(unsigned int irq, unsigned int addr, 251 - int pos, int priority); 252 - extern void make_imask_irq(unsigned int irq); 253 - 254 232 #define PORT_PACR 0xA4050100UL 255 233 #define PORT_PBCR 0xA4050102UL 256 234 #define PORT_PCCR 0xA4050104UL ··· 311 343 #define IRQ6_PRIORITY 1 312 344 #define IRQ7_PRIORITY 1 313 345 314 - extern int shmse_irq_demux(int irq); 315 - #define __irq_demux(irq) shmse_irq_demux(irq) 316 - #define irq_demux(irq) __irq_demux(irq) 346 + int shmse_irq_demux(int irq); 317 347 318 348 #endif /* __ASM_SH_IRQ_SH73180_H */

-23

include/asm-sh/irq-sh7780.h

··· 299 299 #define GPIO_IPR_POS 2 300 300 #define GPIO_PRIORITY 3 301 301 302 - /* ONCHIP_NR_IRQS */ 303 - #define NR_IRQS 150 /* 111 + 16 */ 304 - 305 - /* In a generic kernel, NR_IRQS is an upper bound, and we should use 306 - * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. 307 - */ 308 - #define ACTUAL_NR_IRQS NR_IRQS 309 - 310 - extern void disable_irq(unsigned int); 311 - extern void disable_irq_nosync(unsigned int); 312 - extern void enable_irq(unsigned int); 313 - 314 - /* 315 - * Simple Mask Register Support 316 - */ 317 - extern void make_maskreg_irq(unsigned int irq); 318 - extern unsigned short *irq_mask_register; 319 - 320 - /* 321 - * Function for "on chip support modules". 322 - */ 323 - extern void make_imask_irq(unsigned int irq); 324 - 325 302 #define INTC_TMU0_MSK 0 326 303 #define INTC_TMU3_MSK 1 327 304 #define INTC_RTC_MSK 2

+8 -2

include/asm-sh/irq.h

··· 245 245 #endif /* ST40STB1 */ 246 246 247 247 #endif /* 775x / SH4-202 / ST40STB1 */ 248 + #endif /* 7780 */ 248 249 249 250 /* NR_IRQS is made from three components: 250 251 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules ··· 275 274 # define ONCHIP_NR_IRQS 72 276 275 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 277 276 # define ONCHIP_NR_IRQS 144 278 - #elif defined(CONFIG_CPU_SUBTYPE_SH7300) 277 + #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 278 + defined(CONFIG_CPU_SUBTYPE_SH73180) 279 279 # define ONCHIP_NR_IRQS 109 280 + #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 281 + # define ONCHIP_NR_IRQS 111 280 282 #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ 281 283 # define ONCHIP_NR_IRQS 144 282 284 #endif ··· 310 306 # define OFFCHIP_NR_IRQS 96 311 307 #elif defined (CONFIG_SH_TITAN) 312 308 # define OFFCHIP_NR_IRQS 4 309 + #elif defined(CONFIG_SH_R7780RP) 310 + # define OFFCHIP_NR_IRQS 16 313 311 #elif defined(CONFIG_SH_UNKNOWN) 314 312 # define OFFCHIP_NR_IRQS 16 /* Must also be last */ 315 313 #else ··· 556 550 #define INTC_ICR_IRLM (1<<7) 557 551 #endif 558 552 559 - #else 553 + #ifdef CONFIG_CPU_SUBTYPE_SH7780 560 554 #include <asm/irq-sh7780.h> 561 555 #endif 562 556