Merge branch 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux into drm-next

+115 -12

drivers/gpu/drm/radeon/atombios.h

··· 1711 1711 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1712 1712 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1713 1713 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1714 + #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1714 1715 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1716 + #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1715 1717 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1716 1718 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1717 1719 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 ··· 2225 2223 USHORT usVoltageLevel; // real voltage level 2226 2224 }SET_VOLTAGE_PARAMETERS_V2; 2227 2225 2228 - 2226 + // used by both SetVoltageTable v1.3 and v1.4 2229 2227 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2230 2228 { 2231 2229 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI ··· 2292 2290 #define ATOM_GET_VOLTAGE_VID 0x00 2293 2291 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2294 2292 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2295 - // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2296 - #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2293 + #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2297 2294 2295 + // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2296 + #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2298 2297 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2299 2298 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2300 - // undefined power state 2299 + 2301 2300 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2302 2301 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2302 + 2303 + // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2304 + typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2305 + { 2306 + UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2307 + UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2308 + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2309 + ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2310 + }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2311 + 2312 + // New in GetVoltageInfo v1.2 ucVoltageMode 2313 + #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2314 + 2315 + // New Added from CI Hawaii for EVV feature 2316 + typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2317 + { 2318 + USHORT usVoltageLevel; // real voltage level in unit of mv 2319 + USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2320 + ULONG ulReseved; 2321 + }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2303 2322 2304 2323 /****************************************************************************/ 2305 2324 // Structures used by TVEncoderControlTable ··· 3887 3864 #define PP_AC_DC_SWITCH_GPIO_PINID 60 3888 3865 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 3889 3866 #define VDDC_VRHOT_GPIO_PINID 61 3867 + //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 3868 + #define VDDC_PCC_GPIO_PINID 62 3890 3869 3891 3870 typedef struct _ATOM_GPIO_PIN_LUT 3892 3871 { ··· 4194 4169 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4195 4170 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4196 4171 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4197 - 4172 + #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4198 4173 4199 4174 //Must be updated when new record type is added,equal to that record definition! 4200 - #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4175 + #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE 4201 4176 4202 4177 typedef struct _ATOM_I2C_RECORD 4203 4178 { ··· 4422 4397 USHORT usReserved; 4423 4398 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4424 4399 4400 + typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4401 + { 4402 + USHORT usConnectorObjectId; 4403 + UCHAR ucConnectorType; 4404 + UCHAR ucPosition; 4405 + }ATOM_CONNECTOR_LAYOUT_INFO; 4406 + 4407 + // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4408 + #define CONNECTOR_TYPE_DVI_D 1 4409 + #define CONNECTOR_TYPE_DVI_I 2 4410 + #define CONNECTOR_TYPE_VGA 3 4411 + #define CONNECTOR_TYPE_HDMI 4 4412 + #define CONNECTOR_TYPE_DISPLAY_PORT 5 4413 + #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4414 + 4415 + typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4416 + { 4417 + ATOM_COMMON_RECORD_HEADER sheader; 4418 + UCHAR ucLength; 4419 + UCHAR ucWidth; 4420 + UCHAR ucConnNum; 4421 + UCHAR ucReserved; 4422 + ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4423 + }ATOM_BRACKET_LAYOUT_RECORD; 4424 + 4425 4425 /****************************************************************************/ 4426 4426 // ASIC voltage data table 4427 4427 /****************************************************************************/ ··· 4574 4524 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4575 4525 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4576 4526 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4577 - #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4578 - #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4527 + #define VOLTAGE_OBJ_EVV 8 4528 + #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4529 + #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4579 4530 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4580 4531 4581 4532 typedef struct _VOLTAGE_LUT_ENTRY_V2 ··· 4602 4551 ULONG ulReserved; 4603 4552 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4604 4553 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4554 + 4555 + // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 4556 + #define VOLTAGE_DATA_ONE_BYTE 0 4557 + #define VOLTAGE_DATA_TWO_BYTE 1 4605 4558 4606 4559 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4607 4560 { ··· 4639 4584 // 1:0 offset trim, 4640 4585 USHORT usLoadLine_PSI; 4641 4586 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4642 - UCHAR ucReserved[2]; 4587 + UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 4588 + UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 4643 4589 ULONG ulReserved; 4644 4590 }ATOM_SVID2_VOLTAGE_OBJECT_V3; 4645 4591 ··· 4692 4636 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4693 4637 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4694 4638 }ATOM_ASIC_PROFILING_INFO_V2_1; 4639 + 4640 + typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 4641 + { 4642 + ATOM_COMMON_TABLE_HEADER asHeader; 4643 + ULONG ulEvvDerateTdp; 4644 + ULONG ulEvvDerateTdc; 4645 + ULONG ulBoardCoreTemp; 4646 + ULONG ulMaxVddc; 4647 + ULONG ulMinVddc; 4648 + ULONG ulLoadLineSlop; 4649 + ULONG ulLeakageTemp; 4650 + ULONG ulLeakageVoltage; 4651 + ULONG ulCACmEncodeRange; 4652 + ULONG ulCACmEncodeAverage; 4653 + ULONG ulCACbEncodeRange; 4654 + ULONG ulCACbEncodeAverage; 4655 + ULONG ulKt_bEncodeRange; 4656 + ULONG ulKt_bEncodeAverage; 4657 + ULONG ulKv_mEncodeRange; 4658 + ULONG ulKv_mEncodeAverage; 4659 + ULONG ulKv_bEncodeRange; 4660 + ULONG ulKv_bEncodeAverage; 4661 + ULONG ulLkgEncodeLn_MaxDivMin; 4662 + ULONG ulLkgEncodeMin; 4663 + ULONG ulEfuseLogisticAlpha; 4664 + USHORT usPowerDpm0; 4665 + USHORT usCurrentDpm0; 4666 + USHORT usPowerDpm1; 4667 + USHORT usCurrentDpm1; 4668 + USHORT usPowerDpm2; 4669 + USHORT usCurrentDpm2; 4670 + USHORT usPowerDpm3; 4671 + USHORT usCurrentDpm3; 4672 + USHORT usPowerDpm4; 4673 + USHORT usCurrentDpm4; 4674 + USHORT usPowerDpm5; 4675 + USHORT usCurrentDpm5; 4676 + USHORT usPowerDpm6; 4677 + USHORT usCurrentDpm6; 4678 + USHORT usPowerDpm7; 4679 + USHORT usCurrentDpm7; 4680 + }ATOM_ASIC_PROFILING_INFO_V3_1; 4681 + 4695 4682 4696 4683 typedef struct _ATOM_POWER_SOURCE_OBJECT 4697 4684 { ··· 5907 5808 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5908 5809 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5909 5810 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5811 + #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 5812 + #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 5910 5813 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5911 5814 5912 5815 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 ··· 6343 6242 #define _128Mx32 0x53 6344 6243 #define _256Mx8 0x61 6345 6244 #define _256Mx16 0x62 6245 + #define _512Mx8 0x71 6346 6246 6347 6247 #define SAMSUNG 0x1 6348 6248 #define INFINEON 0x2 ··· 7089 6987 UCHAR ucMaxDispEngineNum; 7090 6988 UCHAR ucMaxActiveDispEngineNum; 7091 6989 UCHAR ucMaxPPLLNum; 7092 - UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7093 - UCHAR ucReserved[3]; 7094 - ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 6990 + UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 6991 + UCHAR ucDispCaps; 6992 + UCHAR ucReserved[2]; 6993 + ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 7095 6994 }ATOM_DISP_OUT_INFO_V3; 7096 6995 7097 6996 //ucDispCaps

+18 -1

drivers/gpu/drm/radeon/atombios_crtc.c

··· 1910 1910 int i; 1911 1911 1912 1912 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1913 + if (crtc->fb) { 1914 + int r; 1915 + struct radeon_framebuffer *radeon_fb; 1916 + struct radeon_bo *rbo; 1917 + 1918 + radeon_fb = to_radeon_framebuffer(crtc->fb); 1919 + rbo = gem_to_radeon_bo(radeon_fb->obj); 1920 + r = radeon_bo_reserve(rbo, false); 1921 + if (unlikely(r)) 1922 + DRM_ERROR("failed to reserve rbo before unpin\n"); 1923 + else { 1924 + radeon_bo_unpin(rbo); 1925 + radeon_bo_unreserve(rbo); 1926 + } 1927 + } 1913 1928 /* disable the GRPH */ 1914 1929 if (ASIC_IS_DCE4(rdev)) 1915 1930 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); ··· 1955 1940 break; 1956 1941 case ATOM_PPLL0: 1957 1942 /* disable the ppll */ 1958 - if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE)) 1943 + if ((rdev->family == CHIP_ARUBA) || 1944 + (rdev->family == CHIP_BONAIRE) || 1945 + (rdev->family == CHIP_HAWAII)) 1959 1946 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1960 1947 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1961 1948 break;

+47 -11

drivers/gpu/drm/radeon/ci_dpm.c

··· 40 40 #define VOLTAGE_VID_OFFSET_SCALE1 625 41 41 #define VOLTAGE_VID_OFFSET_SCALE2 100 42 42 43 + static const struct ci_pt_defaults defaults_hawaii_xt = 44 + { 45 + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 46 + { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 47 + { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 48 + }; 49 + 50 + static const struct ci_pt_defaults defaults_hawaii_pro = 51 + { 52 + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 53 + { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, 54 + { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } 55 + }; 56 + 43 57 static const struct ci_pt_defaults defaults_bonaire_xt = 44 58 { 45 59 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, ··· 201 187 struct ci_power_info *pi = ci_get_pi(rdev); 202 188 203 189 switch (rdev->pdev->device) { 204 - case 0x6650: 205 - case 0x6658: 206 - case 0x665C: 207 - default: 190 + case 0x6650: 191 + case 0x6658: 192 + case 0x665C: 193 + default: 208 194 pi->powertune_defaults = &defaults_bonaire_xt; 209 195 break; 210 - case 0x6651: 211 - case 0x665D: 196 + case 0x6651: 197 + case 0x665D: 212 198 pi->powertune_defaults = &defaults_bonaire_pro; 213 199 break; 214 - case 0x6640: 200 + case 0x6640: 215 201 pi->powertune_defaults = &defaults_saturn_xt; 216 202 break; 217 - case 0x6641: 203 + case 0x6641: 218 204 pi->powertune_defaults = &defaults_saturn_pro; 205 + break; 206 + case 0x67B8: 207 + case 0x67B0: 208 + case 0x67A0: 209 + case 0x67A1: 210 + case 0x67A2: 211 + case 0x67A8: 212 + case 0x67A9: 213 + case 0x67AA: 214 + case 0x67B9: 215 + case 0x67BE: 216 + pi->powertune_defaults = &defaults_hawaii_xt; 217 + break; 218 + case 0x67BA: 219 + case 0x67B1: 220 + pi->powertune_defaults = &defaults_hawaii_pro; 219 221 break; 220 222 } 221 223 ··· 5172 5142 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5173 5143 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5174 5144 5175 - pi->thermal_temp_setting.temperature_low = 99500; 5176 - pi->thermal_temp_setting.temperature_high = 100000; 5177 - pi->thermal_temp_setting.temperature_shutdown = 104000; 5145 + if (rdev->family == CHIP_HAWAII) { 5146 + pi->thermal_temp_setting.temperature_low = 94500; 5147 + pi->thermal_temp_setting.temperature_high = 95000; 5148 + pi->thermal_temp_setting.temperature_shutdown = 104000; 5149 + } else { 5150 + pi->thermal_temp_setting.temperature_low = 99500; 5151 + pi->thermal_temp_setting.temperature_high = 100000; 5152 + pi->thermal_temp_setting.temperature_shutdown = 104000; 5153 + } 5178 5154 5179 5155 pi->uvd_enabled = false; 5180 5156

+4

drivers/gpu/drm/radeon/ci_smc.c

··· 217 217 ucode_start_address = BONAIRE_SMC_UCODE_START; 218 218 ucode_size = BONAIRE_SMC_UCODE_SIZE; 219 219 break; 220 + case CHIP_HAWAII: 221 + ucode_start_address = HAWAII_SMC_UCODE_START; 222 + ucode_size = HAWAII_SMC_UCODE_SIZE; 223 + break; 220 224 default: 221 225 DRM_ERROR("unknown asic in smc ucode loader\n"); 222 226 BUG();

+496 -8

drivers/gpu/drm/radeon/cik.c

··· 41 41 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); 42 42 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); 43 43 MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); 44 + MODULE_FIRMWARE("radeon/HAWAII_pfp.bin"); 45 + MODULE_FIRMWARE("radeon/HAWAII_me.bin"); 46 + MODULE_FIRMWARE("radeon/HAWAII_ce.bin"); 47 + MODULE_FIRMWARE("radeon/HAWAII_mec.bin"); 48 + MODULE_FIRMWARE("radeon/HAWAII_mc.bin"); 49 + MODULE_FIRMWARE("radeon/HAWAII_rlc.bin"); 50 + MODULE_FIRMWARE("radeon/HAWAII_sdma.bin"); 51 + MODULE_FIRMWARE("radeon/HAWAII_smc.bin"); 44 52 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin"); 45 53 MODULE_FIRMWARE("radeon/KAVERI_me.bin"); 46 54 MODULE_FIRMWARE("radeon/KAVERI_ce.bin"); ··· 1305 1297 0xd80c, 0xff000ff0, 0x00000100 1306 1298 }; 1307 1299 1300 + static const u32 hawaii_golden_spm_registers[] = 1301 + { 1302 + 0x30800, 0xe0ffffff, 0xe0000000 1303 + }; 1304 + 1305 + static const u32 hawaii_golden_common_registers[] = 1306 + { 1307 + 0x30800, 0xffffffff, 0xe0000000, 1308 + 0x28350, 0xffffffff, 0x3a00161a, 1309 + 0x28354, 0xffffffff, 0x0000002e, 1310 + 0x9a10, 0xffffffff, 0x00018208, 1311 + 0x98f8, 0xffffffff, 0x12011003 1312 + }; 1313 + 1314 + static const u32 hawaii_golden_registers[] = 1315 + { 1316 + 0x3354, 0x00000333, 0x00000333, 1317 + 0x9a10, 0x00010000, 0x00058208, 1318 + 0x9830, 0xffffffff, 0x00000000, 1319 + 0x9834, 0xf00fffff, 0x00000400, 1320 + 0x9838, 0x0002021c, 0x00020200, 1321 + 0xc78, 0x00000080, 0x00000000, 1322 + 0x5bb0, 0x000000f0, 0x00000070, 1323 + 0x5bc0, 0xf0311fff, 0x80300000, 1324 + 0x350c, 0x00810000, 0x408af000, 1325 + 0x7030, 0x31000111, 0x00000011, 1326 + 0x2f48, 0x73773777, 0x12010001, 1327 + 0x2120, 0x0000007f, 0x0000001b, 1328 + 0x21dc, 0x00007fb6, 0x00002191, 1329 + 0x3628, 0x0000003f, 0x0000000a, 1330 + 0x362c, 0x0000003f, 0x0000000a, 1331 + 0x2ae4, 0x00073ffe, 0x000022a2, 1332 + 0x240c, 0x000007ff, 0x00000000, 1333 + 0x8bf0, 0x00002001, 0x00000001, 1334 + 0x8b24, 0xffffffff, 0x00ffffff, 1335 + 0x30a04, 0x0000ff0f, 0x00000000, 1336 + 0x28a4c, 0x07ffffff, 0x06000000, 1337 + 0x3e78, 0x00000001, 0x00000002, 1338 + 0xc768, 0x00000008, 0x00000008, 1339 + 0xc770, 0x00000f00, 0x00000800, 1340 + 0xc774, 0x00000f00, 0x00000800, 1341 + 0xc798, 0x00ffffff, 0x00ff7fbf, 1342 + 0xc79c, 0x00ffffff, 0x00ff7faf, 1343 + 0x8c00, 0x000000ff, 0x00000800, 1344 + 0xe40, 0x00001fff, 0x00001fff, 1345 + 0x9060, 0x0000007f, 0x00000020, 1346 + 0x9508, 0x00010000, 0x00010000, 1347 + 0xae00, 0x00100000, 0x000ff07c, 1348 + 0xac14, 0x000003ff, 0x0000000f, 1349 + 0xac10, 0xffffffff, 0x7564fdec, 1350 + 0xac0c, 0xffffffff, 0x3120b9a8, 1351 + 0xac08, 0x20000000, 0x0f9c0000 1352 + }; 1353 + 1354 + static const u32 hawaii_mgcg_cgcg_init[] = 1355 + { 1356 + 0xc420, 0xffffffff, 0xfffffffd, 1357 + 0x30800, 0xffffffff, 0xe0000000, 1358 + 0x3c2a0, 0xffffffff, 0x00000100, 1359 + 0x3c208, 0xffffffff, 0x00000100, 1360 + 0x3c2c0, 0xffffffff, 0x00000100, 1361 + 0x3c2c8, 0xffffffff, 0x00000100, 1362 + 0x3c2c4, 0xffffffff, 0x00000100, 1363 + 0x55e4, 0xffffffff, 0x00200100, 1364 + 0x3c280, 0xffffffff, 0x00000100, 1365 + 0x3c214, 0xffffffff, 0x06000100, 1366 + 0x3c220, 0xffffffff, 0x00000100, 1367 + 0x3c218, 0xffffffff, 0x06000100, 1368 + 0x3c204, 0xffffffff, 0x00000100, 1369 + 0x3c2e0, 0xffffffff, 0x00000100, 1370 + 0x3c224, 0xffffffff, 0x00000100, 1371 + 0x3c200, 0xffffffff, 0x00000100, 1372 + 0x3c230, 0xffffffff, 0x00000100, 1373 + 0x3c234, 0xffffffff, 0x00000100, 1374 + 0x3c250, 0xffffffff, 0x00000100, 1375 + 0x3c254, 0xffffffff, 0x00000100, 1376 + 0x3c258, 0xffffffff, 0x00000100, 1377 + 0x3c25c, 0xffffffff, 0x00000100, 1378 + 0x3c260, 0xffffffff, 0x00000100, 1379 + 0x3c27c, 0xffffffff, 0x00000100, 1380 + 0x3c278, 0xffffffff, 0x00000100, 1381 + 0x3c210, 0xffffffff, 0x06000100, 1382 + 0x3c290, 0xffffffff, 0x00000100, 1383 + 0x3c274, 0xffffffff, 0x00000100, 1384 + 0x3c2b4, 0xffffffff, 0x00000100, 1385 + 0x3c2b0, 0xffffffff, 0x00000100, 1386 + 0x3c270, 0xffffffff, 0x00000100, 1387 + 0x30800, 0xffffffff, 0xe0000000, 1388 + 0x3c020, 0xffffffff, 0x00010000, 1389 + 0x3c024, 0xffffffff, 0x00030002, 1390 + 0x3c028, 0xffffffff, 0x00040007, 1391 + 0x3c02c, 0xffffffff, 0x00060005, 1392 + 0x3c030, 0xffffffff, 0x00090008, 1393 + 0x3c034, 0xffffffff, 0x00010000, 1394 + 0x3c038, 0xffffffff, 0x00030002, 1395 + 0x3c03c, 0xffffffff, 0x00040007, 1396 + 0x3c040, 0xffffffff, 0x00060005, 1397 + 0x3c044, 0xffffffff, 0x00090008, 1398 + 0x3c048, 0xffffffff, 0x00010000, 1399 + 0x3c04c, 0xffffffff, 0x00030002, 1400 + 0x3c050, 0xffffffff, 0x00040007, 1401 + 0x3c054, 0xffffffff, 0x00060005, 1402 + 0x3c058, 0xffffffff, 0x00090008, 1403 + 0x3c05c, 0xffffffff, 0x00010000, 1404 + 0x3c060, 0xffffffff, 0x00030002, 1405 + 0x3c064, 0xffffffff, 0x00040007, 1406 + 0x3c068, 0xffffffff, 0x00060005, 1407 + 0x3c06c, 0xffffffff, 0x00090008, 1408 + 0x3c070, 0xffffffff, 0x00010000, 1409 + 0x3c074, 0xffffffff, 0x00030002, 1410 + 0x3c078, 0xffffffff, 0x00040007, 1411 + 0x3c07c, 0xffffffff, 0x00060005, 1412 + 0x3c080, 0xffffffff, 0x00090008, 1413 + 0x3c084, 0xffffffff, 0x00010000, 1414 + 0x3c088, 0xffffffff, 0x00030002, 1415 + 0x3c08c, 0xffffffff, 0x00040007, 1416 + 0x3c090, 0xffffffff, 0x00060005, 1417 + 0x3c094, 0xffffffff, 0x00090008, 1418 + 0x3c098, 0xffffffff, 0x00010000, 1419 + 0x3c09c, 0xffffffff, 0x00030002, 1420 + 0x3c0a0, 0xffffffff, 0x00040007, 1421 + 0x3c0a4, 0xffffffff, 0x00060005, 1422 + 0x3c0a8, 0xffffffff, 0x00090008, 1423 + 0x3c0ac, 0xffffffff, 0x00010000, 1424 + 0x3c0b0, 0xffffffff, 0x00030002, 1425 + 0x3c0b4, 0xffffffff, 0x00040007, 1426 + 0x3c0b8, 0xffffffff, 0x00060005, 1427 + 0x3c0bc, 0xffffffff, 0x00090008, 1428 + 0x3c0c0, 0xffffffff, 0x00010000, 1429 + 0x3c0c4, 0xffffffff, 0x00030002, 1430 + 0x3c0c8, 0xffffffff, 0x00040007, 1431 + 0x3c0cc, 0xffffffff, 0x00060005, 1432 + 0x3c0d0, 0xffffffff, 0x00090008, 1433 + 0x3c0d4, 0xffffffff, 0x00010000, 1434 + 0x3c0d8, 0xffffffff, 0x00030002, 1435 + 0x3c0dc, 0xffffffff, 0x00040007, 1436 + 0x3c0e0, 0xffffffff, 0x00060005, 1437 + 0x3c0e4, 0xffffffff, 0x00090008, 1438 + 0x3c0e8, 0xffffffff, 0x00010000, 1439 + 0x3c0ec, 0xffffffff, 0x00030002, 1440 + 0x3c0f0, 0xffffffff, 0x00040007, 1441 + 0x3c0f4, 0xffffffff, 0x00060005, 1442 + 0x3c0f8, 0xffffffff, 0x00090008, 1443 + 0xc318, 0xffffffff, 0x00020200, 1444 + 0x3350, 0xffffffff, 0x00000200, 1445 + 0x15c0, 0xffffffff, 0x00000400, 1446 + 0x55e8, 0xffffffff, 0x00000000, 1447 + 0x2f50, 0xffffffff, 0x00000902, 1448 + 0x3c000, 0xffffffff, 0x96940200, 1449 + 0x8708, 0xffffffff, 0x00900100, 1450 + 0xc424, 0xffffffff, 0x0020003f, 1451 + 0x38, 0xffffffff, 0x0140001c, 1452 + 0x3c, 0x000f0000, 0x000f0000, 1453 + 0x220, 0xffffffff, 0xc060000c, 1454 + 0x224, 0xc0000fff, 0x00000100, 1455 + 0xf90, 0xffffffff, 0x00000100, 1456 + 0xf98, 0x00000101, 0x00000000, 1457 + 0x20a8, 0xffffffff, 0x00000104, 1458 + 0x55e4, 0xff000fff, 0x00000100, 1459 + 0x30cc, 0xc0000fff, 0x00000104, 1460 + 0xc1e4, 0x00000001, 0x00000001, 1461 + 0xd00c, 0xff000ff0, 0x00000100, 1462 + 0xd80c, 0xff000ff0, 0x00000100 1463 + }; 1464 + 1308 1465 static void cik_init_golden_registers(struct radeon_device *rdev) 1309 1466 { 1310 1467 switch (rdev->family) { ··· 1514 1341 radeon_program_register_sequence(rdev, 1515 1342 spectre_golden_spm_registers, 1516 1343 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 1344 + break; 1345 + case CHIP_HAWAII: 1346 + radeon_program_register_sequence(rdev, 1347 + hawaii_mgcg_cgcg_init, 1348 + (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 1349 + radeon_program_register_sequence(rdev, 1350 + hawaii_golden_registers, 1351 + (const u32)ARRAY_SIZE(hawaii_golden_registers)); 1352 + radeon_program_register_sequence(rdev, 1353 + hawaii_golden_common_registers, 1354 + (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); 1355 + radeon_program_register_sequence(rdev, 1356 + hawaii_golden_spm_registers, 1357 + (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); 1517 1358 break; 1518 1359 default: 1519 1360 break; ··· 1636 1449 {0x0000009f, 0x00b48000} 1637 1450 }; 1638 1451 1452 + #define HAWAII_IO_MC_REGS_SIZE 22 1453 + 1454 + static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] = 1455 + { 1456 + {0x0000007d, 0x40000000}, 1457 + {0x0000007e, 0x40180304}, 1458 + {0x0000007f, 0x0000ff00}, 1459 + {0x00000081, 0x00000000}, 1460 + {0x00000083, 0x00000800}, 1461 + {0x00000086, 0x00000000}, 1462 + {0x00000087, 0x00000100}, 1463 + {0x00000088, 0x00020100}, 1464 + {0x00000089, 0x00000000}, 1465 + {0x0000008b, 0x00040000}, 1466 + {0x0000008c, 0x00000100}, 1467 + {0x0000008e, 0xff010000}, 1468 + {0x00000090, 0xffffefff}, 1469 + {0x00000091, 0xfff3efff}, 1470 + {0x00000092, 0xfff3efbf}, 1471 + {0x00000093, 0xf7ffffff}, 1472 + {0x00000094, 0xffffff7f}, 1473 + {0x00000095, 0x00000fff}, 1474 + {0x00000096, 0x00116fff}, 1475 + {0x00000097, 0x60010000}, 1476 + {0x00000098, 0x10010000}, 1477 + {0x0000009f, 0x00c79000} 1478 + }; 1479 + 1480 + 1639 1481 /** 1640 1482 * cik_srbm_select - select specific register instances 1641 1483 * ··· 1709 1493 1710 1494 switch (rdev->family) { 1711 1495 case CHIP_BONAIRE: 1712 - default: 1713 1496 io_mc_regs = (u32 *)&bonaire_io_mc_regs; 1714 1497 ucode_size = CIK_MC_UCODE_SIZE; 1715 1498 regs_size = BONAIRE_IO_MC_REGS_SIZE; 1716 1499 break; 1500 + case CHIP_HAWAII: 1501 + io_mc_regs = (u32 *)&hawaii_io_mc_regs; 1502 + ucode_size = HAWAII_MC_UCODE_SIZE; 1503 + regs_size = HAWAII_IO_MC_REGS_SIZE; 1504 + break; 1505 + default: 1506 + return -EINVAL; 1717 1507 } 1718 1508 1719 1509 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; ··· 1781 1559 { 1782 1560 const char *chip_name; 1783 1561 size_t pfp_req_size, me_req_size, ce_req_size, 1784 - mec_req_size, rlc_req_size, mc_req_size, 1785 - sdma_req_size, smc_req_size; 1562 + mec_req_size, rlc_req_size, mc_req_size = 0, 1563 + sdma_req_size, smc_req_size = 0; 1786 1564 char fw_name[30]; 1787 1565 int err; 1788 1566 ··· 1799 1577 mc_req_size = CIK_MC_UCODE_SIZE * 4; 1800 1578 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1801 1579 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4); 1580 + break; 1581 + case CHIP_HAWAII: 1582 + chip_name = "HAWAII"; 1583 + pfp_req_size = CIK_PFP_UCODE_SIZE * 4; 1584 + me_req_size = CIK_ME_UCODE_SIZE * 4; 1585 + ce_req_size = CIK_CE_UCODE_SIZE * 4; 1586 + mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1587 + rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; 1588 + mc_req_size = HAWAII_MC_UCODE_SIZE * 4; 1589 + sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1590 + smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4); 1802 1591 break; 1803 1592 case CHIP_KAVERI: 1804 1593 chip_name = "KAVERI"; ··· 1991 1758 1992 1759 num_pipe_configs = rdev->config.cik.max_tile_pipes; 1993 1760 if (num_pipe_configs > 8) 1994 - num_pipe_configs = 8; /* ??? */ 1761 + num_pipe_configs = 16; 1995 1762 1996 - if (num_pipe_configs == 8) { 1763 + if (num_pipe_configs == 16) { 1764 + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1765 + switch (reg_offset) { 1766 + case 0: 1767 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1768 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1769 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1770 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); 1771 + break; 1772 + case 1: 1773 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1774 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1775 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1776 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); 1777 + break; 1778 + case 2: 1779 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1780 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1781 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1782 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); 1783 + break; 1784 + case 3: 1785 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1786 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1787 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1788 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); 1789 + break; 1790 + case 4: 1791 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1792 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1793 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1794 + TILE_SPLIT(split_equal_to_row_size)); 1795 + break; 1796 + case 5: 1797 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1798 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1799 + break; 1800 + case 6: 1801 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1802 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1803 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1804 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); 1805 + break; 1806 + case 7: 1807 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1808 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1809 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1810 + TILE_SPLIT(split_equal_to_row_size)); 1811 + break; 1812 + case 8: 1813 + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1814 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1815 + break; 1816 + case 9: 1817 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1818 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1819 + break; 1820 + case 10: 1821 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1822 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1823 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1824 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1825 + break; 1826 + case 11: 1827 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1828 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1829 + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | 1830 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1831 + break; 1832 + case 12: 1833 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1834 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1835 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1836 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1837 + break; 1838 + case 13: 1839 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1840 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1841 + break; 1842 + case 14: 1843 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1844 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1845 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1846 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1847 + break; 1848 + case 16: 1849 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1850 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1851 + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | 1852 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1853 + break; 1854 + case 17: 1855 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1856 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1857 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1858 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1859 + break; 1860 + case 27: 1861 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1862 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1863 + break; 1864 + case 28: 1865 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1866 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1867 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1868 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1869 + break; 1870 + case 29: 1871 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1872 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1873 + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | 1874 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1875 + break; 1876 + case 30: 1877 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1878 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1879 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1880 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1881 + break; 1882 + default: 1883 + gb_tile_moden = 0; 1884 + break; 1885 + } 1886 + rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; 1887 + WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1888 + } 1889 + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1890 + switch (reg_offset) { 1891 + case 0: 1892 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1893 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1894 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1895 + NUM_BANKS(ADDR_SURF_16_BANK)); 1896 + break; 1897 + case 1: 1898 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1899 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1900 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1901 + NUM_BANKS(ADDR_SURF_16_BANK)); 1902 + break; 1903 + case 2: 1904 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1905 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1906 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1907 + NUM_BANKS(ADDR_SURF_16_BANK)); 1908 + break; 1909 + case 3: 1910 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1911 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1912 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1913 + NUM_BANKS(ADDR_SURF_16_BANK)); 1914 + break; 1915 + case 4: 1916 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1917 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1918 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1919 + NUM_BANKS(ADDR_SURF_8_BANK)); 1920 + break; 1921 + case 5: 1922 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1923 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1924 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1925 + NUM_BANKS(ADDR_SURF_4_BANK)); 1926 + break; 1927 + case 6: 1928 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1929 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1930 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1931 + NUM_BANKS(ADDR_SURF_2_BANK)); 1932 + break; 1933 + case 8: 1934 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1935 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1936 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1937 + NUM_BANKS(ADDR_SURF_16_BANK)); 1938 + break; 1939 + case 9: 1940 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1941 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1942 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1943 + NUM_BANKS(ADDR_SURF_16_BANK)); 1944 + break; 1945 + case 10: 1946 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1947 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1948 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1949 + NUM_BANKS(ADDR_SURF_16_BANK)); 1950 + break; 1951 + case 11: 1952 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1953 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1954 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1955 + NUM_BANKS(ADDR_SURF_8_BANK)); 1956 + break; 1957 + case 12: 1958 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1959 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1960 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1961 + NUM_BANKS(ADDR_SURF_4_BANK)); 1962 + break; 1963 + case 13: 1964 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1965 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1966 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1967 + NUM_BANKS(ADDR_SURF_2_BANK)); 1968 + break; 1969 + case 14: 1970 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1971 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1972 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1973 + NUM_BANKS(ADDR_SURF_2_BANK)); 1974 + break; 1975 + default: 1976 + gb_tile_moden = 0; 1977 + break; 1978 + } 1979 + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1980 + } 1981 + } else if (num_pipe_configs == 8) { 1997 1982 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1998 1983 switch (reg_offset) { 1999 1984 case 0: ··· 3096 2645 for (j = 0; j < sh_per_se; j++) { 3097 2646 cik_select_se_sh(rdev, i, j); 3098 2647 data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 3099 - disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); 2648 + if (rdev->family == CHIP_HAWAII) 2649 + disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH); 2650 + else 2651 + disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); 3100 2652 } 3101 2653 } 3102 2654 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); ··· 3116 2662 data = 0; 3117 2663 for (j = 0; j < sh_per_se; j++) { 3118 2664 switch (enabled_rbs & 3) { 2665 + case 0: 2666 + if (j == 0) 2667 + data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3); 2668 + else 2669 + data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0); 2670 + break; 3119 2671 case 1: 3120 2672 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 3121 2673 break; ··· 3173 2713 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; 3174 2714 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; 3175 2715 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 2716 + break; 2717 + case CHIP_HAWAII: 2718 + rdev->config.cik.max_shader_engines = 4; 2719 + rdev->config.cik.max_tile_pipes = 16; 2720 + rdev->config.cik.max_cu_per_sh = 11; 2721 + rdev->config.cik.max_sh_per_se = 1; 2722 + rdev->config.cik.max_backends_per_se = 4; 2723 + rdev->config.cik.max_texture_channel_caches = 16; 2724 + rdev->config.cik.max_gprs = 256; 2725 + rdev->config.cik.max_gs_threads = 32; 2726 + rdev->config.cik.max_hw_contexts = 8; 2727 + 2728 + rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; 2729 + rdev->config.cik.sc_prim_fifo_size_backend = 0x100; 2730 + rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; 2731 + rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; 2732 + gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 3176 2733 break; 3177 2734 case CHIP_KAVERI: 3178 2735 rdev->config.cik.max_shader_engines = 1; ··· 3954 3477 int r; 3955 3478 3956 3479 WREG32(CP_SEM_WAIT_TIMER, 0x0); 3957 - WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 3480 + if (rdev->family != CHIP_HAWAII) 3481 + WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 3958 3482 3959 3483 /* Set the write pointer delay */ 3960 3484 WREG32(CP_RB_WPTR_DELAY, 0); ··· 5292 4814 static void cik_vm_decode_fault(struct radeon_device *rdev, 5293 4815 u32 status, u32 addr, u32 mc_client) 5294 4816 { 5295 - u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 4817 + u32 mc_id; 5296 4818 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 5297 4819 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 5298 4820 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 5299 4821 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 4822 + 4823 + if (rdev->family == CHIP_HAWAII) 4824 + mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 4825 + else 4826 + mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 5300 4827 5301 4828 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 5302 4829 protections, vmid, addr, ··· 5559 5076 5560 5077 switch (rdev->family) { 5561 5078 case CHIP_BONAIRE: 5079 + case CHIP_HAWAII: 5562 5080 default: 5563 5081 size = BONAIRE_RLC_UCODE_SIZE; 5564 5082 break; ··· 6315 5831 case CHIP_KABINI: 6316 5832 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 6317 5833 buffer[count++] = cpu_to_le32(0x00000000); 5834 + break; 5835 + case CHIP_HAWAII: 5836 + buffer[count++] = 0x3a00161a; 5837 + buffer[count++] = 0x0000002e; 6318 5838 break; 6319 5839 default: 6320 5840 buffer[count++] = cpu_to_le32(0x00000000);

+12 -28

drivers/gpu/drm/radeon/cik_sdma.c

··· 102 102 { 103 103 struct radeon_ring *ring = &rdev->ring[fence->ring]; 104 104 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 105 - u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 106 - SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 107 - u32 ref_and_mask; 108 - 109 - if (fence->ring == R600_RING_TYPE_DMA_INDEX) 110 - ref_and_mask = SDMA0; 111 - else 112 - ref_and_mask = SDMA1; 113 105 114 106 /* write the fence */ 115 107 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); ··· 111 119 /* generate an interrupt */ 112 120 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 113 121 /* flush HDP */ 114 - radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 115 - radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 116 - radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 117 - radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ 118 - radeon_ring_write(ring, ref_and_mask); /* MASK */ 119 - radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ 122 + /* We should be using the new POLL_REG_MEM special op packet here 123 + * but it causes sDMA to hang sometimes 124 + */ 125 + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 126 + radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 127 + radeon_ring_write(ring, 0); 120 128 } 121 129 122 130 /** ··· 712 720 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 713 721 { 714 722 struct radeon_ring *ring = &rdev->ring[ridx]; 715 - u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 716 - SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 717 - u32 ref_and_mask; 718 723 719 724 if (vm == NULL) 720 725 return; 721 - 722 - if (ridx == R600_RING_TYPE_DMA_INDEX) 723 - ref_and_mask = SDMA0; 724 - else 725 - ref_and_mask = SDMA1; 726 726 727 727 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 728 728 if (vm->id < 8) { ··· 750 766 radeon_ring_write(ring, VMID(0)); 751 767 752 768 /* flush HDP */ 753 - radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 754 - radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 755 - radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 756 - radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ 757 - radeon_ring_write(ring, ref_and_mask); /* MASK */ 758 - radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ 769 + /* We should be using the new POLL_REG_MEM special op packet here 770 + * but it causes sDMA to hang sometimes 771 + */ 772 + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 773 + radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 774 + radeon_ring_write(ring, 0); 759 775 760 776 /* flush TLB */ 761 777 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

+7 -1

drivers/gpu/drm/radeon/cikd.h

··· 25 25 #define CIK_H 26 26 27 27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28 + #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 28 29 29 - #define CIK_RB_BITMAP_WIDTH_PER_SH 2 30 + #define CIK_RB_BITMAP_WIDTH_PER_SH 2 31 + #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 30 32 31 33 /* DIDT IND registers */ 32 34 #define DIDT_SQ_CTRL0 0x0 ··· 501 499 * bit 4: write 502 500 */ 503 501 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 502 + #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 504 503 #define MEMORY_CLIENT_ID_SHIFT 12 505 504 #define MEMORY_CLIENT_RW_MASK (1 << 24) 506 505 #define MEMORY_CLIENT_RW_SHIFT 24 ··· 1165 1162 # define ADDR_SURF_P8_32x32_16x16 12 1166 1163 # define ADDR_SURF_P8_32x32_16x32 13 1167 1164 # define ADDR_SURF_P8_32x64_32x32 14 1165 + # define ADDR_SURF_P16_32x32_8x16 16 1166 + # define ADDR_SURF_P16_32x32_16x16 17 1168 1167 # define TILE_SPLIT(x) ((x) << 11) 1169 1168 # define ADDR_SURF_TILE_SPLIT_64B 0 1170 1169 # define ADDR_SURF_TILE_SPLIT_128B 1 ··· 1460 1455 # define RASTER_CONFIG_RB_MAP_1 1 1461 1456 # define RASTER_CONFIG_RB_MAP_2 2 1462 1457 # define RASTER_CONFIG_RB_MAP_3 3 1458 + #define PKR_MAP(x) ((x) << 8) 1463 1459 1464 1460 #define VGT_EVENT_INITIATOR 0x28a90 1465 1461 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)

+15 -8

drivers/gpu/drm/radeon/dce6_afmt.c

··· 156 156 u8 *sadb; 157 157 int sad_count; 158 158 159 - /* XXX: setting this register causes hangs on some asics */ 160 - return; 161 - 162 159 if (!dig->afmt->pin) 163 160 return; 164 161 ··· 241 244 242 245 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 243 246 u32 value = 0; 247 + u8 stereo_freqs = 0; 248 + int max_channels = -1; 244 249 int j; 245 250 246 251 for (j = 0; j < sad_count; j++) { 247 252 struct cea_sad *sad = &sads[j]; 248 253 249 254 if (sad->format == eld_reg_to_type[i][1]) { 250 - value = MAX_CHANNELS(sad->channels) | 251 - DESCRIPTOR_BYTE_2(sad->byte2) | 252 - SUPPORTED_FREQUENCIES(sad->freq); 255 + if (sad->channels > max_channels) { 256 + value = MAX_CHANNELS(sad->channels) | 257 + DESCRIPTOR_BYTE_2(sad->byte2) | 258 + SUPPORTED_FREQUENCIES(sad->freq); 259 + max_channels = sad->channels; 260 + } 261 + 253 262 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 254 - value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 255 - break; 263 + stereo_freqs |= sad->freq; 264 + else 265 + break; 256 266 } 257 267 } 268 + 269 + value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 270 + 258 271 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 259 272 } 260 273

+15 -8

drivers/gpu/drm/radeon/evergreen_hdmi.c

··· 105 105 u8 *sadb; 106 106 int sad_count; 107 107 108 - /* XXX: setting this register causes hangs on some asics */ 109 - return; 110 - 111 108 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 112 109 if (connector->encoder == encoder) { 113 110 radeon_connector = to_radeon_connector(connector); ··· 181 184 182 185 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 183 186 u32 value = 0; 187 + u8 stereo_freqs = 0; 188 + int max_channels = -1; 184 189 int j; 185 190 186 191 for (j = 0; j < sad_count; j++) { 187 192 struct cea_sad *sad = &sads[j]; 188 193 189 194 if (sad->format == eld_reg_to_type[i][1]) { 190 - value = MAX_CHANNELS(sad->channels) | 191 - DESCRIPTOR_BYTE_2(sad->byte2) | 192 - SUPPORTED_FREQUENCIES(sad->freq); 195 + if (sad->channels > max_channels) { 196 + value = MAX_CHANNELS(sad->channels) | 197 + DESCRIPTOR_BYTE_2(sad->byte2) | 198 + SUPPORTED_FREQUENCIES(sad->freq); 199 + max_channels = sad->channels; 200 + } 201 + 193 202 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 194 - value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 195 - break; 203 + stereo_freqs |= sad->freq; 204 + else 205 + break; 196 206 } 197 207 } 208 + 209 + value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 210 + 198 211 WREG32(eld_reg_to_type[i][0], value); 199 212 } 200 213

+66 -32

drivers/gpu/drm/radeon/r600_hdmi.c

··· 24 24 * Authors: Christian König 25 25 */ 26 26 #include <linux/hdmi.h> 27 + #include <linux/gcd.h> 27 28 #include <drm/drmP.h> 28 29 #include <drm/radeon_drm.h> 29 30 #include "radeon.h" ··· 58 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 59 58 /* 32kHz 44.1kHz 48kHz */ 60 59 /* Clock N CTS N CTS N CTS */ 61 - { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 60 + { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ 62 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 63 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 64 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 65 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 66 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 67 - { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 66 + { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ 68 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 69 - { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 68 + { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ 70 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 71 - { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 72 70 }; 73 71 74 - /* 75 - * calculate CTS value if it's not found in the table 76 - */ 77 - static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 78 - { 79 - u64 n; 80 - u32 d; 81 72 82 - if (*CTS == 0) { 83 - n = (u64)clock * (u64)N * 1000ULL; 84 - d = 128 * freq; 85 - do_div(n, d); 86 - *CTS = n; 87 - } 88 - DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 89 - N, *CTS, freq); 73 + /* 74 + * calculate CTS and N values if they are not found in the table 75 + */ 76 + static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) 77 + { 78 + int n, cts; 79 + unsigned long div, mul; 80 + 81 + /* Safe, but overly large values */ 82 + n = 128 * freq; 83 + cts = clock * 1000; 84 + 85 + /* Smallest valid fraction */ 86 + div = gcd(n, cts); 87 + 88 + n /= div; 89 + cts /= div; 90 + 91 + /* 92 + * The optimal N is 128*freq/1000. Calculate the closest larger 93 + * value that doesn't truncate any bits. 94 + */ 95 + mul = ((128*freq/1000) + (n-1))/n; 96 + 97 + n *= mul; 98 + cts *= mul; 99 + 100 + /* Check that we are in spec (not always possible) */ 101 + if (n < (128*freq/1500)) 102 + printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); 103 + if (n > (128*freq/300)) 104 + printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); 105 + 106 + *N = n; 107 + *CTS = cts; 108 + 109 + DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", 110 + *N, *CTS, freq); 90 111 } 91 112 92 113 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) ··· 116 93 struct radeon_hdmi_acr res; 117 94 u8 i; 118 95 119 - for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 120 - r600_hdmi_predefined_acr[i].clock != 0; i++) 121 - ; 122 - res = r600_hdmi_predefined_acr[i]; 96 + /* Precalculated values for common clocks */ 97 + for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { 98 + if (r600_hdmi_predefined_acr[i].clock == clock) 99 + return r600_hdmi_predefined_acr[i]; 100 + } 123 101 124 - /* In case some CTS are missing */ 125 - r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 126 - r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 127 - r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 102 + /* And odd clocks get manually calculated */ 103 + r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); 104 + r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); 105 + r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); 128 106 129 107 return res; 130 108 } ··· 412 388 413 389 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 414 390 u32 value = 0; 391 + u8 stereo_freqs = 0; 392 + int max_channels = -1; 415 393 int j; 416 394 417 395 for (j = 0; j < sad_count; j++) { 418 396 struct cea_sad *sad = &sads[j]; 419 397 420 398 if (sad->format == eld_reg_to_type[i][1]) { 421 - value = MAX_CHANNELS(sad->channels) | 422 - DESCRIPTOR_BYTE_2(sad->byte2) | 423 - SUPPORTED_FREQUENCIES(sad->freq); 399 + if (sad->channels > max_channels) { 400 + value = MAX_CHANNELS(sad->channels) | 401 + DESCRIPTOR_BYTE_2(sad->byte2) | 402 + SUPPORTED_FREQUENCIES(sad->freq); 403 + max_channels = sad->channels; 404 + } 405 + 424 406 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 425 - value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 426 - break; 407 + stereo_freqs |= sad->freq; 408 + else 409 + break; 427 410 } 428 411 } 412 + 413 + value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 414 + 429 415 WREG32(eld_reg_to_type[i][0], value); 430 416 } 431 417

+39 -18

drivers/gpu/drm/radeon/radeon_asic.c

··· 2437 2437 } 2438 2438 break; 2439 2439 case CHIP_BONAIRE: 2440 + case CHIP_HAWAII: 2440 2441 rdev->asic = &ci_asic; 2441 2442 rdev->num_crtc = 6; 2442 2443 rdev->has_uvd = true; 2443 - rdev->cg_flags = 2444 - RADEON_CG_SUPPORT_GFX_MGCG | 2445 - RADEON_CG_SUPPORT_GFX_MGLS | 2446 - /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2447 - RADEON_CG_SUPPORT_GFX_CGLS | 2448 - RADEON_CG_SUPPORT_GFX_CGTS | 2449 - RADEON_CG_SUPPORT_GFX_CGTS_LS | 2450 - RADEON_CG_SUPPORT_GFX_CP_LS | 2451 - RADEON_CG_SUPPORT_MC_LS | 2452 - RADEON_CG_SUPPORT_MC_MGCG | 2453 - RADEON_CG_SUPPORT_SDMA_MGCG | 2454 - RADEON_CG_SUPPORT_SDMA_LS | 2455 - RADEON_CG_SUPPORT_BIF_LS | 2456 - RADEON_CG_SUPPORT_VCE_MGCG | 2457 - RADEON_CG_SUPPORT_UVD_MGCG | 2458 - RADEON_CG_SUPPORT_HDP_LS | 2459 - RADEON_CG_SUPPORT_HDP_MGCG; 2460 - rdev->pg_flags = 0; 2444 + if (rdev->family == CHIP_BONAIRE) { 2445 + rdev->cg_flags = 2446 + RADEON_CG_SUPPORT_GFX_MGCG | 2447 + RADEON_CG_SUPPORT_GFX_MGLS | 2448 + /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2449 + RADEON_CG_SUPPORT_GFX_CGLS | 2450 + RADEON_CG_SUPPORT_GFX_CGTS | 2451 + RADEON_CG_SUPPORT_GFX_CGTS_LS | 2452 + RADEON_CG_SUPPORT_GFX_CP_LS | 2453 + RADEON_CG_SUPPORT_MC_LS | 2454 + RADEON_CG_SUPPORT_MC_MGCG | 2455 + RADEON_CG_SUPPORT_SDMA_MGCG | 2456 + RADEON_CG_SUPPORT_SDMA_LS | 2457 + RADEON_CG_SUPPORT_BIF_LS | 2458 + RADEON_CG_SUPPORT_VCE_MGCG | 2459 + RADEON_CG_SUPPORT_UVD_MGCG | 2460 + RADEON_CG_SUPPORT_HDP_LS | 2461 + RADEON_CG_SUPPORT_HDP_MGCG; 2462 + rdev->pg_flags = 0; 2463 + } else { 2464 + rdev->cg_flags = 2465 + RADEON_CG_SUPPORT_GFX_MGCG | 2466 + RADEON_CG_SUPPORT_GFX_MGLS | 2467 + /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2468 + RADEON_CG_SUPPORT_GFX_CGLS | 2469 + RADEON_CG_SUPPORT_GFX_CGTS | 2470 + RADEON_CG_SUPPORT_GFX_CP_LS | 2471 + RADEON_CG_SUPPORT_MC_LS | 2472 + RADEON_CG_SUPPORT_MC_MGCG | 2473 + RADEON_CG_SUPPORT_SDMA_MGCG | 2474 + RADEON_CG_SUPPORT_SDMA_LS | 2475 + RADEON_CG_SUPPORT_BIF_LS | 2476 + RADEON_CG_SUPPORT_VCE_MGCG | 2477 + RADEON_CG_SUPPORT_UVD_MGCG | 2478 + RADEON_CG_SUPPORT_HDP_LS | 2479 + RADEON_CG_SUPPORT_HDP_MGCG; 2480 + rdev->pg_flags = 0; 2481 + } 2461 2482 break; 2462 2483 case CHIP_KAVERI: 2463 2484 case CHIP_KABINI:

+4 -12

drivers/gpu/drm/radeon/radeon_connectors.c

··· 1728 1728 if (radeon_audio != 0) 1729 1729 drm_object_attach_property(&radeon_connector->base.base, 1730 1730 rdev->mode_info.audio_property, 1731 - (radeon_audio == 1) ? 1732 - RADEON_AUDIO_AUTO : 1733 - RADEON_AUDIO_DISABLE); 1731 + RADEON_AUDIO_AUTO); 1734 1732 1735 1733 subpixel_order = SubPixelHorizontalRGB; 1736 1734 connector->interlace_allowed = true; ··· 1826 1828 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1827 1829 drm_object_attach_property(&radeon_connector->base.base, 1828 1830 rdev->mode_info.audio_property, 1829 - (radeon_audio == 1) ? 1830 - RADEON_AUDIO_AUTO : 1831 - RADEON_AUDIO_DISABLE); 1831 + RADEON_AUDIO_AUTO); 1832 1832 } 1833 1833 if (ASIC_IS_AVIVO(rdev)) { 1834 1834 drm_object_attach_property(&radeon_connector->base.base, ··· 1876 1880 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1877 1881 drm_object_attach_property(&radeon_connector->base.base, 1878 1882 rdev->mode_info.audio_property, 1879 - (radeon_audio == 1) ? 1880 - RADEON_AUDIO_AUTO : 1881 - RADEON_AUDIO_DISABLE); 1883 + RADEON_AUDIO_AUTO); 1882 1884 } 1883 1885 if (ASIC_IS_AVIVO(rdev)) { 1884 1886 drm_object_attach_property(&radeon_connector->base.base, ··· 1925 1931 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { 1926 1932 drm_object_attach_property(&radeon_connector->base.base, 1927 1933 rdev->mode_info.audio_property, 1928 - (radeon_audio == 1) ? 1929 - RADEON_AUDIO_AUTO : 1930 - RADEON_AUDIO_DISABLE); 1934 + RADEON_AUDIO_AUTO); 1931 1935 } 1932 1936 if (ASIC_IS_AVIVO(rdev)) { 1933 1937 drm_object_attach_property(&radeon_connector->base.base,

+1

drivers/gpu/drm/radeon/radeon_device.c

··· 98 98 "BONAIRE", 99 99 "KAVERI", 100 100 "KABINI", 101 + "HAWAII", 101 102 "LAST", 102 103 }; 103 104

+1

drivers/gpu/drm/radeon/radeon_family.h

··· 96 96 CHIP_BONAIRE, 97 97 CHIP_KAVERI, 98 98 CHIP_KABINI, 99 + CHIP_HAWAII, 99 100 CHIP_LAST, 100 101 }; 101 102

+21

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

··· 1056 1056 } 1057 1057 } 1058 1058 1059 + static void radeon_crtc_disable(struct drm_crtc *crtc) 1060 + { 1061 + radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1062 + if (crtc->fb) { 1063 + int r; 1064 + struct radeon_framebuffer *radeon_fb; 1065 + struct radeon_bo *rbo; 1066 + 1067 + radeon_fb = to_radeon_framebuffer(crtc->fb); 1068 + rbo = gem_to_radeon_bo(radeon_fb->obj); 1069 + r = radeon_bo_reserve(rbo, false); 1070 + if (unlikely(r)) 1071 + DRM_ERROR("failed to reserve rbo before unpin\n"); 1072 + else { 1073 + radeon_bo_unpin(rbo); 1074 + radeon_bo_unreserve(rbo); 1075 + } 1076 + } 1077 + } 1078 + 1059 1079 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1060 1080 .dpms = radeon_crtc_dpms, 1061 1081 .mode_fixup = radeon_crtc_mode_fixup, ··· 1085 1065 .prepare = radeon_crtc_prepare, 1086 1066 .commit = radeon_crtc_commit, 1087 1067 .load_lut = radeon_crtc_load_lut, 1068 + .disable = radeon_crtc_disable 1088 1069 }; 1089 1070 1090 1071

+1

drivers/gpu/drm/radeon/radeon_pm.c

··· 1256 1256 case CHIP_BONAIRE: 1257 1257 case CHIP_KABINI: 1258 1258 case CHIP_KAVERI: 1259 + case CHIP_HAWAII: 1259 1260 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1260 1261 if (!rdev->rlc_fw) 1261 1262 rdev->pm.pm_method = PM_METHOD_PROFILE;

+4

drivers/gpu/drm/radeon/radeon_ucode.h

··· 59 59 #define SI_MC_UCODE_SIZE 7769 60 60 #define OLAND_MC_UCODE_SIZE 7863 61 61 #define CIK_MC_UCODE_SIZE 7866 62 + #define HAWAII_MC_UCODE_SIZE 7933 62 63 63 64 /* SDMA */ 64 65 #define CIK_SDMA_UCODE_SIZE 1050 ··· 143 142 144 143 #define BONAIRE_SMC_UCODE_START 0x20000 145 144 #define BONAIRE_SMC_UCODE_SIZE 0x1FDEC 145 + 146 + #define HAWAII_SMC_UCODE_START 0x20000 147 + #define HAWAII_SMC_UCODE_SIZE 0x1FDEC 146 148 147 149 #endif

+1

drivers/gpu/drm/radeon/radeon_uvd.c

··· 97 97 case CHIP_BONAIRE: 98 98 case CHIP_KABINI: 99 99 case CHIP_KAVERI: 100 + case CHIP_HAWAII: 100 101 fw_name = FIRMWARE_BONAIRE; 101 102 break; 102 103

+5 -11

drivers/gpu/drm/radeon/rs690.c

··· 345 345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 346 346 rdev->pm.sideport_bandwidth.full) 347 347 max_bandwidth = rdev->pm.sideport_bandwidth; 348 - read_delay_latency.full = dfixed_const(370 * 800 * 1000); 349 - read_delay_latency.full = dfixed_div(read_delay_latency, 350 - rdev->pm.igp_sideport_mclk); 348 + read_delay_latency.full = dfixed_const(370 * 800); 349 + a.full = dfixed_const(1000); 350 + b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a); 351 + read_delay_latency.full = dfixed_div(read_delay_latency, b); 352 + read_delay_latency.full = dfixed_mul(read_delay_latency, a); 351 353 } else { 352 354 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 353 355 rdev->pm.k8_bandwidth.full) ··· 490 488 } 491 489 if (wm0->priority_mark.full > priority_mark02.full) 492 490 priority_mark02.full = wm0->priority_mark.full; 493 - if (dfixed_trunc(priority_mark02) < 0) 494 - priority_mark02.full = 0; 495 491 if (wm0->priority_mark_max.full > priority_mark02.full) 496 492 priority_mark02.full = wm0->priority_mark_max.full; 497 493 if (wm1->priority_mark.full > priority_mark12.full) 498 494 priority_mark12.full = wm1->priority_mark.full; 499 - if (dfixed_trunc(priority_mark12) < 0) 500 - priority_mark12.full = 0; 501 495 if (wm1->priority_mark_max.full > priority_mark12.full) 502 496 priority_mark12.full = wm1->priority_mark_max.full; 503 497 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); ··· 524 526 } 525 527 if (wm0->priority_mark.full > priority_mark02.full) 526 528 priority_mark02.full = wm0->priority_mark.full; 527 - if (dfixed_trunc(priority_mark02) < 0) 528 - priority_mark02.full = 0; 529 529 if (wm0->priority_mark_max.full > priority_mark02.full) 530 530 priority_mark02.full = wm0->priority_mark_max.full; 531 531 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); ··· 551 555 } 552 556 if (wm1->priority_mark.full > priority_mark12.full) 553 557 priority_mark12.full = wm1->priority_mark.full; 554 - if (dfixed_trunc(priority_mark12) < 0) 555 - priority_mark12.full = 0; 556 558 if (wm1->priority_mark_max.full > priority_mark12.full) 557 559 priority_mark12.full = wm1->priority_mark_max.full; 558 560 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);

-8

drivers/gpu/drm/radeon/rv515.c

··· 1155 1155 } 1156 1156 if (wm0->priority_mark.full > priority_mark02.full) 1157 1157 priority_mark02.full = wm0->priority_mark.full; 1158 - if (dfixed_trunc(priority_mark02) < 0) 1159 - priority_mark02.full = 0; 1160 1158 if (wm0->priority_mark_max.full > priority_mark02.full) 1161 1159 priority_mark02.full = wm0->priority_mark_max.full; 1162 1160 if (wm1->priority_mark.full > priority_mark12.full) 1163 1161 priority_mark12.full = wm1->priority_mark.full; 1164 - if (dfixed_trunc(priority_mark12) < 0) 1165 - priority_mark12.full = 0; 1166 1162 if (wm1->priority_mark_max.full > priority_mark12.full) 1167 1163 priority_mark12.full = wm1->priority_mark_max.full; 1168 1164 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); ··· 1189 1193 } 1190 1194 if (wm0->priority_mark.full > priority_mark02.full) 1191 1195 priority_mark02.full = wm0->priority_mark.full; 1192 - if (dfixed_trunc(priority_mark02) < 0) 1193 - priority_mark02.full = 0; 1194 1196 if (wm0->priority_mark_max.full > priority_mark02.full) 1195 1197 priority_mark02.full = wm0->priority_mark_max.full; 1196 1198 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); ··· 1216 1222 } 1217 1223 if (wm1->priority_mark.full > priority_mark12.full) 1218 1224 priority_mark12.full = wm1->priority_mark.full; 1219 - if (dfixed_trunc(priority_mark12) < 0) 1220 - priority_mark12.full = 0; 1221 1225 if (wm1->priority_mark_max.full > priority_mark12.full) 1222 1226 priority_mark12.full = wm1->priority_mark_max.full; 1223 1227 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);

+12

include/drm/drm_pciids.h

··· 261 261 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 262 262 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 263 263 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ 264 + {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 265 + {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 266 + {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 267 + {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 268 + {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 269 + {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 270 + {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 271 + {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 272 + {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 273 + {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 274 + {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 275 + {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \ 264 276 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 265 277 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 266 278 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \