tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-pinctrl-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.15 (take two)
- Add pin control and GPIO support for the new RZ/G2L SoC.
+1365
+155
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+155
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas RZ/G2L combined Pin and GPIO controller
8
+
9
+
maintainers:
10
+
- Geert Uytterhoeven <geert+renesas@glider.be>
11
+
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
+
13
+
description:
14
+
The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
15
+
controller.
16
+
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17
+
Each port features up to 8 pins, each of them configurable for GPIO function
18
+
(port mode) or in alternate function mode.
19
+
Up to 8 different alternate function modes exist for each single pin.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
gpio-controller: true
30
+
31
+
'#gpio-cells':
32
+
const: 2
33
+
description:
34
+
The first cell contains the global GPIO port index, constructed using the
35
+
RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
36
+
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
37
+
E.g. "RZG2L_GPIO(39, 1)" for P39_1.
38
+
39
+
gpio-ranges:
40
+
maxItems: 1
41
+
42
+
clocks:
43
+
maxItems: 1
44
+
45
+
power-domains:
46
+
maxItems: 1
47
+
48
+
resets:
49
+
items:
50
+
- description: GPIO_RSTN signal
51
+
- description: GPIO_PORT_RESETN signal
52
+
- description: GPIO_SPARE_RESETN signal
53
+
54
+
additionalProperties:
55
+
anyOf:
56
+
- type: object
57
+
allOf:
58
+
- $ref: pincfg-node.yaml#
59
+
- $ref: pinmux-node.yaml#
60
+
61
+
description:
62
+
Pin controller client devices use pin configuration subnodes (children
63
+
and grandchildren) for desired pin configuration.
64
+
Client device subnodes use below standard properties.
65
+
66
+
properties:
67
+
phandle: true
68
+
pinmux:
69
+
description:
70
+
Values are constructed from GPIO port number, pin number, and
71
+
alternate function configuration number using the RZG2L_PORT_PINMUX()
72
+
helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
73
+
pins: true
74
+
drive-strength:
75
+
enum: [ 2, 4, 8, 12 ]
76
+
power-source:
77
+
enum: [ 1800, 2500, 3300 ]
78
+
slew-rate: true
79
+
gpio-hog: true
80
+
gpios: true
81
+
input-enable: true
82
+
output-high: true
83
+
output-low: true
84
+
line-name: true
85
+
86
+
- type: object
87
+
properties:
88
+
phandle: true
89
+
90
+
additionalProperties:
91
+
$ref: "#/additionalProperties/anyOf/0"
92
+
93
+
required:
94
+
- compatible
95
+
- reg
96
+
- gpio-controller
97
+
- '#gpio-cells'
98
+
- gpio-ranges
99
+
- clocks
100
+
- power-domains
101
+
- resets
102
+
103
+
examples:
104
+
- |
105
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
106
+
#include <dt-bindings/clock/r9a07g044-cpg.h>
107
+
108
+
pinctrl: pinctrl@11030000 {
109
+
compatible = "renesas,r9a07g044-pinctrl";
110
+
reg = <0x11030000 0x10000>;
111
+
112
+
gpio-controller;
113
+
#gpio-cells = <2>;
114
+
gpio-ranges = <&pinctrl 0 0 392>;
115
+
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
116
+
resets = <&cpg R9A07G044_GPIO_RSTN>,
117
+
<&cpg R9A07G044_GPIO_PORT_RESETN>,
118
+
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
119
+
power-domains = <&cpg>;
120
+
121
+
scif0_pins: serial0 {
122
+
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
123
+
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
124
+
};
125
+
126
+
i2c1_pins: i2c1 {
127
+
pins = "RIIC1_SDA", "RIIC1_SCL";
128
+
input-enable;
129
+
};
130
+
131
+
sd1-pwr-en-hog {
132
+
gpio-hog;
133
+
gpios = <RZG2L_GPIO(39, 2) 0>;
134
+
output-high;
135
+
line-name = "sd1_pwr_en";
136
+
};
137
+
138
+
sdhi1_pins: sd1 {
139
+
sd1_mux {
140
+
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
141
+
<RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
142
+
power-source = <3300>;
143
+
};
144
+
145
+
sd1_data {
146
+
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
147
+
power-source = <3300>;
148
+
};
149
+
150
+
sd1_ctrl {
151
+
pins = "SD1_CLK", "SD1_CMD";
152
+
power-source = <3300>;
153
+
};
154
+
};
155
+
};
+11
drivers/pinctrl/renesas/Kconfig
+11
drivers/pinctrl/renesas/Kconfig
···
37
37
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
38
38
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
39
39
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
40
+
select PINCTRL_RZG2L if ARCH_R9A07G044
40
41
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
41
42
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
42
43
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
···
176
175
select GPIOLIB
177
176
help
178
177
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
178
+
179
+
config PINCTRL_RZG2L
180
+
bool "pin control support for RZ/G2L" if COMPILE_TEST
181
+
depends on OF
182
+
select GPIOLIB
183
+
select GENERIC_PINCTRL_GROUPS
184
+
select GENERIC_PINMUX_FUNCTIONS
185
+
select GENERIC_PINCONF
186
+
help
187
+
This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
179
188
180
189
config PINCTRL_PFC_R8A77470
181
190
bool "pin control support for RZ/G1C" if COMPILE_TEST
+1
drivers/pinctrl/renesas/Makefile
+1
drivers/pinctrl/renesas/Makefile
+1175
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+1175
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Renesas RZ/G2L Pin Control and GPIO driver core
4
+
*
5
+
* Copyright (C) 2021 Renesas Electronics Corporation.
6
+
*/
7
+
8
+
#include <linux/bitops.h>
9
+
#include <linux/clk.h>
10
+
#include <linux/gpio/driver.h>
11
+
#include <linux/io.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/pinctrl/pinconf-generic.h>
15
+
#include <linux/pinctrl/pinconf.h>
16
+
#include <linux/pinctrl/pinctrl.h>
17
+
#include <linux/pinctrl/pinmux.h>
18
+
#include <linux/spinlock.h>
19
+
20
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
21
+
22
+
#include "../core.h"
23
+
#include "../pinconf.h"
24
+
#include "../pinmux.h"
25
+
26
+
#define DRV_NAME "pinctrl-rzg2l"
27
+
28
+
/*
29
+
* Use 16 lower bits [15:0] for pin identifier
30
+
* Use 16 higher bits [31:16] for pin mux function
31
+
*/
32
+
#define MUX_PIN_ID_MASK GENMASK(15, 0)
33
+
#define MUX_FUNC_MASK GENMASK(31, 16)
34
+
#define MUX_FUNC_OFFS 16
35
+
#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
36
+
37
+
/* PIN capabilities */
38
+
#define PIN_CFG_IOLH BIT(0)
39
+
#define PIN_CFG_SR BIT(1)
40
+
#define PIN_CFG_IEN BIT(2)
41
+
#define PIN_CFG_PUPD BIT(3)
42
+
#define PIN_CFG_IOLH_SD0 BIT(4)
43
+
#define PIN_CFG_IOLH_SD1 BIT(5)
44
+
#define PIN_CFG_IOLH_QSPI BIT(6)
45
+
#define PIN_CFG_IOLH_ETH0 BIT(7)
46
+
#define PIN_CFG_IOLH_ETH1 BIT(8)
47
+
#define PIN_CFG_FILONOFF BIT(9)
48
+
#define PIN_CFG_FILNUM BIT(10)
49
+
#define PIN_CFG_FILCLKSEL BIT(11)
50
+
51
+
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \
52
+
PIN_CFG_SR | \
53
+
PIN_CFG_PUPD | \
54
+
PIN_CFG_FILONOFF | \
55
+
PIN_CFG_FILNUM | \
56
+
PIN_CFG_FILCLKSEL)
57
+
58
+
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
59
+
PIN_CFG_FILONOFF | \
60
+
PIN_CFG_FILNUM | \
61
+
PIN_CFG_FILCLKSEL)
62
+
63
+
/*
64
+
* n indicates number of pins in the port, a is the register index
65
+
* and f is pin configuration capabilities supported.
66
+
*/
67
+
#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
68
+
#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
69
+
#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
70
+
#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
71
+
72
+
/*
73
+
* BIT(31) indicates dedicated pin, p is the register index while
74
+
* referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
75
+
* (b * 8) and f is the pin configuration capabilities supported.
76
+
*/
77
+
#define RZG2L_SINGLE_PIN BIT(31)
78
+
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
79
+
((p) << 24) | ((b) << 20) | (f))
80
+
#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24)
81
+
#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
82
+
#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
83
+
84
+
#define P(n) (0x0000 + 0x10 + (n))
85
+
#define PM(n) (0x0100 + 0x20 + (n) * 2)
86
+
#define PMC(n) (0x0200 + 0x10 + (n))
87
+
#define PFC(n) (0x0400 + 0x40 + (n) * 4)
88
+
#define PIN(n) (0x0800 + 0x10 + (n))
89
+
#define IEN(n) (0x1800 + (n) * 8)
90
+
#define PWPR (0x3014)
91
+
#define SD_CH(n) (0x3000 + (n) * 4)
92
+
#define QSPI (0x3008)
93
+
94
+
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
95
+
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
96
+
97
+
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
98
+
#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
99
+
100
+
#define PM_MASK 0x03
101
+
#define PVDD_MASK 0x01
102
+
#define PFC_MASK 0x07
103
+
#define IEN_MASK 0x01
104
+
105
+
#define PM_INPUT 0x1
106
+
#define PM_OUTPUT 0x2
107
+
108
+
#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
109
+
#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
110
+
111
+
struct rzg2l_dedicated_configs {
112
+
const char *name;
113
+
u32 config;
114
+
};
115
+
116
+
struct rzg2l_pinctrl_data {
117
+
const char * const *port_pins;
118
+
const u32 *port_pin_configs;
119
+
struct rzg2l_dedicated_configs *dedicated_pins;
120
+
unsigned int n_port_pins;
121
+
unsigned int n_dedicated_pins;
122
+
};
123
+
124
+
struct rzg2l_pinctrl {
125
+
struct pinctrl_dev *pctl;
126
+
struct pinctrl_desc desc;
127
+
struct pinctrl_pin_desc *pins;
128
+
129
+
const struct rzg2l_pinctrl_data *data;
130
+
void __iomem *base;
131
+
struct device *dev;
132
+
struct clk *clk;
133
+
134
+
struct gpio_chip gpio_chip;
135
+
struct pinctrl_gpio_range gpio_range;
136
+
137
+
spinlock_t lock;
138
+
};
139
+
140
+
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
141
+
u8 port, u8 pin, u8 func)
142
+
{
143
+
unsigned long flags;
144
+
u32 reg;
145
+
146
+
spin_lock_irqsave(&pctrl->lock, flags);
147
+
148
+
/* Set pin to 'Non-use (Hi-Z input protection)' */
149
+
reg = readw(pctrl->base + PM(port));
150
+
reg &= ~(PM_MASK << (pin * 2));
151
+
writew(reg, pctrl->base + PM(port));
152
+
153
+
/* Temporarily switch to GPIO mode with PMC register */
154
+
reg = readb(pctrl->base + PMC(port));
155
+
writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
156
+
157
+
/* Set the PWPR register to allow PFC register to write */
158
+
writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
159
+
writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
160
+
161
+
/* Select Pin function mode with PFC register */
162
+
reg = readl(pctrl->base + PFC(port));
163
+
reg &= ~(PFC_MASK << (pin * 4));
164
+
writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
165
+
166
+
/* Set the PWPR register to be write-protected */
167
+
writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
168
+
writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
169
+
170
+
/* Switch to Peripheral pin function with PMC register */
171
+
reg = readb(pctrl->base + PMC(port));
172
+
writeb(reg | BIT(pin), pctrl->base + PMC(port));
173
+
174
+
spin_unlock_irqrestore(&pctrl->lock, flags);
175
+
};
176
+
177
+
static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
178
+
unsigned int func_selector,
179
+
unsigned int group_selector)
180
+
{
181
+
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
182
+
struct function_desc *func;
183
+
unsigned int i, *psel_val;
184
+
struct group_desc *group;
185
+
int *pins;
186
+
187
+
func = pinmux_generic_get_function(pctldev, func_selector);
188
+
if (!func)
189
+
return -EINVAL;
190
+
group = pinctrl_generic_get_group(pctldev, group_selector);
191
+
if (!group)
192
+
return -EINVAL;
193
+
194
+
psel_val = func->data;
195
+
pins = group->pins;
196
+
197
+
for (i = 0; i < group->num_pins; i++) {
198
+
dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
199
+
RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]),
200
+
psel_val[i]);
201
+
rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]),
202
+
RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
203
+
}
204
+
205
+
return 0;
206
+
};
207
+
208
+
static int rzg2l_map_add_config(struct pinctrl_map *map,
209
+
const char *group_or_pin,
210
+
enum pinctrl_map_type type,
211
+
unsigned long *configs,
212
+
unsigned int num_configs)
213
+
{
214
+
unsigned long *cfgs;
215
+
216
+
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
217
+
GFP_KERNEL);
218
+
if (!cfgs)
219
+
return -ENOMEM;
220
+
221
+
map->type = type;
222
+
map->data.configs.group_or_pin = group_or_pin;
223
+
map->data.configs.configs = cfgs;
224
+
map->data.configs.num_configs = num_configs;
225
+
226
+
return 0;
227
+
}
228
+
229
+
static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
230
+
struct device_node *np,
231
+
struct pinctrl_map **map,
232
+
unsigned int *num_maps,
233
+
unsigned int *index)
234
+
{
235
+
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
236
+
struct pinctrl_map *maps = *map;
237
+
unsigned int nmaps = *num_maps;
238
+
unsigned long *configs = NULL;
239
+
unsigned int *pins, *psel_val;
240
+
unsigned int num_pinmux = 0;
241
+
unsigned int idx = *index;
242
+
unsigned int num_pins, i;
243
+
unsigned int num_configs;
244
+
struct property *pinmux;
245
+
struct property *prop;
246
+
int ret, gsel, fsel;
247
+
const char **pin_fn;
248
+
const char *pin;
249
+
250
+
pinmux = of_find_property(np, "pinmux", NULL);
251
+
if (pinmux)
252
+
num_pinmux = pinmux->length / sizeof(u32);
253
+
254
+
ret = of_property_count_strings(np, "pins");
255
+
if (ret == -EINVAL) {
256
+
num_pins = 0;
257
+
} else if (ret < 0) {
258
+
dev_err(pctrl->dev, "Invalid pins list in DT\n");
259
+
return ret;
260
+
} else {
261
+
num_pins = ret;
262
+
}
263
+
264
+
if (!num_pinmux && !num_pins)
265
+
return 0;
266
+
267
+
if (num_pinmux && num_pins) {
268
+
dev_err(pctrl->dev,
269
+
"DT node must contain either a pinmux or pins and not both\n");
270
+
return -EINVAL;
271
+
}
272
+
273
+
ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
274
+
if (ret < 0)
275
+
return ret;
276
+
277
+
if (num_pins && !num_configs) {
278
+
dev_err(pctrl->dev, "DT node must contain a config\n");
279
+
ret = -ENODEV;
280
+
goto done;
281
+
}
282
+
283
+
if (num_pinmux)
284
+
nmaps += 1;
285
+
286
+
if (num_pins)
287
+
nmaps += num_pins;
288
+
289
+
maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
290
+
if (!maps) {
291
+
ret = -ENOMEM;
292
+
goto done;
293
+
}
294
+
295
+
*map = maps;
296
+
*num_maps = nmaps;
297
+
if (num_pins) {
298
+
of_property_for_each_string(np, "pins", prop, pin) {
299
+
ret = rzg2l_map_add_config(&maps[idx], pin,
300
+
PIN_MAP_TYPE_CONFIGS_PIN,
301
+
configs, num_configs);
302
+
if (ret < 0)
303
+
goto done;
304
+
305
+
idx++;
306
+
}
307
+
ret = 0;
308
+
goto done;
309
+
}
310
+
311
+
pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
312
+
psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
313
+
GFP_KERNEL);
314
+
pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
315
+
if (!pins || !psel_val || !pin_fn) {
316
+
ret = -ENOMEM;
317
+
goto done;
318
+
}
319
+
320
+
/* Collect pin locations and mux settings from DT properties */
321
+
for (i = 0; i < num_pinmux; ++i) {
322
+
u32 value;
323
+
324
+
ret = of_property_read_u32_index(np, "pinmux", i, &value);
325
+
if (ret)
326
+
goto done;
327
+
pins[i] = value & MUX_PIN_ID_MASK;
328
+
psel_val[i] = MUX_FUNC(value);
329
+
}
330
+
331
+
/* Register a single pin group listing all the pins we read from DT */
332
+
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
333
+
if (gsel < 0) {
334
+
ret = gsel;
335
+
goto done;
336
+
}
337
+
338
+
/*
339
+
* Register a single group function where the 'data' is an array PSEL
340
+
* register values read from DT.
341
+
*/
342
+
pin_fn[0] = np->name;
343
+
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
344
+
psel_val);
345
+
if (fsel < 0) {
346
+
ret = fsel;
347
+
goto remove_group;
348
+
}
349
+
350
+
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
351
+
maps[idx].data.mux.group = np->name;
352
+
maps[idx].data.mux.function = np->name;
353
+
idx++;
354
+
355
+
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
356
+
ret = 0;
357
+
goto done;
358
+
359
+
remove_group:
360
+
pinctrl_generic_remove_group(pctldev, gsel);
361
+
done:
362
+
*index = idx;
363
+
kfree(configs);
364
+
return ret;
365
+
}
366
+
367
+
static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
368
+
struct pinctrl_map *map,
369
+
unsigned int num_maps)
370
+
{
371
+
unsigned int i;
372
+
373
+
if (!map)
374
+
return;
375
+
376
+
for (i = 0; i < num_maps; ++i) {
377
+
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
378
+
map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
379
+
kfree(map[i].data.configs.configs);
380
+
}
381
+
kfree(map);
382
+
}
383
+
384
+
static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
385
+
struct device_node *np,
386
+
struct pinctrl_map **map,
387
+
unsigned int *num_maps)
388
+
{
389
+
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
390
+
struct device_node *child;
391
+
unsigned int index;
392
+
int ret;
393
+
394
+
*map = NULL;
395
+
*num_maps = 0;
396
+
index = 0;
397
+
398
+
for_each_child_of_node(np, child) {
399
+
ret = rzg2l_dt_subnode_to_map(pctldev, child, map,
400
+
num_maps, &index);
401
+
if (ret < 0) {
402
+
of_node_put(child);
403
+
goto done;
404
+
}
405
+
}
406
+
407
+
if (*num_maps == 0) {
408
+
ret = rzg2l_dt_subnode_to_map(pctldev, np, map,
409
+
num_maps, &index);
410
+
if (ret < 0)
411
+
goto done;
412
+
}
413
+
414
+
if (*num_maps)
415
+
return 0;
416
+
417
+
dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
418
+
ret = -EINVAL;
419
+
420
+
done:
421
+
if (ret < 0)
422
+
rzg2l_dt_free_map(pctldev, *map, *num_maps);
423
+
424
+
return ret;
425
+
}
426
+
427
+
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
428
+
unsigned int _pin,
429
+
unsigned long *config)
430
+
{
431
+
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
432
+
enum pin_config_param param = pinconf_to_config_param(*config);
433
+
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
434
+
unsigned int *pin_data = pin->drv_data;
435
+
unsigned int arg = 0;
436
+
unsigned long flags;
437
+
void __iomem *addr;
438
+
u32 port = 0, reg;
439
+
u32 cfg = 0;
440
+
u8 bit = 0;
441
+
442
+
if (!pin_data)
443
+
return -EINVAL;
444
+
445
+
if (*pin_data & RZG2L_SINGLE_PIN) {
446
+
port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);
447
+
cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
448
+
bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
449
+
}
450
+
451
+
switch (param) {
452
+
case PIN_CONFIG_INPUT_ENABLE:
453
+
if (!(cfg & PIN_CFG_IEN))
454
+
return -EINVAL;
455
+
spin_lock_irqsave(&pctrl->lock, flags);
456
+
/* handle _L/_H for 32-bit register read/write */
457
+
addr = pctrl->base + IEN(port);
458
+
if (bit >= 4) {
459
+
bit -= 4;
460
+
addr += 4;
461
+
}
462
+
463
+
reg = readl(addr) & (IEN_MASK << (bit * 8));
464
+
arg = (reg >> (bit * 8)) & 0x1;
465
+
spin_unlock_irqrestore(&pctrl->lock, flags);
466
+
break;
467
+
468
+
case PIN_CONFIG_POWER_SOURCE: {
469
+
u32 pwr_reg = 0x0;
470
+
471
+
if (cfg & PIN_CFG_IOLH_SD0)
472
+
pwr_reg = SD_CH(0);
473
+
else if (cfg & PIN_CFG_IOLH_SD1)
474
+
pwr_reg = SD_CH(1);
475
+
else if (cfg & PIN_CFG_IOLH_QSPI)
476
+
pwr_reg = QSPI;
477
+
else
478
+
return -EINVAL;
479
+
480
+
spin_lock_irqsave(&pctrl->lock, flags);
481
+
addr = pctrl->base + pwr_reg;
482
+
arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300;
483
+
spin_unlock_irqrestore(&pctrl->lock, flags);
484
+
break;
485
+
}
486
+
487
+
default:
488
+
return -ENOTSUPP;
489
+
}
490
+
491
+
*config = pinconf_to_config_packed(param, arg);
492
+
493
+
return 0;
494
+
};
495
+
496
+
static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
497
+
unsigned int _pin,
498
+
unsigned long *_configs,
499
+
unsigned int num_configs)
500
+
{
501
+
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
502
+
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
503
+
unsigned int *pin_data = pin->drv_data;
504
+
enum pin_config_param param;
505
+
unsigned long flags;
506
+
void __iomem *addr;
507
+
u32 port = 0, reg;
508
+
unsigned int i;
509
+
u32 cfg = 0;
510
+
u8 bit = 0;
511
+
512
+
if (!pin_data)
513
+
return -EINVAL;
514
+
515
+
if (*pin_data & RZG2L_SINGLE_PIN) {
516
+
port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);
517
+
cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
518
+
bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
519
+
}
520
+
521
+
for (i = 0; i < num_configs; i++) {
522
+
param = pinconf_to_config_param(_configs[i]);
523
+
switch (param) {
524
+
case PIN_CONFIG_INPUT_ENABLE: {
525
+
unsigned int arg =
526
+
pinconf_to_config_argument(_configs[i]);
527
+
528
+
if (!(cfg & PIN_CFG_IEN))
529
+
return -EINVAL;
530
+
531
+
/* handle _L/_H for 32-bit register read/write */
532
+
addr = pctrl->base + IEN(port);
533
+
if (bit >= 4) {
534
+
bit -= 4;
535
+
addr += 4;
536
+
}
537
+
538
+
spin_lock_irqsave(&pctrl->lock, flags);
539
+
reg = readl(addr) & ~(IEN_MASK << (bit * 8));
540
+
writel(reg | (arg << (bit * 8)), addr);
541
+
spin_unlock_irqrestore(&pctrl->lock, flags);
542
+
break;
543
+
}
544
+
545
+
case PIN_CONFIG_POWER_SOURCE: {
546
+
unsigned int mV = pinconf_to_config_argument(_configs[i]);
547
+
u32 pwr_reg = 0x0;
548
+
549
+
if (mV != 1800 && mV != 3300)
550
+
return -EINVAL;
551
+
552
+
if (cfg & PIN_CFG_IOLH_SD0)
553
+
pwr_reg = SD_CH(0);
554
+
else if (cfg & PIN_CFG_IOLH_SD1)
555
+
pwr_reg = SD_CH(1);
556
+
else if (cfg & PIN_CFG_IOLH_QSPI)
557
+
pwr_reg = QSPI;
558
+
else
559
+
return -EINVAL;
560
+
561
+
addr = pctrl->base + pwr_reg;
562
+
spin_lock_irqsave(&pctrl->lock, flags);
563
+
writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr);
564
+
spin_unlock_irqrestore(&pctrl->lock, flags);
565
+
break;
566
+
}
567
+
default:
568
+
return -EOPNOTSUPP;
569
+
}
570
+
}
571
+
572
+
return 0;
573
+
}
574
+
575
+
static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
576
+
unsigned int group,
577
+
unsigned long *configs,
578
+
unsigned int num_configs)
579
+
{
580
+
const unsigned int *pins;
581
+
unsigned int i, npins;
582
+
int ret;
583
+
584
+
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
585
+
if (ret)
586
+
return ret;
587
+
588
+
for (i = 0; i < npins; i++) {
589
+
ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
590
+
num_configs);
591
+
if (ret)
592
+
return ret;
593
+
}
594
+
595
+
return 0;
596
+
};
597
+
598
+
static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
599
+
unsigned int group,
600
+
unsigned long *config)
601
+
{
602
+
const unsigned int *pins;
603
+
unsigned int i, npins, prev_config = 0;
604
+
int ret;
605
+
606
+
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
607
+
if (ret)
608
+
return ret;
609
+
610
+
for (i = 0; i < npins; i++) {
611
+
ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
612
+
if (ret)
613
+
return ret;
614
+
615
+
/* Check config matching between to pin */
616
+
if (i && prev_config != *config)
617
+
return -EOPNOTSUPP;
618
+
619
+
prev_config = *config;
620
+
}
621
+
622
+
return 0;
623
+
};
624
+
625
+
static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
626
+
.get_groups_count = pinctrl_generic_get_group_count,
627
+
.get_group_name = pinctrl_generic_get_group_name,
628
+
.get_group_pins = pinctrl_generic_get_group_pins,
629
+
.dt_node_to_map = rzg2l_dt_node_to_map,
630
+
.dt_free_map = rzg2l_dt_free_map,
631
+
};
632
+
633
+
static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
634
+
.get_functions_count = pinmux_generic_get_function_count,
635
+
.get_function_name = pinmux_generic_get_function_name,
636
+
.get_function_groups = pinmux_generic_get_function_groups,
637
+
.set_mux = rzg2l_pinctrl_set_mux,
638
+
.strict = true,
639
+
};
640
+
641
+
static const struct pinconf_ops rzg2l_pinctrl_confops = {
642
+
.is_generic = true,
643
+
.pin_config_get = rzg2l_pinctrl_pinconf_get,
644
+
.pin_config_set = rzg2l_pinctrl_pinconf_set,
645
+
.pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
646
+
.pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
647
+
.pin_config_config_dbg_show = pinconf_generic_dump_config,
648
+
};
649
+
650
+
static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
651
+
{
652
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
653
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
654
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
655
+
unsigned long flags;
656
+
u8 reg8;
657
+
int ret;
658
+
659
+
ret = pinctrl_gpio_request(chip->base + offset);
660
+
if (ret)
661
+
return ret;
662
+
663
+
spin_lock_irqsave(&pctrl->lock, flags);
664
+
665
+
/* Select GPIO mode in PMC Register */
666
+
reg8 = readb(pctrl->base + PMC(port));
667
+
reg8 &= ~BIT(bit);
668
+
writeb(reg8, pctrl->base + PMC(port));
669
+
670
+
spin_unlock_irqrestore(&pctrl->lock, flags);
671
+
672
+
return 0;
673
+
}
674
+
675
+
static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port,
676
+
u8 bit, bool output)
677
+
{
678
+
unsigned long flags;
679
+
u16 reg16;
680
+
681
+
spin_lock_irqsave(&pctrl->lock, flags);
682
+
683
+
reg16 = readw(pctrl->base + PM(port));
684
+
reg16 &= ~(PM_MASK << (bit * 2));
685
+
686
+
reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
687
+
writew(reg16, pctrl->base + PM(port));
688
+
689
+
spin_unlock_irqrestore(&pctrl->lock, flags);
690
+
}
691
+
692
+
static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
693
+
{
694
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
695
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
696
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
697
+
698
+
if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) {
699
+
u16 reg16;
700
+
701
+
reg16 = readw(pctrl->base + PM(port));
702
+
reg16 = (reg16 >> (bit * 2)) & PM_MASK;
703
+
if (reg16 == PM_OUTPUT)
704
+
return GPIO_LINE_DIRECTION_OUT;
705
+
}
706
+
707
+
return GPIO_LINE_DIRECTION_IN;
708
+
}
709
+
710
+
static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
711
+
unsigned int offset)
712
+
{
713
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
714
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
715
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
716
+
717
+
rzg2l_gpio_set_direction(pctrl, port, bit, false);
718
+
719
+
return 0;
720
+
}
721
+
722
+
static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
723
+
int value)
724
+
{
725
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
726
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
727
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
728
+
unsigned long flags;
729
+
u8 reg8;
730
+
731
+
spin_lock_irqsave(&pctrl->lock, flags);
732
+
733
+
reg8 = readb(pctrl->base + P(port));
734
+
735
+
if (value)
736
+
writeb(reg8 | BIT(bit), pctrl->base + P(port));
737
+
else
738
+
writeb(reg8 & ~BIT(bit), pctrl->base + P(port));
739
+
740
+
spin_unlock_irqrestore(&pctrl->lock, flags);
741
+
}
742
+
743
+
static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
744
+
unsigned int offset, int value)
745
+
{
746
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
747
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
748
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
749
+
750
+
rzg2l_gpio_set(chip, offset, value);
751
+
rzg2l_gpio_set_direction(pctrl, port, bit, true);
752
+
753
+
return 0;
754
+
}
755
+
756
+
static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
757
+
{
758
+
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
759
+
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
760
+
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
761
+
u16 reg16;
762
+
763
+
reg16 = readw(pctrl->base + PM(port));
764
+
reg16 = (reg16 >> (bit * 2)) & PM_MASK;
765
+
766
+
if (reg16 == PM_INPUT)
767
+
return !!(readb(pctrl->base + PIN(port)) & BIT(bit));
768
+
else if (reg16 == PM_OUTPUT)
769
+
return !!(readb(pctrl->base + P(port)) & BIT(bit));
770
+
else
771
+
return -EINVAL;
772
+
}
773
+
774
+
static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
775
+
{
776
+
pinctrl_gpio_free(chip->base + offset);
777
+
778
+
/*
779
+
* Set the GPIO as an input to ensure that the next GPIO request won't
780
+
* drive the GPIO pin as an output.
781
+
*/
782
+
rzg2l_gpio_direction_input(chip, offset);
783
+
}
784
+
785
+
static const char * const rzg2l_gpio_names[] = {
786
+
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
787
+
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
788
+
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
789
+
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
790
+
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
791
+
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
792
+
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
793
+
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
794
+
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
795
+
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
796
+
"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
797
+
"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
798
+
"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
799
+
"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
800
+
"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
801
+
"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
802
+
"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
803
+
"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
804
+
"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
805
+
"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
806
+
"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
807
+
"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
808
+
"P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
809
+
"P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
810
+
"P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
811
+
"P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
812
+
"P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
813
+
"P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
814
+
"P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
815
+
"P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
816
+
"P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
817
+
"P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
818
+
"P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
819
+
"P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
820
+
"P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
821
+
"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
822
+
"P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
823
+
"P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
824
+
"P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
825
+
"P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
826
+
"P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
827
+
"P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
828
+
"P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
829
+
"P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
830
+
"P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
831
+
"P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
832
+
"P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
833
+
"P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
834
+
"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
835
+
};
836
+
837
+
static const u32 rzg2l_gpio_configs[] = {
838
+
RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
839
+
RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
840
+
RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
841
+
RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
842
+
RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
843
+
RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
844
+
RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
845
+
RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
846
+
RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
847
+
RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
848
+
RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
849
+
RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
850
+
RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
851
+
RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
852
+
RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
853
+
RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
854
+
RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
855
+
RZG2L_GPIO_PORT_PACK(3, 0x22, RZG2L_MPXED_PIN_FUNCS),
856
+
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
857
+
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
858
+
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
859
+
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
860
+
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
861
+
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
862
+
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
863
+
RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
864
+
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
865
+
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
866
+
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
867
+
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
868
+
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
869
+
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
870
+
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
871
+
RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
872
+
RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
873
+
RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
874
+
RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
875
+
RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
876
+
RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
877
+
RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
878
+
RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
879
+
RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
880
+
RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
881
+
RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
882
+
RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
883
+
RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
884
+
RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
885
+
RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
886
+
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
887
+
};
888
+
889
+
static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
890
+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
891
+
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
892
+
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
893
+
(PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) },
894
+
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
895
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) },
896
+
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
897
+
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
898
+
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
899
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
900
+
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
901
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
902
+
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
903
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
904
+
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
905
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
906
+
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
907
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
908
+
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
909
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
910
+
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
911
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
912
+
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
913
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
914
+
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
915
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
916
+
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
917
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
918
+
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
919
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
920
+
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
921
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))},
922
+
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
923
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
924
+
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
925
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
926
+
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
927
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
928
+
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
929
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
930
+
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
931
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
932
+
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
933
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
934
+
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
935
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
936
+
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
937
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
938
+
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
939
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
940
+
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
941
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
942
+
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
943
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
944
+
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
945
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
946
+
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
947
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
948
+
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
949
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
950
+
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
951
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
952
+
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
953
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
954
+
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
955
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
956
+
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
957
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
958
+
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
959
+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
960
+
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
961
+
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) },
962
+
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
963
+
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
964
+
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
965
+
{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
966
+
};
967
+
968
+
static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
969
+
{
970
+
struct device_node *np = pctrl->dev->of_node;
971
+
struct gpio_chip *chip = &pctrl->gpio_chip;
972
+
const char *name = dev_name(pctrl->dev);
973
+
struct of_phandle_args of_args;
974
+
int ret;
975
+
976
+
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
977
+
if (ret) {
978
+
dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
979
+
return ret;
980
+
}
981
+
982
+
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
983
+
of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) {
984
+
dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
985
+
return -EINVAL;
986
+
}
987
+
988
+
chip->names = rzg2l_gpio_names;
989
+
chip->request = rzg2l_gpio_request;
990
+
chip->free = rzg2l_gpio_free;
991
+
chip->get_direction = rzg2l_gpio_get_direction;
992
+
chip->direction_input = rzg2l_gpio_direction_input;
993
+
chip->direction_output = rzg2l_gpio_direction_output;
994
+
chip->get = rzg2l_gpio_get;
995
+
chip->set = rzg2l_gpio_set;
996
+
chip->label = name;
997
+
chip->parent = pctrl->dev;
998
+
chip->owner = THIS_MODULE;
999
+
chip->base = -1;
1000
+
chip->ngpio = of_args.args[2];
1001
+
1002
+
pctrl->gpio_range.id = 0;
1003
+
pctrl->gpio_range.pin_base = 0;
1004
+
pctrl->gpio_range.base = 0;
1005
+
pctrl->gpio_range.npins = chip->ngpio;
1006
+
pctrl->gpio_range.name = chip->label;
1007
+
pctrl->gpio_range.gc = chip;
1008
+
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1009
+
if (ret) {
1010
+
dev_err(pctrl->dev, "failed to add GPIO controller\n");
1011
+
return ret;
1012
+
}
1013
+
1014
+
dev_dbg(pctrl->dev, "Registered gpio controller\n");
1015
+
1016
+
return 0;
1017
+
}
1018
+
1019
+
static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
1020
+
{
1021
+
struct pinctrl_pin_desc *pins;
1022
+
unsigned int i, j;
1023
+
u32 *pin_data;
1024
+
int ret;
1025
+
1026
+
pctrl->desc.name = DRV_NAME;
1027
+
pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
1028
+
pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
1029
+
pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
1030
+
pctrl->desc.confops = &rzg2l_pinctrl_confops;
1031
+
pctrl->desc.owner = THIS_MODULE;
1032
+
1033
+
pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1034
+
if (!pins)
1035
+
return -ENOMEM;
1036
+
1037
+
pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1038
+
sizeof(*pin_data), GFP_KERNEL);
1039
+
if (!pin_data)
1040
+
return -ENOMEM;
1041
+
1042
+
pctrl->pins = pins;
1043
+
pctrl->desc.pins = pins;
1044
+
1045
+
for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1046
+
pins[i].number = i;
1047
+
pins[i].name = pctrl->data->port_pins[i];
1048
+
if (i && !(i % RZG2L_PINS_PER_PORT))
1049
+
j++;
1050
+
pin_data[i] = pctrl->data->port_pin_configs[j];
1051
+
pins[i].drv_data = &pin_data[i];
1052
+
}
1053
+
1054
+
for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1055
+
unsigned int index = pctrl->data->n_port_pins + i;
1056
+
1057
+
pins[index].number = index;
1058
+
pins[index].name = pctrl->data->dedicated_pins[i].name;
1059
+
pin_data[index] = pctrl->data->dedicated_pins[i].config;
1060
+
pins[index].drv_data = &pin_data[index];
1061
+
}
1062
+
1063
+
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1064
+
&pctrl->pctl);
1065
+
if (ret) {
1066
+
dev_err(pctrl->dev, "pinctrl registration failed\n");
1067
+
return ret;
1068
+
}
1069
+
1070
+
ret = pinctrl_enable(pctrl->pctl);
1071
+
if (ret) {
1072
+
dev_err(pctrl->dev, "pinctrl enable failed\n");
1073
+
return ret;
1074
+
}
1075
+
1076
+
ret = rzg2l_gpio_register(pctrl);
1077
+
if (ret) {
1078
+
dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1079
+
return ret;
1080
+
}
1081
+
1082
+
return 0;
1083
+
}
1084
+
1085
+
static void rzg2l_pinctrl_clk_disable(void *data)
1086
+
{
1087
+
clk_disable_unprepare(data);
1088
+
}
1089
+
1090
+
static int rzg2l_pinctrl_probe(struct platform_device *pdev)
1091
+
{
1092
+
struct rzg2l_pinctrl *pctrl;
1093
+
int ret;
1094
+
1095
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1096
+
if (!pctrl)
1097
+
return -ENOMEM;
1098
+
1099
+
pctrl->dev = &pdev->dev;
1100
+
1101
+
pctrl->data = of_device_get_match_data(&pdev->dev);
1102
+
if (!pctrl->data)
1103
+
return -EINVAL;
1104
+
1105
+
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1106
+
if (IS_ERR(pctrl->base))
1107
+
return PTR_ERR(pctrl->base);
1108
+
1109
+
pctrl->clk = devm_clk_get(pctrl->dev, NULL);
1110
+
if (IS_ERR(pctrl->clk)) {
1111
+
ret = PTR_ERR(pctrl->clk);
1112
+
dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
1113
+
return ret;
1114
+
}
1115
+
1116
+
spin_lock_init(&pctrl->lock);
1117
+
1118
+
platform_set_drvdata(pdev, pctrl);
1119
+
1120
+
ret = clk_prepare_enable(pctrl->clk);
1121
+
if (ret) {
1122
+
dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
1123
+
return ret;
1124
+
}
1125
+
1126
+
ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable,
1127
+
pctrl->clk);
1128
+
if (ret) {
1129
+
dev_err(pctrl->dev,
1130
+
"failed to register GPIO clk disable action, %i\n",
1131
+
ret);
1132
+
return ret;
1133
+
}
1134
+
1135
+
ret = rzg2l_pinctrl_register(pctrl);
1136
+
if (ret)
1137
+
return ret;
1138
+
1139
+
dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1140
+
return 0;
1141
+
}
1142
+
1143
+
static struct rzg2l_pinctrl_data r9a07g044_data = {
1144
+
.port_pins = rzg2l_gpio_names,
1145
+
.port_pin_configs = rzg2l_gpio_configs,
1146
+
.dedicated_pins = rzg2l_dedicated_pins,
1147
+
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
1148
+
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins),
1149
+
};
1150
+
1151
+
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
1152
+
{
1153
+
.compatible = "renesas,r9a07g044-pinctrl",
1154
+
.data = &r9a07g044_data,
1155
+
},
1156
+
{ /* sentinel */ }
1157
+
};
1158
+
1159
+
static struct platform_driver rzg2l_pinctrl_driver = {
1160
+
.driver = {
1161
+
.name = DRV_NAME,
1162
+
.of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
1163
+
},
1164
+
.probe = rzg2l_pinctrl_probe,
1165
+
};
1166
+
1167
+
static int __init rzg2l_pinctrl_init(void)
1168
+
{
1169
+
return platform_driver_register(&rzg2l_pinctrl_driver);
1170
+
}
1171
+
core_initcall(rzg2l_pinctrl_init);
1172
+
1173
+
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
1174
+
MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
1175
+
MODULE_LICENSE("GPL v2");
+23
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
+23
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* This header provides constants for Renesas RZ/G2L family pinctrl bindings.
4
+
*
5
+
* Copyright (C) 2021 Renesas Electronics Corp.
6
+
*
7
+
*/
8
+
9
+
#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
10
+
#define __DT_BINDINGS_RZG2L_PINCTRL_H
11
+
12
+
#define RZG2L_PINS_PER_PORT 8
13
+
14
+
/*
15
+
* Create the pin index from its bank and position numbers and store in
16
+
* the upper 16 bits the alternate function identifier
17
+
*/
18
+
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
19
+
20
+
/* Convert a port and pin label to its global pin index */
21
+
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
22
+
23
+
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */