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ARM: dts: sunxi: Use constants for RTC clock indexes

The binding header provides descriptive names for the RTC clock indexes,
since the indexes were arbitrarily chosen by the binding, not by the
hardware. Let's use the names, so the meaning is clearer.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220607012438.18183-1-samuel@sholland.org

authored by

Samuel Holland and committed by
Jernej Skrabec 8cce5702 4f05f03e

+43 -32
+7 -5
arch/arm/boot/dts/sun6i-a31.dtsi
··· 46 46 #include <dt-bindings/thermal/thermal.h> 47 47 48 48 #include <dt-bindings/clock/sun6i-a31-ccu.h> 49 + #include <dt-bindings/clock/sun6i-rtc.h> 49 50 #include <dt-bindings/reset/sun6i-a31-ccu.h> 50 51 51 52 / { ··· 599 598 ccu: clock@1c20000 { 600 599 compatible = "allwinner,sun6i-a31-ccu"; 601 600 reg = <0x01c20000 0x400>; 602 - clocks = <&osc24M>, <&rtc 0>; 601 + clocks = <&osc24M>, <&rtc CLK_OSC32K>; 603 602 clock-names = "hosc", "losc"; 604 603 #clock-cells = <1>; 605 604 #reset-cells = <1>; ··· 613 612 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 614 613 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 615 614 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 616 - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; 615 + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, 616 + <&rtc CLK_OSC32K>; 617 617 clock-names = "apb", "hosc", "losc"; 618 618 gpio-controller; 619 619 interrupt-controller; ··· 1321 1319 ar100: ar100_clk { 1322 1320 compatible = "allwinner,sun6i-a31-ar100-clk"; 1323 1321 #clock-cells = <0>; 1324 - clocks = <&rtc 0>, <&osc24M>, 1322 + clocks = <&rtc CLK_OSC32K>, <&osc24M>, 1325 1323 <&ccu CLK_PLL_PERIPH>, 1326 1324 <&ccu CLK_PLL_PERIPH>; 1327 1325 clock-output-names = "ar100"; ··· 1356 1354 ir_clk: ir_clk { 1357 1355 #clock-cells = <0>; 1358 1356 compatible = "allwinner,sun4i-a10-mod0-clk"; 1359 - clocks = <&rtc 0>, <&osc24M>; 1357 + clocks = <&rtc CLK_OSC32K>, <&osc24M>; 1360 1358 clock-output-names = "ir"; 1361 1359 }; 1362 1360 ··· 1387 1385 interrupt-parent = <&r_intc>; 1388 1386 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1389 1387 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1390 - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 1388 + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; 1391 1389 clock-names = "apb", "hosc", "losc"; 1392 1390 resets = <&apb0_rst 0>; 1393 1391 gpio-controller;
+5 -3
arch/arm/boot/dts/sun8i-a23-a33.dtsi
··· 44 44 45 45 #include <dt-bindings/interrupt-controller/arm-gic.h> 46 46 47 + #include <dt-bindings/clock/sun6i-rtc.h> 47 48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 48 49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 49 50 ··· 330 329 331 330 ccu: clock@1c20000 { 332 331 reg = <0x01c20000 0x400>; 333 - clocks = <&osc24M>, <&rtc 0>; 332 + clocks = <&osc24M>, <&rtc CLK_OSC32K>; 334 333 clock-names = "hosc", "losc"; 335 334 #clock-cells = <1>; 336 335 #reset-cells = <1>; ··· 341 340 reg = <0x01c20800 0x400>; 342 341 interrupt-parent = <&r_intc>; 343 342 /* interrupts get set in SoC specific dtsi file */ 344 - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 343 + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 344 + <&rtc CLK_OSC32K>; 345 345 clock-names = "apb", "hosc", "losc"; 346 346 gpio-controller; 347 347 interrupt-controller; ··· 812 810 reg = <0x01f02c00 0x400>; 813 811 interrupt-parent = <&r_intc>; 814 812 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 815 - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 813 + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; 816 814 clock-names = "apb", "hosc", "losc"; 817 815 resets = <&apb0_rst 0>; 818 816 gpio-controller;
+2 -2
arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
··· 106 106 wifi_pwrseq: wifi_pwrseq { 107 107 compatible = "mmc-pwrseq-simple"; 108 108 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ 109 - clocks = <&rtc 1>; 109 + clocks = <&rtc CLK_OSC32K_FANOUT>; 110 110 clock-names = "ext_clock"; 111 111 }; 112 112 }; ··· 181 181 bluetooth { 182 182 compatible = "brcm,bcm43438-bt"; 183 183 max-speed = <1500000>; 184 - clocks = <&rtc 1>; 184 + clocks = <&rtc CLK_OSC32K_FANOUT>; 185 185 clock-names = "lpo"; 186 186 vbat-supply = <&reg_vcc3v3>; 187 187 vddio-supply = <&reg_vcc3v3>;
+2 -2
arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
··· 90 90 wifi_pwrseq: wifi_pwrseq { 91 91 compatible = "mmc-pwrseq-simple"; 92 92 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ 93 - clocks = <&rtc 1>; 93 + clocks = <&rtc CLK_OSC32K_FANOUT>; 94 94 clock-names = "ext_clock"; 95 95 }; 96 96 ··· 151 151 152 152 bluetooth { 153 153 compatible = "brcm,bcm43438-bt"; 154 - clocks = <&rtc 1>; 154 + clocks = <&rtc CLK_OSC32K_FANOUT>; 155 155 clock-names = "lpo"; 156 156 vbat-supply = <&reg_vcc3v3>; 157 157 vddio-supply = <&reg_vcc3v3>;
+1 -1
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
··· 127 127 128 128 bluetooth { 129 129 compatible = "brcm,bcm43438-bt"; 130 - clocks = <&rtc 1>; 130 + clocks = <&rtc CLK_OSC32K_FANOUT>; 131 131 clock-names = "lpo"; 132 132 vbat-supply = <&reg_vcc3v3>; 133 133 vddio-supply = <&reg_vcc3v3>;
+2 -2
arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
··· 46 46 wifi_pwrseq: wifi_pwrseq { 47 47 compatible = "mmc-pwrseq-simple"; 48 48 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ 49 - clocks = <&rtc 1>; 49 + clocks = <&rtc CLK_OSC32K_FANOUT>; 50 50 clock-names = "ext_clock"; 51 51 }; 52 52 ··· 147 147 148 148 bluetooth { 149 149 compatible = "brcm,bcm43438-bt"; 150 - clocks = <&rtc 1>; 150 + clocks = <&rtc CLK_OSC32K_FANOUT>; 151 151 clock-names = "lpo"; 152 152 vbat-supply = <&reg_vcc3v3>; 153 153 vddio-supply = <&reg_vcc3v3>;
+2 -2
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
··· 91 91 wifi_pwrseq: wifi_pwrseq { 92 92 compatible = "mmc-pwrseq-simple"; 93 93 reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ 94 - clocks = <&rtc 1>; 94 + clocks = <&rtc CLK_OSC32K_FANOUT>; 95 95 clock-names = "ext_clock"; 96 96 }; 97 97 }; ··· 283 283 284 284 bluetooth { 285 285 compatible = "brcm,bcm43438-bt"; 286 - clocks = <&rtc 1>; 286 + clocks = <&rtc CLK_OSC32K_FANOUT>; 287 287 clock-names = "lpo"; 288 288 vbat-supply = <&reg_dldo1>; 289 289 vddio-supply = <&reg_aldo3>;
+5 -3
arch/arm/boot/dts/sun8i-r40.dtsi
··· 42 42 */ 43 43 44 44 #include <dt-bindings/interrupt-controller/arm-gic.h> 45 + #include <dt-bindings/clock/sun6i-rtc.h> 45 46 #include <dt-bindings/clock/sun8i-de2.h> 46 47 #include <dt-bindings/clock/sun8i-r40-ccu.h> 47 48 #include <dt-bindings/clock/sun8i-tcon-top.h> ··· 486 485 ccu: clock@1c20000 { 487 486 compatible = "allwinner,sun8i-r40-ccu"; 488 487 reg = <0x01c20000 0x400>; 489 - clocks = <&osc24M>, <&rtc 0>; 488 + clocks = <&osc24M>, <&rtc CLK_OSC32K>; 490 489 clock-names = "hosc", "losc"; 491 490 #clock-cells = <1>; 492 491 #reset-cells = <1>; ··· 505 504 compatible = "allwinner,sun8i-r40-pinctrl"; 506 505 reg = <0x01c20800 0x400>; 507 506 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 508 - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 507 + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 508 + <&rtc CLK_OSC32K>; 509 509 clock-names = "apb", "hosc", "losc"; 510 510 gpio-controller; 511 511 interrupt-controller; ··· 1233 1231 reg-io-width = <1>; 1234 1232 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1235 1233 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 1236 - <&ccu CLK_HDMI>, <&rtc 0>; 1234 + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1237 1235 clock-names = "iahb", "isfr", "tmds", "cec"; 1238 1236 resets = <&ccu RST_BUS_HDMI1>; 1239 1237 reset-names = "ctrl";
+4 -2
arch/arm/boot/dts/sun8i-v3s.dtsi
··· 42 42 */ 43 43 44 44 #include <dt-bindings/interrupt-controller/arm-gic.h> 45 + #include <dt-bindings/clock/sun6i-rtc.h> 45 46 #include <dt-bindings/clock/sun8i-v3s-ccu.h> 46 47 #include <dt-bindings/reset/sun8i-v3s-ccu.h> 47 48 #include <dt-bindings/clock/sun8i-de2.h> ··· 322 321 ccu: clock@1c20000 { 323 322 compatible = "allwinner,sun8i-v3s-ccu"; 324 323 reg = <0x01c20000 0x400>; 325 - clocks = <&osc24M>, <&rtc 0>; 324 + clocks = <&osc24M>, <&rtc CLK_OSC32K>; 326 325 clock-names = "hosc", "losc"; 327 326 #clock-cells = <1>; 328 327 #reset-cells = <1>; ··· 343 342 reg = <0x01c20800 0x400>; 344 343 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 345 344 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 346 - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 345 + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 346 + <&rtc CLK_OSC32K>; 347 347 clock-names = "apb", "hosc", "losc"; 348 348 gpio-controller; 349 349 #gpio-cells = <3>;
+2 -2
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
··· 101 101 wifi_pwrseq: wifi_pwrseq { 102 102 compatible = "mmc-pwrseq-simple"; 103 103 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ 104 - clocks = <&rtc 1>; 104 + clocks = <&rtc CLK_OSC32K_FANOUT>; 105 105 clock-names = "ext_clock"; 106 106 }; 107 107 }; ··· 221 221 bluetooth { 222 222 compatible = "brcm,bcm43438-bt"; 223 223 max-speed = <1500000>; 224 - clocks = <&rtc 1>; 224 + clocks = <&rtc CLK_OSC32K_FANOUT>; 225 225 clock-names = "lpo"; 226 226 vbat-supply = <&reg_vcc3v3>; 227 227 vddio-supply = <&reg_vcc3v3>;
+2 -2
arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
··· 22 22 compatible = "mmc-pwrseq-simple"; 23 23 reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ 24 24 post-power-on-delay-ms = <200>; 25 - clocks = <&rtc 1>; 25 + clocks = <&rtc CLK_OSC32K_FANOUT>; 26 26 clock-names = "ext_clock"; 27 27 }; 28 28 }; ··· 124 124 125 125 bluetooth { 126 126 compatible = "brcm,bcm43438-bt"; 127 - clocks = <&rtc 1>; 127 + clocks = <&rtc CLK_OSC32K_FANOUT>; 128 128 clock-names = "lpo"; 129 129 vbat-supply = <&reg_vcc3v3>; 130 130 vddio-supply = <&reg_vcc3v3>;
+8 -5
arch/arm/boot/dts/sunxi-h3-h5.dtsi
··· 40 40 * OTHER DEALINGS IN THE SOFTWARE. 41 41 */ 42 42 43 + #include <dt-bindings/clock/sun6i-rtc.h> 43 44 #include <dt-bindings/clock/sun8i-de2.h> 44 45 #include <dt-bindings/clock/sun8i-h3-ccu.h> 45 46 #include <dt-bindings/clock/sun8i-r-ccu.h> ··· 387 386 ccu: clock@1c20000 { 388 387 /* compatible is in per SoC .dtsi file */ 389 388 reg = <0x01c20000 0x400>; 390 - clocks = <&osc24M>, <&rtc 0>; 389 + clocks = <&osc24M>, <&rtc CLK_OSC32K>; 391 390 clock-names = "hosc", "losc"; 392 391 #clock-cells = <1>; 393 392 #reset-cells = <1>; ··· 399 398 interrupt-parent = <&r_intc>; 400 399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 401 400 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 402 - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 401 + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 402 + <&rtc CLK_OSC32K>; 403 403 clock-names = "apb", "hosc", "losc"; 404 404 gpio-controller; 405 405 #gpio-cells = <3>; ··· 820 818 reg-io-width = <1>; 821 819 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 822 820 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 823 - <&ccu CLK_HDMI>, <&rtc 0>; 821 + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 824 822 clock-names = "iahb", "isfr", "tmds", "cec"; 825 823 resets = <&ccu RST_BUS_HDMI1>; 826 824 reset-names = "ctrl"; ··· 880 878 r_ccu: clock@1f01400 { 881 879 compatible = "allwinner,sun8i-h3-r-ccu"; 882 880 reg = <0x01f01400 0x100>; 883 - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 881 + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 884 882 <&ccu CLK_PLL_PERIPH0>; 885 883 clock-names = "hosc", "losc", "iosc", "pll-periph"; 886 884 #clock-cells = <1>; ··· 933 931 reg = <0x01f02c00 0x400>; 934 932 interrupt-parent = <&r_intc>; 935 933 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 936 - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; 934 + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 935 + <&rtc CLK_OSC32K>; 937 936 clock-names = "apb", "hosc", "losc"; 938 937 gpio-controller; 939 938 #gpio-cells = <3>;