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kernel
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linux
net/mlx5: Expose mlx5e_link_mode
The mlx5e_link_mode enumeration will also be used in mlx5_ib for RoCE.
This patch moves the enumeration to the mlx5 driver port header file.
Signed-off-by: Noa Osherovich <noaos@mellanox.com>
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
authored by
Noa Osherovich
and committed by
Leon Romanovsky
8cca30a7
2e353b34
+33
-34
-34
drivers/net/ethernet/mellanox/mlx5/core/en.h
-34
drivers/net/ethernet/mellanox/mlx5/core/en.h
···
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void *ppriv;
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};
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654
-
enum mlx5e_link_mode {
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MLX5E_1000BASE_CX_SGMII = 0,
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MLX5E_1000BASE_KX = 1,
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MLX5E_10GBASE_CX4 = 2,
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MLX5E_10GBASE_KX4 = 3,
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MLX5E_10GBASE_KR = 4,
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MLX5E_20GBASE_KR2 = 5,
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MLX5E_40GBASE_CR4 = 6,
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MLX5E_40GBASE_KR4 = 7,
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MLX5E_56GBASE_R4 = 8,
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MLX5E_10GBASE_CR = 12,
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MLX5E_10GBASE_SR = 13,
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MLX5E_10GBASE_ER = 14,
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MLX5E_40GBASE_SR4 = 15,
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MLX5E_40GBASE_LR4 = 16,
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MLX5E_50GBASE_SR2 = 18,
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MLX5E_100GBASE_CR4 = 20,
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MLX5E_100GBASE_SR4 = 21,
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MLX5E_100GBASE_KR4 = 22,
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MLX5E_100GBASE_LR4 = 23,
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MLX5E_100BASE_TX = 24,
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MLX5E_1000BASE_T = 25,
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MLX5E_10GBASE_T = 26,
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MLX5E_25GBASE_CR = 27,
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MLX5E_25GBASE_KR = 28,
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MLX5E_25GBASE_SR = 29,
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MLX5E_50GBASE_CR2 = 30,
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MLX5E_50GBASE_KR2 = 31,
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MLX5E_LINK_MODES_NUMBER,
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-
};
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#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
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-
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void mlx5e_build_ptys2ethtool_map(void);
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void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
+33
include/linux/mlx5/port.h
+33
include/linux/mlx5/port.h
···
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#define MLX5_I2C_ADDR_HIGH 0x51
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#define MLX5_EEPROM_PAGE_LENGTH 256
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+
enum mlx5e_link_mode {
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MLX5E_1000BASE_CX_SGMII = 0,
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+
MLX5E_1000BASE_KX = 1,
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+
MLX5E_10GBASE_CX4 = 2,
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MLX5E_10GBASE_KX4 = 3,
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MLX5E_10GBASE_KR = 4,
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MLX5E_20GBASE_KR2 = 5,
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MLX5E_40GBASE_CR4 = 6,
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MLX5E_40GBASE_KR4 = 7,
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MLX5E_56GBASE_R4 = 8,
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MLX5E_10GBASE_CR = 12,
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+
MLX5E_10GBASE_SR = 13,
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MLX5E_10GBASE_ER = 14,
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MLX5E_40GBASE_SR4 = 15,
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MLX5E_40GBASE_LR4 = 16,
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+
MLX5E_50GBASE_SR2 = 18,
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MLX5E_100GBASE_CR4 = 20,
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MLX5E_100GBASE_SR4 = 21,
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MLX5E_100GBASE_KR4 = 22,
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MLX5E_100GBASE_LR4 = 23,
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MLX5E_100BASE_TX = 24,
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MLX5E_1000BASE_T = 25,
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+
MLX5E_10GBASE_T = 26,
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MLX5E_25GBASE_CR = 27,
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MLX5E_25GBASE_KR = 28,
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MLX5E_25GBASE_SR = 29,
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MLX5E_50GBASE_CR2 = 30,
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MLX5E_50GBASE_KR2 = 31,
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MLX5E_LINK_MODES_NUMBER,
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};
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+
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#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
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+
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int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
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int ptys_size, int proto_mask, u8 local_port);