crypto: qat - reduce stack size with KASAN

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Passing the register value by reference here leads a large amount of stack being
used when CONFIG_KASAN is enabled:

drivers/crypto/qat/qat_common/qat_hal.c: In function 'qat_hal_exec_micro_inst.constprop':
drivers/crypto/qat/qat_common/qat_hal.c:963:1: error: the frame size of 1792 bytes is larger than 1536 bytes [-Werror=frame-larger-than=]

Changing the register-read function to return the value instead reduces the stack
size to around 800 bytes, most of which is for the 'savuwords' array. The function
now no longer returns an error code, but nothing ever evaluated that anyway.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Arnd Bergmann and committed by

Herbert Xu 8 years ago 8c9478a4 3a2d4fb5

+67 -66

1 changed file

expand all

drivers

crypto

qat

qat_common

qat_hal.c

+67 -66

drivers/crypto/qat/qat_common/qat_hal.c

··· 117 117 118 118 #define CSR_RETRY_TIMES 500 119 119 static int qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, 120 - unsigned char ae, unsigned int csr, 121 - unsigned int *value) 120 + unsigned char ae, unsigned int csr) 122 121 { 123 122 unsigned int iterations = CSR_RETRY_TIMES; 123 + int value; 124 124 125 125 do { 126 - *value = GET_AE_CSR(handle, ae, csr); 126 + value = GET_AE_CSR(handle, ae, csr); 127 127 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) 128 - return 0; 128 + return value; 129 129 } while (iterations--); 130 130 131 131 pr_err("QAT: Read CSR timeout\n"); 132 - return -EFAULT; 132 + return 0; 133 133 } 134 134 135 135 static int qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, ··· 154 154 { 155 155 unsigned int cur_ctx; 156 156 157 - qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); 157 + cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); 158 158 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); 159 - qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, events); 159 + *events = qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT); 160 160 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); 161 161 } 162 162 ··· 169 169 int times = MAX_RETRY_TIMES; 170 170 int elapsed_cycles = 0; 171 171 172 - qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &base_cnt); 172 + base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); 173 173 base_cnt &= 0xffff; 174 174 while ((int)cycles > elapsed_cycles && times--) { 175 175 if (chk_inactive) 176 - qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); 176 + csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); 177 177 178 - qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &cur_cnt); 178 + cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); 179 179 cur_cnt &= 0xffff; 180 180 elapsed_cycles = cur_cnt - base_cnt; 181 181 ··· 207 207 } 208 208 209 209 /* Sets the accelaration engine context mode to either four or eight */ 210 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); 210 + csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 211 211 csr = IGNORE_W1C_MASK & csr; 212 212 new_csr = (mode == 4) ? 213 213 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) : ··· 221 221 { 222 222 unsigned int csr, new_csr; 223 223 224 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); 224 + csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 225 225 csr &= IGNORE_W1C_MASK; 226 226 227 227 new_csr = (mode) ? ··· 240 240 { 241 241 unsigned int csr, new_csr; 242 242 243 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); 243 + csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 244 244 csr &= IGNORE_W1C_MASK; 245 245 switch (lm_type) { 246 246 case ICP_LMEM0: ··· 328 328 { 329 329 unsigned int ctx, cur_ctx; 330 330 331 - qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); 331 + cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); 332 332 333 333 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { 334 334 if (!(ctx_mask & (1 << ctx))) ··· 340 340 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); 341 341 } 342 342 343 - static void qat_hal_rd_indr_csr(struct icp_qat_fw_loader_handle *handle, 343 + static unsigned int qat_hal_rd_indr_csr(struct icp_qat_fw_loader_handle *handle, 344 344 unsigned char ae, unsigned char ctx, 345 - unsigned int ae_csr, unsigned int *csr_val) 345 + unsigned int ae_csr) 346 346 { 347 - unsigned int cur_ctx; 347 + unsigned int cur_ctx, csr_val; 348 348 349 - qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); 349 + cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); 350 350 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); 351 - qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val); 351 + csr_val = qat_hal_rd_ae_csr(handle, ae, ae_csr); 352 352 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); 353 + 354 + return csr_val; 353 355 } 354 356 355 357 static void qat_hal_put_sig_event(struct icp_qat_fw_loader_handle *handle, ··· 360 358 { 361 359 unsigned int ctx, cur_ctx; 362 360 363 - qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); 361 + cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); 364 362 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { 365 363 if (!(ctx_mask & (1 << ctx))) 366 364 continue; ··· 376 374 { 377 375 unsigned int ctx, cur_ctx; 378 376 379 - qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); 377 + cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); 380 378 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { 381 379 if (!(ctx_mask & (1 << ctx))) 382 380 continue; ··· 394 392 int times = MAX_RETRY_TIMES; 395 393 396 394 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { 397 - qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, 398 - (unsigned int *)&base_cnt); 395 + base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); 399 396 base_cnt &= 0xffff; 400 397 401 398 do { 402 - qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, 403 - (unsigned int *)&cur_cnt); 399 + cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); 404 400 cur_cnt &= 0xffff; 405 401 } while (times-- && (cur_cnt == base_cnt)); 406 402 ··· 416 416 { 417 417 unsigned int enable = 0, active = 0; 418 418 419 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable); 420 - qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active); 419 + enable = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 420 + active = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); 421 421 if ((enable & (0xff << CE_ENABLE_BITPOS)) || 422 422 (active & (1 << ACS_ABO_BITPOS))) 423 423 return 1; ··· 540 540 { 541 541 unsigned int ctx; 542 542 543 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); 543 + ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 544 544 ctx &= IGNORE_W1C_MASK & 545 545 (~((ctx_mask & ICP_QAT_UCLO_AE_ALL_CTX) << CE_ENABLE_BITPOS)); 546 546 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); ··· 583 583 unsigned int ustore_addr; 584 584 unsigned int i; 585 585 586 - qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); 586 + ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); 587 587 uaddr |= UA_ECS; 588 588 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); 589 589 for (i = 0; i < words_num; i++) { ··· 604 604 { 605 605 unsigned int ctx; 606 606 607 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); 607 + ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 608 608 ctx &= IGNORE_W1C_MASK; 609 609 ctx_mask &= (ctx & CE_INUSE_CONTEXTS) ? 0x55 : 0xFF; 610 610 ctx |= (ctx_mask << CE_ENABLE_BITPOS); ··· 636 636 int ret = 0; 637 637 638 638 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { 639 - qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); 639 + csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); 640 640 csr_val &= ~(1 << MMC_SHARE_CS_BITPOS); 641 641 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); 642 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val); 642 + csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 643 643 csr_val &= IGNORE_W1C_MASK; 644 644 csr_val |= CE_NN_MODE; 645 645 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); ··· 648 648 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, 649 649 handle->hal_handle->upc_mask & 650 650 INIT_PC_VALUE); 651 - qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); 651 + savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); 652 652 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0); 653 653 qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY); 654 654 qat_hal_wr_indr_csr(handle, ae, ctx_mask, ··· 760 760 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { 761 761 unsigned int csr_val = 0; 762 762 763 - qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val); 763 + csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE); 764 764 csr_val |= 0x1; 765 765 qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); 766 766 } ··· 826 826 unsigned int i, uwrd_lo, uwrd_hi; 827 827 unsigned int ustore_addr, misc_control; 828 828 829 - qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &misc_control); 829 + misc_control = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); 830 830 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, 831 831 misc_control & 0xfffffffb); 832 - qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); 832 + ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); 833 833 uaddr |= UA_ECS; 834 834 for (i = 0; i < words_num; i++) { 835 835 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); 836 836 uaddr++; 837 - qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER, &uwrd_lo); 838 - qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER, &uwrd_hi); 837 + uwrd_lo = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER); 838 + uwrd_hi = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER); 839 839 uword[i] = uwrd_hi; 840 840 uword[i] = (uword[i] << 0x20) | uwrd_lo; 841 841 } ··· 849 849 { 850 850 unsigned int i, ustore_addr; 851 851 852 - qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); 852 + ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); 853 853 uaddr |= UA_ECS; 854 854 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); 855 855 for (i = 0; i < words_num; i++) { ··· 890 890 return -EINVAL; 891 891 } 892 892 /* save current context */ 893 - qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0); 894 - qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1); 895 - qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_0_BYTE_INDEX, 896 - &ind_lm_addr_byte0); 897 - qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_1_BYTE_INDEX, 898 - &ind_lm_addr_byte1); 893 + ind_lm_addr0 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT); 894 + ind_lm_addr1 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT); 895 + ind_lm_addr_byte0 = qat_hal_rd_indr_csr(handle, ae, ctx, 896 + INDIRECT_LM_ADDR_0_BYTE_INDEX); 897 + ind_lm_addr_byte1 = qat_hal_rd_indr_csr(handle, ae, ctx, 898 + INDIRECT_LM_ADDR_1_BYTE_INDEX); 899 899 if (inst_num <= MAX_EXEC_INST) 900 900 qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords); 901 901 qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events); 902 - qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, &savpc); 902 + savpc = qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT); 903 903 savpc = (savpc & handle->hal_handle->upc_mask) >> 0; 904 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 904 + ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 905 905 ctx_enables &= IGNORE_W1C_MASK; 906 - qat_hal_rd_ae_csr(handle, ae, CC_ENABLE, &savcc); 907 - qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); 908 - qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_ctl); 909 - qat_hal_rd_indr_csr(handle, ae, ctx, FUTURE_COUNT_SIGNAL_INDIRECT, 910 - &ind_cnt_sig); 911 - qat_hal_rd_indr_csr(handle, ae, ctx, CTX_SIG_EVENTS_INDIRECT, &ind_sig); 912 - qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, &act_sig); 906 + savcc = qat_hal_rd_ae_csr(handle, ae, CC_ENABLE); 907 + savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); 908 + ctxarb_ctl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL); 909 + ind_cnt_sig = qat_hal_rd_indr_csr(handle, ae, ctx, 910 + FUTURE_COUNT_SIGNAL_INDIRECT); 911 + ind_sig = qat_hal_rd_indr_csr(handle, ae, ctx, 912 + CTX_SIG_EVENTS_INDIRECT); 913 + act_sig = qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE); 913 914 /* execute micro codes */ 914 915 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); 915 916 qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst); ··· 928 927 if (endpc) { 929 928 unsigned int ctx_status; 930 929 931 - qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, 932 - &ctx_status); 930 + ctx_status = qat_hal_rd_indr_csr(handle, ae, ctx, 931 + CTX_STS_INDIRECT); 933 932 *endpc = ctx_status & handle->hal_handle->upc_mask; 934 933 } 935 934 /* retore to saved context */ ··· 939 938 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events); 940 939 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 941 940 handle->hal_handle->upc_mask & savpc); 942 - qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); 941 + csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); 943 942 newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS); 944 943 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val); 945 944 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc); ··· 987 986 insts = (uint64_t)0xA030000000ull | ((reg_addr & 0x3ff) << 10); 988 987 break; 989 988 } 990 - qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); 991 - qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_cntl); 992 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 989 + savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); 990 + ctxarb_cntl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL); 991 + ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 993 992 ctx_enables &= IGNORE_W1C_MASK; 994 993 if (ctx != (savctx & ACS_ACNO)) 995 994 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 996 995 ctx & ACS_ACNO); 997 996 qat_hal_get_uwords(handle, ae, 0, 1, &savuword); 998 997 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); 999 - qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); 998 + ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); 1000 999 uaddr = UA_ECS; 1001 1000 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); 1002 1001 insts = qat_hal_set_uword_ecc(insts); ··· 1012 1011 * the instruction should have been executed 1013 1012 * prior to clearing the ECS in putUwords 1014 1013 */ 1015 - qat_hal_rd_ae_csr(handle, ae, ALU_OUT, data); 1014 + *data = qat_hal_rd_ae_csr(handle, ae, ALU_OUT); 1016 1015 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); 1017 1016 qat_hal_wr_uwords(handle, ae, 0, 1, &savuword); 1018 1017 if (ctx != (savctx & ACS_ACNO)) ··· 1189 1188 unsigned short mask; 1190 1189 unsigned short dr_offset = 0x10; 1191 1190 1192 - status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 1191 + status = ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 1193 1192 if (CE_INUSE_CONTEXTS & ctx_enables) { 1194 1193 if (ctx & 0x1) { 1195 1194 pr_err("QAT: bad 4-ctx mode,ctx=0x%x\n", ctx); ··· 1239 1238 const int num_inst = ARRAY_SIZE(micro_inst), code_off = 1; 1240 1239 const unsigned short gprnum = 0, dly = num_inst * 0x5; 1241 1240 1242 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 1241 + ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 1243 1242 if (CE_INUSE_CONTEXTS & ctx_enables) { 1244 1243 if (ctx & 0x1) { 1245 1244 pr_err("QAT: 4-ctx mode,ctx=0x%x\n", ctx); ··· 1283 1282 unsigned int ctx_enables; 1284 1283 int stat = 0; 1285 1284 1286 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 1285 + ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 1287 1286 ctx_enables &= IGNORE_W1C_MASK; 1288 1287 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE); 1289 1288 ··· 1300 1299 { 1301 1300 unsigned int ctx_enables; 1302 1301 1303 - qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); 1302 + ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); 1304 1303 if (ctx_enables & CE_INUSE_CONTEXTS) { 1305 1304 /* 4-ctx mode */ 1306 1305 *relreg = absreg_num & 0x1F;