Merge tag 'qcom-dts-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

+15 -10

arch/arm/boot/dts/qcom-apq8060-dragonboard.dts

··· 1 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 #include <dt-bindings/input/input.h> 3 3 #include <dt-bindings/gpio/gpio.h> 4 + #include <dt-bindings/leds/common.h> 4 5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 5 6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 6 7 #include "qcom-msm8660.dtsi" ··· 274 273 }; 275 274 276 275 gpio@150 { 277 - dragon_ethernet_gpios: ethernet-gpios { 276 + dragon_ethernet_gpios: ethernet-state { 278 277 pinconf { 279 278 pins = "gpio7"; 280 279 function = "normal"; ··· 283 282 power-source = <PM8058_GPIO_S3>; 284 283 }; 285 284 }; 286 - dragon_bmp085_gpios: bmp085-gpios { 285 + dragon_bmp085_gpios: bmp085-state { 287 286 pinconf { 288 287 pins = "gpio16"; 289 288 function = "normal"; ··· 292 291 power-source = <PM8058_GPIO_S3>; 293 292 }; 294 293 }; 295 - dragon_mpu3050_gpios: mpu3050-gpios { 294 + dragon_mpu3050_gpios: mpu3050-state { 296 295 pinconf { 297 296 pins = "gpio17"; 298 297 function = "normal"; ··· 301 300 power-source = <PM8058_GPIO_S3>; 302 301 }; 303 302 }; 304 - dragon_sdcc3_gpios: sdcc3-gpios { 303 + dragon_sdcc3_gpios: sdcc3-state { 305 304 pinconf { 306 305 pins = "gpio22"; 307 306 function = "normal"; ··· 310 309 power-source = <PM8058_GPIO_S3>; 311 310 }; 312 311 }; 313 - dragon_sdcc5_gpios: sdcc5-gpios { 312 + dragon_sdcc5_gpios: sdcc5-state { 314 313 pinconf { 315 314 pins = "gpio26"; 316 315 function = "normal"; ··· 320 319 power-source = <PM8058_GPIO_S3>; 321 320 }; 322 321 }; 323 - dragon_ak8975_gpios: ak8975-gpios { 322 + dragon_ak8975_gpios: ak8975-state { 324 323 pinconf { 325 324 pins = "gpio33"; 326 325 function = "normal"; ··· 329 328 power-source = <PM8058_GPIO_S3>; 330 329 }; 331 330 }; 332 - dragon_cm3605_gpios: cm3605-gpios { 331 + dragon_cm3605_gpios: cm3605-state { 333 332 /* Pin 34 connected to the proxy IRQ */ 334 - pinconf_gpio34 { 333 + gpio34-pins { 335 334 pins = "gpio34"; 336 335 function = "normal"; 337 336 input-enable; ··· 339 338 power-source = <PM8058_GPIO_S3>; 340 339 }; 341 340 /* Pin 35 connected to ASET */ 342 - pinconf_gpio35 { 341 + gpio35-pins { 343 342 pins = "gpio35"; 344 343 function = "normal"; 345 344 output-high; ··· 347 346 power-source = <PM8058_GPIO_S3>; 348 347 }; 349 348 }; 350 - dragon_veth_gpios: veth-gpios { 349 + dragon_veth_gpios: veth-state { 351 350 pinconf { 352 351 pins = "gpio40"; 353 352 function = "normal"; ··· 417 416 compatible = "qcom,pm8058-led"; 418 417 reg = <0x131>; 419 418 label = "pm8058:red"; 419 + color = <LED_COLOR_ID_RED>; 420 420 default-state = "off"; 421 421 }; 422 422 led@132 { ··· 428 426 compatible = "qcom,pm8058-led"; 429 427 reg = <0x132>; 430 428 label = "pm8058:yellow"; 429 + color = <LED_COLOR_ID_YELLOW>; 431 430 default-state = "off"; 432 431 linux,default-trigger = "mmc0"; 433 432 }; ··· 436 433 compatible = "qcom,pm8058-led"; 437 434 reg = <0x133>; 438 435 label = "pm8058:green"; 436 + function = LED_FUNCTION_HEARTBEAT; 437 + color = <LED_COLOR_ID_GREEN>; 439 438 default-state = "on"; 440 439 linux,default-trigger = "heartbeat"; 441 440 };

+12 -12

arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts

··· 24 24 ramoops@88d00000{ 25 25 compatible = "ramoops"; 26 26 reg = <0x88d00000 0x100000>; 27 - record-size = <0x00020000>; 28 - console-size = <0x00020000>; 29 - ftrace-size = <0x00020000>; 27 + record-size = <0x00020000>; 28 + console-size = <0x00020000>; 29 + ftrace-size = <0x00020000>; 30 30 }; 31 31 }; 32 32 ··· 44 44 45 45 gpio-keys { 46 46 compatible = "gpio-keys"; 47 - volume_up { 47 + key-volume-up { 48 48 label = "Volume Up"; 49 49 gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; 50 50 linux,code = <KEY_VOLUMEUP>; 51 51 }; 52 - volume_down { 52 + key-volume-down { 53 53 label = "Volume Down"; 54 54 gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; 55 55 linux,code = <KEY_VOLUMEDOWN>; ··· 98 98 * tabla2x-slim-VDDIO_CDC 99 99 */ 100 100 s4 { 101 - regulator-min-microvolt = <1800000>; 102 - regulator-max-microvolt = <1800000>; 101 + regulator-min-microvolt = <1800000>; 102 + regulator-max-microvolt = <1800000>; 103 103 qcom,switch-mode-frequency = <3200000>; 104 104 regulator-always-on; 105 105 }; ··· 341 341 }; 342 342 }; 343 343 344 - imem@2a03f000 { 345 - compatible = "syscon", "simple-mfd"; 344 + sram@2a03f000 { 345 + compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; 346 346 reg = <0x2a03f000 0x1000>; 347 347 348 348 reboot-mode { 349 349 compatible = "syscon-reboot-mode"; 350 350 offset = <0x65c>; 351 351 352 - mode-normal = <0x77665501>; 353 - mode-bootloader = <0x77665500>; 354 - mode-recovery = <0x77665502>; 352 + mode-normal = <0x77665501>; 353 + mode-bootloader = <0x77665500>; 354 + mode-recovery = <0x77665502>; 355 355 }; 356 356 }; 357 357 };

+7 -7

arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts

··· 82 82 }; 83 83 84 84 s4 { 85 - regulator-min-microvolt = <1800000>; 86 - regulator-max-microvolt = <1800000>; 85 + regulator-min-microvolt = <1800000>; 86 + regulator-max-microvolt = <1800000>; 87 87 qcom,switch-mode-frequency = <3200000>; 88 88 }; 89 89 ··· 196 196 qcom,ssbi@500000 { 197 197 pmic@0 { 198 198 gpio@150 { 199 - wlan_default_gpios: wlan-gpios { 200 - pios { 199 + wlan_default_gpios: wlan-gpios-state { 200 + pinconf { 201 201 pins = "gpio43"; 202 202 function = "normal"; 203 203 bias-disable; ··· 230 230 sdcc3: mmc@12180000 { 231 231 status = "okay"; 232 232 vmmc-supply = <&v3p3_fixed>; 233 - pinctrl-names = "default"; 234 - pinctrl-0 = <&card_detect>; 235 - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; 233 + pinctrl-names = "default"; 234 + pinctrl-0 = <&card_detect>; 235 + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; 236 236 }; 237 237 /* WLAN */ 238 238 sdcc4: mmc@121c0000 {

+13 -12

arch/arm/boot/dts/qcom-apq8064-ifc6410.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include "qcom-apq8064-v2.0.dtsi" 3 3 #include <dt-bindings/gpio/gpio.h> 4 + #include <dt-bindings/leds/common.h> 4 5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 5 6 6 7 / { ··· 40 39 41 40 led@1 { 42 41 label = "apq8064:green:user1"; 42 + color = <LED_COLOR_ID_GREEN>; 43 43 gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; 44 44 default-state = "on"; 45 45 }; ··· 110 108 }; 111 109 112 110 s4 { 113 - regulator-min-microvolt = <1800000>; 114 - regulator-max-microvolt = <1800000>; 111 + regulator-min-microvolt = <1800000>; 112 + regulator-max-microvolt = <1800000>; 115 113 qcom,switch-mode-frequency = <3200000>; 116 114 }; 117 115 ··· 242 240 }; 243 241 244 242 sata0: sata@29000000 { 245 - status = "okay"; 246 - target-supply = <&pm8921_s4>; 243 + status = "okay"; 244 + target-supply = <&pm8921_s4>; 247 245 }; 248 246 249 247 /* OTG */ ··· 293 291 qcom,ssbi@500000 { 294 292 pmic@0 { 295 293 gpio@150 { 296 - wlan_default_gpios: wlan-gpios { 297 - pios { 294 + wlan_default_gpios: wlan-gpios-state { 295 + pinconf { 298 296 pins = "gpio43"; 299 297 function = "normal"; 300 298 bias-disable; ··· 302 300 }; 303 301 }; 304 302 305 - notify_led: nled { 306 - pios { 303 + notify_led: nled-state { 304 + pinconf { 307 305 pins = "gpio18"; 308 306 function = "normal"; 309 307 bias-disable; ··· 326 324 sdcc3: mmc@12180000 { 327 325 status = "okay"; 328 326 vmmc-supply = <&pm8921_l6>; 329 - pinctrl-names = "default"; 330 - pinctrl-0 = <&card_detect>; 331 - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; 327 + pinctrl-names = "default"; 328 + pinctrl-0 = <&card_detect>; 329 + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; 332 330 }; 333 331 /* WLAN */ 334 332 sdcc4: mmc@121c0000 { ··· 343 341 status = "okay"; 344 342 345 343 core-vdda-supply = <&pm8921_hdmi_switch>; 346 - hdmi-mux-supply = <&ext_3p3v>; 347 344 348 345 hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; 349 346

+5 -5

arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts

··· 23 23 pinctrl-names = "default"; 24 24 pinctrl-0 = <&gpio_keys_pin_a>; 25 25 26 - camera-focus { 26 + key-camera-focus { 27 27 label = "camera_focus"; 28 28 gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; 29 29 linux,input-type = <1>; 30 30 linux,code = <KEY_CAMERA_FOCUS>; 31 31 }; 32 32 33 - camera-snapshot { 33 + key-camera-snapshot { 34 34 label = "camera_snapshot"; 35 35 gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; 36 36 linux,input-type = <1>; 37 37 linux,code = <KEY_CAMERA>; 38 38 }; 39 39 40 - volume-down { 40 + key-volume-down { 41 41 label = "volume_down"; 42 42 gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; 43 43 linux,input-type = <1>; 44 44 linux,code = <KEY_VOLUMEDOWN>; 45 45 }; 46 46 47 - volume-up { 47 + key-volume-up { 48 48 label = "volume_up"; 49 49 gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; 50 50 linux,input-type = <1>; ··· 334 334 qcom,ssbi@500000 { 335 335 pmic@0 { 336 336 gpio@150 { 337 - gpio_keys_pin_a: gpio-keys-pin-active { 337 + gpio_keys_pin_a: gpio-keys-active-state { 338 338 pins = "gpio3", "gpio4", "gpio29", "gpio35"; 339 339 function = "normal"; 340 340

+79 -77

arch/arm/boot/dts/qcom-apq8064.dtsi

··· 315 315 316 316 firmware { 317 317 scm { 318 - compatible = "qcom,scm-apq8064"; 318 + compatible = "qcom,scm-apq8064", "qcom,scm"; 319 319 320 320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 321 321 clock-names = "core"; ··· 430 430 }; 431 431 432 432 sps_sic_non_secure: sps-sic-non-secure@12100000 { 433 - compatible = "syscon"; 434 - reg = <0x12100000 0x10000>; 433 + compatible = "syscon"; 434 + reg = <0x12100000 0x10000>; 435 435 }; 436 436 437 437 gsbi1: gsbi@12440000 { ··· 796 796 }; 797 797 798 798 qfprom: qfprom@700000 { 799 - compatible = "qcom,qfprom"; 800 - reg = <0x00700000 0x1000>; 801 - #address-cells = <1>; 802 - #size-cells = <1>; 799 + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 800 + reg = <0x00700000 0x1000>; 801 + #address-cells = <1>; 802 + #size-cells = <1>; 803 803 ranges; 804 - tsens_calib: calib { 804 + tsens_calib: calib@404 { 805 805 reg = <0x404 0x10>; 806 806 }; 807 - tsens_backup: backup_calib { 807 + tsens_backup: backup_calib@414 { 808 808 reg = <0x414 0x10>; 809 809 }; 810 810 }; ··· 836 836 }; 837 837 838 838 l2cc: clock-controller@2011000 { 839 - compatible = "qcom,kpss-gcc", "syscon"; 840 - reg = <0x2011000 0x1000>; 839 + compatible = "qcom,kpss-gcc", "syscon"; 840 + reg = <0x2011000 0x1000>; 841 841 }; 842 842 843 843 rpm@108000 { 844 - compatible = "qcom,rpm-apq8064"; 845 - reg = <0x108000 0x1000>; 846 - qcom,ipc = <&l2cc 0x8 2>; 844 + compatible = "qcom,rpm-apq8064"; 845 + reg = <0x108000 0x1000>; 846 + qcom,ipc = <&l2cc 0x8 2>; 847 847 848 - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 849 - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 850 - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 851 - interrupt-names = "ack", "err", "wakeup"; 848 + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 849 + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 850 + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 851 + interrupt-names = "ack", "err", "wakeup"; 852 852 853 853 rpmcc: clock-controller { 854 - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 854 + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 855 855 #clock-cells = <1>; 856 856 }; 857 857 ··· 1004 1004 }; 1005 1005 1006 1006 sata_phy0: phy@1b400000 { 1007 - compatible = "qcom,apq8064-sata-phy"; 1008 - status = "disabled"; 1009 - reg = <0x1b400000 0x200>; 1010 - reg-names = "phy_mem"; 1011 - clocks = <&gcc SATA_PHY_CFG_CLK>; 1012 - clock-names = "cfg"; 1013 - #phy-cells = <0>; 1007 + compatible = "qcom,apq8064-sata-phy"; 1008 + status = "disabled"; 1009 + reg = <0x1b400000 0x200>; 1010 + reg-names = "phy_mem"; 1011 + clocks = <&gcc SATA_PHY_CFG_CLK>; 1012 + clock-names = "cfg"; 1013 + #phy-cells = <0>; 1014 1014 }; 1015 1015 1016 1016 sata0: sata@29000000 { 1017 - compatible = "qcom,apq8064-ahci", "generic-ahci"; 1018 - status = "disabled"; 1019 - reg = <0x29000000 0x180>; 1020 - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1017 + compatible = "qcom,apq8064-ahci", "generic-ahci"; 1018 + status = "disabled"; 1019 + reg = <0x29000000 0x180>; 1020 + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1021 1021 1022 - clocks = <&gcc SFAB_SATA_S_H_CLK>, 1023 - <&gcc SATA_H_CLK>, 1024 - <&gcc SATA_A_CLK>, 1025 - <&gcc SATA_RXOOB_CLK>, 1026 - <&gcc SATA_PMALIVE_CLK>; 1027 - clock-names = "slave_iface", 1028 - "iface", 1029 - "bus", 1030 - "rxoob", 1031 - "core_pmalive"; 1022 + clocks = <&gcc SFAB_SATA_S_H_CLK>, 1023 + <&gcc SATA_H_CLK>, 1024 + <&gcc SATA_A_CLK>, 1025 + <&gcc SATA_RXOOB_CLK>, 1026 + <&gcc SATA_PMALIVE_CLK>; 1027 + clock-names = "slave_iface", 1028 + "iface", 1029 + "bus", 1030 + "rxoob", 1031 + "core_pmalive"; 1032 1032 1033 - assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1034 - <&gcc SATA_PMALIVE_CLK>; 1035 - assigned-clock-rates = <100000000>, <100000000>; 1033 + assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1034 + <&gcc SATA_PMALIVE_CLK>; 1035 + assigned-clock-rates = <100000000>, <100000000>; 1036 1036 1037 - phys = <&sata_phy0>; 1038 - phy-names = "sata-phy"; 1039 - ports-implemented = <0x1>; 1037 + phys = <&sata_phy0>; 1038 + phy-names = "sata-phy"; 1039 + ports-implemented = <0x1>; 1040 1040 }; 1041 1041 1042 1042 /* Temporary fixed regulator */ ··· 1076 1076 #size-cells = <1>; 1077 1077 ranges; 1078 1078 sdcc1: mmc@12400000 { 1079 - status = "disabled"; 1080 - compatible = "arm,pl18x", "arm,primecell"; 1081 - pinctrl-names = "default"; 1082 - pinctrl-0 = <&sdcc1_pins>; 1079 + status = "disabled"; 1080 + compatible = "arm,pl18x", "arm,primecell"; 1081 + pinctrl-names = "default"; 1082 + pinctrl-0 = <&sdcc1_pins>; 1083 1083 arm,primecell-periphid = <0x00051180>; 1084 - reg = <0x12400000 0x2000>; 1085 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1086 - interrupt-names = "cmd_irq"; 1087 - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1088 - clock-names = "mclk", "apb_pclk"; 1089 - bus-width = <8>; 1090 - max-frequency = <96000000>; 1084 + reg = <0x12400000 0x2000>; 1085 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1086 + interrupt-names = "cmd_irq"; 1087 + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1088 + clock-names = "mclk", "apb_pclk"; 1089 + bus-width = <8>; 1090 + max-frequency = <96000000>; 1091 1091 non-removable; 1092 1092 cap-sd-highspeed; 1093 1093 cap-mmc-highspeed; ··· 1096 1096 }; 1097 1097 1098 1098 sdcc3: mmc@12180000 { 1099 - compatible = "arm,pl18x", "arm,primecell"; 1099 + compatible = "arm,pl18x", "arm,primecell"; 1100 1100 arm,primecell-periphid = <0x00051180>; 1101 - status = "disabled"; 1102 - reg = <0x12180000 0x2000>; 1103 - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1104 - interrupt-names = "cmd_irq"; 1105 - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1106 - clock-names = "mclk", "apb_pclk"; 1107 - bus-width = <4>; 1101 + status = "disabled"; 1102 + reg = <0x12180000 0x2000>; 1103 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1104 + interrupt-names = "cmd_irq"; 1105 + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1106 + clock-names = "mclk", "apb_pclk"; 1107 + bus-width = <4>; 1108 1108 cap-sd-highspeed; 1109 1109 cap-mmc-highspeed; 1110 - max-frequency = <192000000>; 1110 + max-frequency = <192000000>; 1111 1111 no-1-8-v; 1112 1112 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1113 1113 dma-names = "tx", "rx"; 1114 1114 }; 1115 1115 1116 1116 sdcc4: mmc@121c0000 { 1117 - compatible = "arm,pl18x", "arm,primecell"; 1117 + compatible = "arm,pl18x", "arm,primecell"; 1118 1118 arm,primecell-periphid = <0x00051180>; 1119 - status = "disabled"; 1120 - reg = <0x121c0000 0x2000>; 1121 - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1122 - interrupt-names = "cmd_irq"; 1123 - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1124 - clock-names = "mclk", "apb_pclk"; 1125 - bus-width = <4>; 1119 + status = "disabled"; 1120 + reg = <0x121c0000 0x2000>; 1121 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1122 + interrupt-names = "cmd_irq"; 1123 + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1124 + clock-names = "mclk", "apb_pclk"; 1125 + bus-width = <4>; 1126 1126 cap-sd-highspeed; 1127 1127 cap-mmc-highspeed; 1128 - max-frequency = <48000000>; 1128 + max-frequency = <48000000>; 1129 1129 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1130 1130 dma-names = "tx", "rx"; 1131 1131 pinctrl-names = "default"; ··· 1271 1271 syscon-sfpb = <&mmss_sfpb>; 1272 1272 phys = <&dsi0_phy>; 1273 1273 phy-names = "dsi"; 1274 + status = "disabled"; 1275 + 1274 1276 ports { 1275 1277 #address-cells = <1>; 1276 1278 #size-cells = <0>; ··· 1301 1299 <0x04700300 0x200>, 1302 1300 <0x04700500 0x5c>; 1303 1301 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1304 - clock-names = "iface_clk", "ref"; 1302 + clock-names = "iface", "ref"; 1305 1303 clocks = <&mmcc DSI_M_AHB_CLK>, 1306 1304 <&pxo_board>; 1305 + status = "disabled"; 1307 1306 }; 1308 1307 1309 1308 ··· 1423 1420 "slave_iface"; 1424 1421 1425 1422 phys = <&hdmi_phy>; 1426 - phy-names = "hdmi-phy"; 1427 1423 1428 1424 ports { 1429 1425 #address-cells = <1>;

+5 -5

arch/arm/boot/dts/qcom-apq8084.dtsi

··· 95 95 96 96 firmware { 97 97 scm { 98 - compatible = "qcom,scm"; 98 + compatible = "qcom,scm-apq8084", "qcom,scm"; 99 99 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 100 100 clock-names = "core", "bus", "iface"; 101 101 }; ··· 240 240 }; 241 241 242 242 qfprom: qfprom@fc4bc000 { 243 + compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; 244 + reg = <0xfc4bc000 0x1000>; 243 245 #address-cells = <1>; 244 246 #size-cells = <1>; 245 - compatible = "qcom,qfprom"; 246 - reg = <0xfc4bc000 0x1000>; 247 247 tsens_calib: calib@d0 { 248 248 reg = <0xd0 0x18>; 249 249 }; ··· 419 419 status = "disabled"; 420 420 }; 421 421 422 - sdhci@f9824900 { 422 + mmc@f9824900 { 423 423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 424 424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 425 425 reg-names = "hc_mem", "core_mem"; ··· 432 432 status = "disabled"; 433 433 }; 434 434 435 - sdhci@f98a4900 { 435 + mmc@f98a4900 { 436 436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 437 437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 438 438 reg-names = "hc_mem", "core_mem";

+6

arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 2 3 + #include <dt-bindings/leds/common.h> 3 4 #include "qcom-ipq4018-ap120c-ac.dtsi" 4 5 5 6 / { ··· 11 10 12 11 power { 13 12 label = "ap120c-ac:green:power"; 13 + function = LED_FUNCTION_POWER; 14 + color = <LED_COLOR_ID_GREEN>; 14 15 gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; 15 16 default-state = "on"; 16 17 }; 17 18 18 19 wlan { 19 20 label = "ap120c-ac:green:wlan"; 21 + function = LED_FUNCTION_WLAN; 22 + color = <LED_COLOR_ID_GREEN>; 20 23 gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; 21 24 }; 22 25 23 26 support { 24 27 label = "ap120c-ac:green:support"; 28 + color = <LED_COLOR_ID_GREEN>; 25 29 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; 26 30 panic-indicator; 27 31 };

+7

arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 2 3 + #include <dt-bindings/leds/common.h> 3 4 #include "qcom-ipq4018-ap120c-ac.dtsi" 4 5 5 6 / { ··· 9 8 10 9 status: status { 11 10 label = "ap120c-ac:blue:status"; 11 + function = LED_FUNCTION_STATUS; 12 + color = <LED_COLOR_ID_BLUE>; 12 13 gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; 13 14 default-state = "keep"; 14 15 }; 15 16 16 17 wlan2g { 17 18 label = "ap120c-ac:green:wlan2g"; 19 + function = LED_FUNCTION_WLAN; 20 + color = <LED_COLOR_ID_GREEN>; 18 21 gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; 19 22 linux,default-trigger = "phy0tpt"; 20 23 }; 21 24 22 25 wlan5g { 23 26 label = "ap120c-ac:red:wlan5g"; 27 + function = LED_FUNCTION_WLAN; 28 + color = <LED_COLOR_ID_RED>; 24 29 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; 25 30 linux,default-trigger = "phy1tpt"; 26 31 };

+1 -1

arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi

··· 11 11 keys { 12 12 compatible = "gpio-keys"; 13 13 14 - reset { 14 + key-reset { 15 15 label = "reset"; 16 16 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; 17 17 linux,code = <KEY_RESTART>;

+1 -1

arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

··· 93 93 #address-cells = <1>; 94 94 #size-cells = <1>; 95 95 reg = <0>; 96 - compatible = "n25q128a11"; 96 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 97 97 spi-max-frequency = <24000000>; 98 98 }; 99 99 };

+1 -1

arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

··· 56 56 #address-cells = <1>; 57 57 #size-cells = <1>; 58 58 reg = <0>; 59 - compatible = "n25q128a11"; 59 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 60 60 spi-max-frequency = <24000000>; 61 61 }; 62 62 };

+2 -2

arch/arm/boot/dts/qcom-ipq4019.dtsi

··· 156 156 157 157 firmware { 158 158 scm { 159 - compatible = "qcom,scm-ipq4019"; 159 + compatible = "qcom,scm-ipq4019", "qcom,scm"; 160 160 }; 161 161 }; 162 162 ··· 221 221 status = "disabled"; 222 222 }; 223 223 224 - sdhci: sdhci@7824900 { 224 + sdhci: mmc@7824900 { 225 225 compatible = "qcom,sdhci-msm-v4"; 226 226 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 227 227 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

+4 -2

arch/arm/boot/dts/qcom-ipq8064-rb3011.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include "qcom-ipq8064.dtsi" 3 3 #include <dt-bindings/input/input.h> 4 + #include <dt-bindings/leds/common.h> 4 5 5 6 / { 6 7 model = "MikroTik RB3011UiAS-RM"; ··· 188 187 }; 189 188 }; 190 189 191 - gpio_keys { 190 + gpio-keys { 192 191 compatible = "gpio-keys"; 193 192 pinctrl-0 = <&buttons_pins>; 194 193 pinctrl-names = "default"; 195 194 196 - button@1 { 195 + button { 197 196 label = "reset"; 198 197 linux,code = <KEY_RESTART>; 199 198 gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; ··· 209 208 210 209 led@7 { 211 210 label = "rb3011:green:user"; 211 + color = <LED_COLOR_ID_GREEN>; 212 212 gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; 213 213 default-state = "off"; 214 214 };

+6 -3

arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include "qcom-ipq8064.dtsi" 3 3 #include <dt-bindings/input/input.h> 4 + #include <dt-bindings/leds/common.h> 4 5 5 6 / { 6 7 model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; ··· 66 65 status = "okay"; 67 66 }; 68 67 69 - gpio_keys { 68 + gpio-keys { 70 69 compatible = "gpio-keys"; 71 70 pinctrl-0 = <&buttons_pins>; 72 71 pinctrl-names = "default"; 73 72 74 - button@1 { 73 + button-1 { 75 74 label = "reset"; 76 75 linux,code = <KEY_RESTART>; 77 76 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; 78 77 linux,input-type = <1>; 79 78 debounce-interval = <60>; 80 79 }; 81 - button@2 { 80 + button-2 { 82 81 label = "wps"; 83 82 linux,code = <KEY_WPS_BUTTON>; 84 83 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; ··· 108 107 109 108 led@9 { 110 109 label = "status_led_fail"; 110 + function = LED_FUNCTION_STATUS; 111 111 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; 112 112 default-state = "off"; 113 113 }; ··· 121 119 122 120 led@53 { 123 121 label = "status_led_pass"; 122 + function = LED_FUNCTION_STATUS; 124 123 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; 125 124 default-state = "off"; 126 125 };

+18 -18

arch/arm/boot/dts/qcom-ipq8064.dtsi

··· 723 723 }; 724 724 725 725 qfprom: qfprom@700000 { 726 - compatible = "qcom,qfprom"; 726 + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 727 727 reg = <0x00700000 0x1000>; 728 728 #address-cells = <1>; 729 729 #size-cells = <1>; ··· 784 784 l2cc: clock-controller@2011000 { 785 785 compatible = "qcom,kpss-gcc", "syscon"; 786 786 reg = <0x2011000 0x1000>; 787 - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; 787 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 788 788 clock-names = "pll8_vote", "pxo"; 789 789 clock-output-names = "acpu_l2_aux"; 790 790 }; ··· 1184 1184 ranges; 1185 1185 1186 1186 sdcc1: mmc@12400000 { 1187 - status = "disabled"; 1188 - compatible = "arm,pl18x", "arm,primecell"; 1187 + status = "disabled"; 1188 + compatible = "arm,pl18x", "arm,primecell"; 1189 1189 arm,primecell-periphid = <0x00051180>; 1190 - reg = <0x12400000 0x2000>; 1191 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1190 + reg = <0x12400000 0x2000>; 1191 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1192 1192 interrupt-names = "cmd_irq"; 1193 - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1194 - clock-names = "mclk", "apb_pclk"; 1195 - bus-width = <8>; 1196 - max-frequency = <96000000>; 1193 + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1194 + clock-names = "mclk", "apb_pclk"; 1195 + bus-width = <8>; 1196 + max-frequency = <96000000>; 1197 1197 non-removable; 1198 1198 cap-sd-highspeed; 1199 1199 cap-mmc-highspeed; ··· 1204 1204 }; 1205 1205 1206 1206 sdcc3: mmc@12180000 { 1207 - compatible = "arm,pl18x", "arm,primecell"; 1207 + compatible = "arm,pl18x", "arm,primecell"; 1208 1208 arm,primecell-periphid = <0x00051180>; 1209 - status = "disabled"; 1210 - reg = <0x12180000 0x2000>; 1211 - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1209 + status = "disabled"; 1210 + reg = <0x12180000 0x2000>; 1211 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1212 1212 interrupt-names = "cmd_irq"; 1213 - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1214 - clock-names = "mclk", "apb_pclk"; 1215 - bus-width = <8>; 1213 + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1214 + clock-names = "mclk", "apb_pclk"; 1215 + bus-width = <8>; 1216 1216 cap-sd-highspeed; 1217 1217 cap-mmc-highspeed; 1218 - max-frequency = <192000000>; 1218 + max-frequency = <192000000>; 1219 1219 sd-uhs-sdr104; 1220 1220 sd-uhs-ddr50; 1221 1221 vqmmc-supply = <&vsdcc_fixed>;

+1 -1

arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi

··· 114 114 }; 115 115 116 116 &pmicgpio { 117 - usb_vbus_5v_pins: usb_vbus_5v_pins { 117 + usb_vbus_5v_pins: usb-vbus-5v-state { 118 118 pins = "gpio4"; 119 119 function = "normal"; 120 120 output-high;

+4 -3

arch/arm/boot/dts/qcom-mdm9615.dtsi

··· 321 321 322 322 pmicgpio: gpio@150 { 323 323 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; 324 + reg = <0x150>; 324 325 interrupt-controller; 325 326 #interrupt-cells = <2>; 326 327 gpio-controller; ··· 362 361 arm,primecell-periphid = <0x00051180>; 363 362 reg = <0x12180000 0x2000>; 364 363 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 365 - interrupt-names = "cmd_irq"; 364 + interrupt-names = "cmd_irq"; 366 365 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 367 366 clock-names = "mclk", "apb_pclk"; 368 367 bus-width = <8>; ··· 382 381 status = "disabled"; 383 382 reg = <0x12140000 0x2000>; 384 383 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 385 - interrupt-names = "cmd_irq"; 384 + interrupt-names = "cmd_irq"; 386 385 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 387 386 clock-names = "mclk", "apb_pclk"; 388 387 bus-width = <4>; ··· 412 411 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 413 412 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 414 413 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 415 - interrupt-names = "ack", "err", "wakeup"; 414 + interrupt-names = "ack", "err", "wakeup"; 416 415 417 416 regulators { 418 417 compatible = "qcom,rpm-pm8018-regulators";

+3 -3

arch/arm/boot/dts/qcom-msm8226.dtsi

··· 134 134 reg = <0xf9011000 0x1000>; 135 135 }; 136 136 137 - sdhc_1: sdhci@f9824900 { 137 + sdhc_1: mmc@f9824900 { 138 138 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 139 139 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 140 140 reg-names = "hc_mem", "core_mem"; ··· 150 150 status = "disabled"; 151 151 }; 152 152 153 - sdhc_2: sdhci@f98a4900 { 153 + sdhc_2: mmc@f98a4900 { 154 154 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 155 155 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 156 156 reg-names = "hc_mem", "core_mem"; ··· 166 166 status = "disabled"; 167 167 }; 168 168 169 - sdhc_3: sdhci@f9864900 { 169 + sdhc_3: mmc@f9864900 { 170 170 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 171 171 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 172 172 reg-names = "hc_mem", "core_mem";

+55 -55

arch/arm/boot/dts/qcom-msm8660.dtsi

··· 392 392 }; 393 393 394 394 l2cc: clock-controller@2082000 { 395 - compatible = "qcom,kpss-gcc", "syscon"; 396 - reg = <0x02082000 0x1000>; 395 + compatible = "qcom,kpss-gcc", "syscon"; 396 + reg = <0x02082000 0x1000>; 397 397 }; 398 398 399 399 rpm: rpm@104000 { 400 - compatible = "qcom,rpm-msm8660"; 401 - reg = <0x00104000 0x1000>; 402 - qcom,ipc = <&l2cc 0x8 2>; 400 + compatible = "qcom,rpm-msm8660"; 401 + reg = <0x00104000 0x1000>; 402 + qcom,ipc = <&l2cc 0x8 2>; 403 403 404 - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 405 - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 406 - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 407 - interrupt-names = "ack", "err", "wakeup"; 404 + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 405 + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 406 + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 407 + interrupt-names = "ack", "err", "wakeup"; 408 408 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 409 409 clock-names = "ram"; 410 410 411 411 rpmcc: clock-controller { 412 - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 412 + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 413 413 #clock-cells = <1>; 414 414 }; 415 415 ··· 486 486 #size-cells = <1>; 487 487 ranges; 488 488 sdcc1: mmc@12400000 { 489 - status = "disabled"; 490 - compatible = "arm,pl18x", "arm,primecell"; 489 + status = "disabled"; 490 + compatible = "arm,pl18x", "arm,primecell"; 491 491 arm,primecell-periphid = <0x00051180>; 492 - reg = <0x12400000 0x8000>; 493 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 494 - interrupt-names = "cmd_irq"; 495 - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 496 - clock-names = "mclk", "apb_pclk"; 497 - bus-width = <8>; 498 - max-frequency = <48000000>; 492 + reg = <0x12400000 0x8000>; 493 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 494 + interrupt-names = "cmd_irq"; 495 + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 496 + clock-names = "mclk", "apb_pclk"; 497 + bus-width = <8>; 498 + max-frequency = <48000000>; 499 499 non-removable; 500 500 cap-sd-highspeed; 501 501 cap-mmc-highspeed; 502 502 }; 503 503 504 504 sdcc2: mmc@12140000 { 505 - status = "disabled"; 506 - compatible = "arm,pl18x", "arm,primecell"; 505 + status = "disabled"; 506 + compatible = "arm,pl18x", "arm,primecell"; 507 507 arm,primecell-periphid = <0x00051180>; 508 - reg = <0x12140000 0x8000>; 509 - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 510 - interrupt-names = "cmd_irq"; 511 - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 512 - clock-names = "mclk", "apb_pclk"; 513 - bus-width = <8>; 514 - max-frequency = <48000000>; 508 + reg = <0x12140000 0x8000>; 509 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 510 + interrupt-names = "cmd_irq"; 511 + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 512 + clock-names = "mclk", "apb_pclk"; 513 + bus-width = <8>; 514 + max-frequency = <48000000>; 515 515 cap-sd-highspeed; 516 516 cap-mmc-highspeed; 517 517 }; 518 518 519 519 sdcc3: mmc@12180000 { 520 - compatible = "arm,pl18x", "arm,primecell"; 520 + compatible = "arm,pl18x", "arm,primecell"; 521 521 arm,primecell-periphid = <0x00051180>; 522 - status = "disabled"; 523 - reg = <0x12180000 0x8000>; 524 - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 525 - interrupt-names = "cmd_irq"; 526 - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 527 - clock-names = "mclk", "apb_pclk"; 528 - bus-width = <4>; 522 + status = "disabled"; 523 + reg = <0x12180000 0x8000>; 524 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 525 + interrupt-names = "cmd_irq"; 526 + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 527 + clock-names = "mclk", "apb_pclk"; 528 + bus-width = <4>; 529 529 cap-sd-highspeed; 530 530 cap-mmc-highspeed; 531 - max-frequency = <48000000>; 531 + max-frequency = <48000000>; 532 532 no-1-8-v; 533 533 }; 534 534 535 535 sdcc4: mmc@121c0000 { 536 - compatible = "arm,pl18x", "arm,primecell"; 536 + compatible = "arm,pl18x", "arm,primecell"; 537 537 arm,primecell-periphid = <0x00051180>; 538 - status = "disabled"; 539 - reg = <0x121c0000 0x8000>; 540 - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 541 - interrupt-names = "cmd_irq"; 542 - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 543 - clock-names = "mclk", "apb_pclk"; 544 - bus-width = <4>; 545 - max-frequency = <48000000>; 538 + status = "disabled"; 539 + reg = <0x121c0000 0x8000>; 540 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 541 + interrupt-names = "cmd_irq"; 542 + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 543 + clock-names = "mclk", "apb_pclk"; 544 + bus-width = <4>; 545 + max-frequency = <48000000>; 546 546 cap-sd-highspeed; 547 547 cap-mmc-highspeed; 548 548 }; 549 549 550 550 sdcc5: mmc@12200000 { 551 - compatible = "arm,pl18x", "arm,primecell"; 551 + compatible = "arm,pl18x", "arm,primecell"; 552 552 arm,primecell-periphid = <0x00051180>; 553 - status = "disabled"; 554 - reg = <0x12200000 0x8000>; 555 - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 556 - interrupt-names = "cmd_irq"; 557 - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 558 - clock-names = "mclk", "apb_pclk"; 559 - bus-width = <4>; 553 + status = "disabled"; 554 + reg = <0x12200000 0x8000>; 555 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 556 + interrupt-names = "cmd_irq"; 557 + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 558 + clock-names = "mclk", "apb_pclk"; 559 + bus-width = <4>; 560 560 cap-sd-highspeed; 561 561 cap-mmc-highspeed; 562 - max-frequency = <48000000>; 562 + max-frequency = <48000000>; 563 563 }; 564 564 }; 565 565

+27 -27

arch/arm/boot/dts/qcom-msm8960.dtsi

··· 148 148 }; 149 149 150 150 l2cc: clock-controller@2011000 { 151 - compatible = "qcom,kpss-gcc", "syscon"; 152 - reg = <0x2011000 0x1000>; 151 + compatible = "qcom,kpss-gcc", "syscon"; 152 + reg = <0x2011000 0x1000>; 153 153 }; 154 154 155 155 rpm@108000 { 156 - compatible = "qcom,rpm-msm8960"; 157 - reg = <0x108000 0x1000>; 158 - qcom,ipc = <&l2cc 0x8 2>; 156 + compatible = "qcom,rpm-msm8960"; 157 + reg = <0x108000 0x1000>; 158 + qcom,ipc = <&l2cc 0x8 2>; 159 159 160 - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 161 - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 162 - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 163 - interrupt-names = "ack", "err", "wakeup"; 160 + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 161 + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 162 + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 163 + interrupt-names = "ack", "err", "wakeup"; 164 164 165 165 regulators { 166 166 compatible = "qcom,rpm-pm8921-regulators"; ··· 268 268 #size-cells = <1>; 269 269 ranges; 270 270 sdcc1: mmc@12400000 { 271 - status = "disabled"; 272 - compatible = "arm,pl18x", "arm,primecell"; 271 + status = "disabled"; 272 + compatible = "arm,pl18x", "arm,primecell"; 273 273 arm,primecell-periphid = <0x00051180>; 274 - reg = <0x12400000 0x8000>; 275 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 276 - interrupt-names = "cmd_irq"; 277 - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 278 - clock-names = "mclk", "apb_pclk"; 279 - bus-width = <8>; 280 - max-frequency = <96000000>; 274 + reg = <0x12400000 0x8000>; 275 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 276 + interrupt-names = "cmd_irq"; 277 + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 278 + clock-names = "mclk", "apb_pclk"; 279 + bus-width = <8>; 280 + max-frequency = <96000000>; 281 281 non-removable; 282 282 cap-sd-highspeed; 283 283 cap-mmc-highspeed; ··· 285 285 }; 286 286 287 287 sdcc3: mmc@12180000 { 288 - compatible = "arm,pl18x", "arm,primecell"; 288 + compatible = "arm,pl18x", "arm,primecell"; 289 289 arm,primecell-periphid = <0x00051180>; 290 - status = "disabled"; 291 - reg = <0x12180000 0x8000>; 292 - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 293 - interrupt-names = "cmd_irq"; 294 - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 295 - clock-names = "mclk", "apb_pclk"; 296 - bus-width = <4>; 290 + status = "disabled"; 291 + reg = <0x12180000 0x8000>; 292 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 293 + interrupt-names = "cmd_irq"; 294 + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 295 + clock-names = "mclk", "apb_pclk"; 296 + bus-width = <4>; 297 297 cap-sd-highspeed; 298 298 cap-mmc-highspeed; 299 - max-frequency = <192000000>; 299 + max-frequency = <192000000>; 300 300 no-1-8-v; 301 301 vmmc-supply = <&vsdcc_fixed>; 302 302 };

+6 -6

arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts

··· 24 24 pinctrl-names = "default"; 25 25 pinctrl-0 = <&gpio_keys_pin_a>; 26 26 27 - volume-up { 27 + key-volume-up { 28 28 label = "volume_up"; 29 29 gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; 30 30 linux,input-type = <1>; 31 31 linux,code = <KEY_VOLUMEUP>; 32 32 }; 33 33 34 - volume-down { 34 + key-volume-down { 35 35 label = "volume_down"; 36 36 gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; 37 37 linux,input-type = <1>; ··· 272 272 }; 273 273 274 274 &pm8941_gpios { 275 - gpio_keys_pin_a: gpio-keys-active { 275 + gpio_keys_pin_a: gpio-keys-active-state { 276 276 pins = "gpio2", "gpio3"; 277 277 function = "normal"; 278 278 ··· 280 280 power-source = <PM8941_GPIO_S3>; 281 281 }; 282 282 283 - fuelgauge_pin: fuelgauge-int { 283 + fuelgauge_pin: fuelgauge-int-state { 284 284 pins = "gpio9"; 285 285 function = "normal"; 286 286 ··· 289 289 power-source = <PM8941_GPIO_S3>; 290 290 }; 291 291 292 - wlan_sleep_clk_pin: wl-sleep-clk { 292 + wlan_sleep_clk_pin: wl-sleep-clk-state { 293 293 pins = "gpio16"; 294 294 function = "func2"; 295 295 ··· 297 297 power-source = <PM8941_GPIO_S3>; 298 298 }; 299 299 300 - wlan_regulator_pin: wl-reg-active { 300 + wlan_regulator_pin: wl-reg-active-state { 301 301 pins = "gpio17"; 302 302 function = "normal"; 303 303

+5 -5

arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi

··· 20 20 pinctrl-names = "default"; 21 21 pinctrl-0 = <&gpio_keys_pin_a>; 22 22 23 - volume-down { 23 + key-volume-down { 24 24 label = "volume_down"; 25 25 gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; 26 26 linux,input-type = <1>; 27 27 linux,code = <KEY_VOLUMEDOWN>; 28 28 }; 29 29 30 - camera-snapshot { 30 + key-camera-snapshot { 31 31 label = "camera_snapshot"; 32 32 gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; 33 33 linux,input-type = <1>; 34 34 linux,code = <KEY_CAMERA>; 35 35 }; 36 36 37 - camera-focus { 37 + key-camera-focus { 38 38 label = "camera_focus"; 39 39 gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; 40 40 linux,input-type = <1>; 41 41 linux,code = <KEY_CAMERA_FOCUS>; 42 42 }; 43 43 44 - volume-up { 44 + key-volume-up { 45 45 label = "volume_up"; 46 46 gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; 47 47 linux,input-type = <1>; ··· 163 163 }; 164 164 165 165 &pm8941_gpios { 166 - gpio_keys_pin_a: gpio-keys-active { 166 + gpio_keys_pin_a: gpio-keys-active-state { 167 167 pins = "gpio2", "gpio3", "gpio4", "gpio5"; 168 168 function = "normal"; 169 169

+38 -11

arch/arm/boot/dts/qcom-msm8974.dtsi

··· 96 96 97 97 firmware { 98 98 scm { 99 - compatible = "qcom,scm"; 99 + compatible = "qcom,scm-msm8974", "qcom,scm"; 100 100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101 101 clock-names = "core", "bus", "iface"; 102 102 }; ··· 436 436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 437 437 }; 438 438 439 - sdhc_1: sdhci@f9824900 { 439 + sdhc_1: mmc@f9824900 { 440 440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 441 441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 442 442 reg-names = "hc_mem", "core_mem"; ··· 453 453 status = "disabled"; 454 454 }; 455 455 456 - sdhc_3: sdhci@f9864900 { 456 + sdhc_3: mmc@f9864900 { 457 457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 458 458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 459 459 reg-names = "hc_mem", "core_mem"; ··· 472 472 status = "disabled"; 473 473 }; 474 474 475 - sdhc_2: sdhci@f98a4900 { 475 + sdhc_2: mmc@f98a4900 { 476 476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 477 477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 478 478 reg-names = "hc_mem", "core_mem"; ··· 578 578 blsp2_uart1: serial@f995d000 { 579 579 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 580 580 reg = <0xf995d000 0x1000>; 581 - interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>; 581 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 582 582 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 583 583 clock-names = "core", "iface"; 584 584 status = "disabled"; ··· 1118 1118 }; 1119 1119 1120 1120 qfprom: qfprom@fc4bc000 { 1121 + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1122 + reg = <0xfc4bc000 0x1000>; 1121 1123 #address-cells = <1>; 1122 1124 #size-cells = <1>; 1123 - compatible = "qcom,qfprom"; 1124 - reg = <0xfc4bc000 0x1000>; 1125 1125 tsens_calib: calib@d0 { 1126 1126 reg = <0xd0 0x18>; 1127 1127 }; ··· 1144 1144 #size-cells = <0>; 1145 1145 interrupt-controller; 1146 1146 #interrupt-cells = <4>; 1147 + }; 1148 + 1149 + bam_dmux_dma: dma-controller@fc834000 { 1150 + compatible = "qcom,bam-v1.4.0"; 1151 + reg = <0xfc834000 0x7000>; 1152 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1153 + #dma-cells = <1>; 1154 + qcom,ee = <0>; 1155 + 1156 + num-channels = <6>; 1157 + qcom,num-ees = <1>; 1158 + qcom,powered-remotely; 1147 1159 }; 1148 1160 1149 1161 remoteproc_mss: remoteproc@fc880000 { ··· 1190 1178 1191 1179 mpss { 1192 1180 memory-region = <&mpss_region>; 1181 + }; 1182 + 1183 + bam_dmux: bam-dmux { 1184 + compatible = "qcom,bam-dmux"; 1185 + 1186 + interrupt-parent = <&modem_smsm>; 1187 + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1188 + interrupt-names = "pc", "pc-ack"; 1189 + 1190 + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1191 + qcom,smem-state-names = "pc", "pc-ack"; 1192 + 1193 + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1194 + dma-names = "tx", "rx"; 1193 1195 }; 1194 1196 1195 1197 smd-edge { ··· 1612 1586 1613 1587 status = "disabled"; 1614 1588 1615 - gpu_opp_table: opp_table { 1589 + gpu_opp_table: opp-table { 1616 1590 compatible = "operating-points-v2"; 1617 1591 1618 1592 opp-320000000 { ··· 1629 1603 }; 1630 1604 }; 1631 1605 1632 - ocmem@fdd00000 { 1606 + sram@fdd00000 { 1633 1607 compatible = "qcom,msm8974-ocmem"; 1634 1608 reg = <0xfdd00000 0x2000>, 1635 1609 <0xfec00000 0x180000>; 1636 1610 reg-names = "ctrl", "mem"; 1611 + ranges = <0 0xfec00000 0x180000>; 1637 1612 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1638 1613 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1639 1614 clock-names = "core", "iface"; ··· 1677 1650 }; 1678 1651 }; 1679 1652 1680 - imem: imem@fe805000 { 1681 - compatible = "syscon", "simple-mfd"; 1653 + imem: sram@fe805000 { 1654 + compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 1682 1655 reg = <0xfe805000 0x1000>; 1683 1656 1684 1657 reboot-mode {

+7 -7

arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts

··· 25 25 pinctrl-names = "default"; 26 26 pinctrl-0 = <&gpio_keys_pin_a>; 27 27 28 - camera-snapshot { 28 + key-camera-snapshot { 29 29 label = "camera_snapshot"; 30 30 gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; 31 31 linux,code = <KEY_CAMERA>; ··· 33 33 debounce-interval = <15>; 34 34 }; 35 35 36 - volume-down { 36 + key-volume-down { 37 37 label = "volume_down"; 38 38 gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; 39 39 linux,code = <KEY_VOLUMEDOWN>; ··· 41 41 debounce-interval = <15>; 42 42 }; 43 43 44 - volume-up { 44 + key-volume-up { 45 45 label = "volume_up"; 46 46 gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; 47 47 linux,code = <KEY_VOLUMEUP>; ··· 78 78 79 79 &imem { 80 80 reboot-mode { 81 - mode-normal = <0x77665501>; 82 - mode-bootloader = <0x77665500>; 83 - mode-recovery = <0x77665502>; 81 + mode-normal = <0x77665501>; 82 + mode-bootloader = <0x77665500>; 83 + mode-recovery = <0x77665502>; 84 84 }; 85 85 }; 86 86 ··· 110 110 }; 111 111 112 112 &pm8941_gpios { 113 - gpio_keys_pin_a: gpio-keys-active { 113 + gpio_keys_pin_a: gpio-keys-active-state { 114 114 pins = "gpio1", "gpio2", "gpio5"; 115 115 function = "normal"; 116 116

+10 -10

arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts

··· 25 25 pinctrl-names = "default"; 26 26 pinctrl-0 = <&gpio_keys_pin_a>; 27 27 28 - volume-down { 28 + key-volume-down { 29 29 label = "volume_down"; 30 30 gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; 31 31 linux,input-type = <1>; ··· 33 33 debounce-interval = <15>; 34 34 }; 35 35 36 - home-key { 36 + key-home { 37 37 label = "home_key"; 38 38 gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; 39 39 linux,input-type = <1>; ··· 42 42 debounce-interval = <15>; 43 43 }; 44 44 45 - volume-up { 45 + key-volume-up { 46 46 label = "volume_up"; 47 47 gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; 48 48 linux,input-type = <1>; ··· 398 398 }; 399 399 400 400 &pma8084_gpios { 401 - gpio_keys_pin_a: gpio-keys-active { 401 + gpio_keys_pin_a: gpio-keys-active-state { 402 402 pins = "gpio2", "gpio3", "gpio5"; 403 403 function = "normal"; 404 404 ··· 406 406 power-source = <PMA8084_GPIO_S4>; 407 407 }; 408 408 409 - touchkey_pin: touchkey-int-pin { 409 + touchkey_pin: touchkey-int-state { 410 410 pins = "gpio6"; 411 411 function = "normal"; 412 412 bias-disable; ··· 414 414 power-source = <PMA8084_GPIO_S4>; 415 415 }; 416 416 417 - touch_pin: touchscreen-int-pin { 417 + touch_pin: touchscreen-int-state { 418 418 pins = "gpio8"; 419 419 function = "normal"; 420 420 bias-disable; ··· 422 422 power-source = <PMA8084_GPIO_S4>; 423 423 }; 424 424 425 - panel_en_pin: panel-en-pin { 425 + panel_en_pin: panel-en-state { 426 426 pins = "gpio14"; 427 427 function = "normal"; 428 428 bias-pull-up; ··· 430 430 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 431 431 }; 432 432 433 - wlan_sleep_clk_pin: wlan-sleep-clk-pin { 433 + wlan_sleep_clk_pin: wlan-sleep-clk-state { 434 434 pins = "gpio16"; 435 435 function = "func2"; 436 436 ··· 439 439 qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; 440 440 }; 441 441 442 - panel_rst_pin: panel-rst-pin { 442 + panel_rst_pin: panel-rst-state { 443 443 pins = "gpio17"; 444 444 function = "normal"; 445 445 bias-disable; ··· 447 447 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 448 448 }; 449 449 450 - fuelgauge_pin: fuelgauge-int-pin { 450 + fuelgauge_pin: fuelgauge-int-state { 451 451 pins = "gpio21"; 452 452 function = "normal"; 453 453 bias-disable;

+9 -9

arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts

··· 24 24 pinctrl-names = "default"; 25 25 pinctrl-0 = <&gpio_keys_pin_a>; 26 26 27 - volume-down { 27 + key-volume-down { 28 28 label = "volume_down"; 29 29 gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; 30 30 linux,input-type = <1>; 31 31 linux,code = <KEY_VOLUMEDOWN>; 32 32 }; 33 33 34 - camera-snapshot { 34 + key-camera-snapshot { 35 35 label = "camera_snapshot"; 36 36 gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; 37 37 linux,input-type = <1>; 38 38 linux,code = <KEY_CAMERA>; 39 39 }; 40 40 41 - camera-focus { 41 + key-camera-focus { 42 42 label = "camera_focus"; 43 43 gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; 44 44 linux,input-type = <1>; 45 45 linux,code = <KEY_CAMERA_FOCUS>; 46 46 }; 47 47 48 - volume-up { 48 + key-volume-up { 49 49 label = "volume_up"; 50 50 gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; 51 51 linux,input-type = <1>; ··· 244 244 }; 245 245 246 246 &pm8941_gpios { 247 - gpio_keys_pin_a: gpio-keys-active { 247 + gpio_keys_pin_a: gpio-keys-active-state { 248 248 pins = "gpio2", "gpio5"; 249 249 function = "normal"; 250 250 ··· 252 252 power-source = <PM8941_GPIO_S3>; 253 253 }; 254 254 255 - bt_reg_on_pin: bt-reg-on { 255 + bt_reg_on_pin: bt-reg-on-state { 256 256 pins = "gpio16"; 257 257 function = "normal"; 258 258 ··· 260 260 power-source = <PM8941_GPIO_S3>; 261 261 }; 262 262 263 - wlan_sleep_clk_pin: wl-sleep-clk { 263 + wlan_sleep_clk_pin: wl-sleep-clk-state { 264 264 pins = "gpio17"; 265 265 function = "func2"; 266 266 ··· 268 268 power-source = <PM8941_GPIO_S3>; 269 269 }; 270 270 271 - wlan_regulator_pin: wl-reg-active { 271 + wlan_regulator_pin: wl-reg-active-state { 272 272 pins = "gpio18"; 273 273 function = "normal"; 274 274 ··· 276 276 power-source = <PM8941_GPIO_S3>; 277 277 }; 278 278 279 - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { 279 + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { 280 280 pins = "gpio20"; 281 281 function = "normal"; 282 282

+1

arch/arm/boot/dts/qcom-pm8841.dtsi

··· 24 24 compatible = "qcom,spmi-temp-alarm"; 25 25 reg = <0x2400>; 26 26 interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; 27 + #thermal-sensor-cells = <0>; 27 28 }; 28 29 }; 29 30

+1 -1

arch/arm/boot/dts/qcom-pm8941.dtsi

··· 68 68 interrupt-controller; 69 69 #interrupt-cells = <2>; 70 70 71 - boost_bypass_n_pin: boost-bypass { 71 + boost_bypass_n_pin: boost-bypass-state { 72 72 pins = "gpio21"; 73 73 function = "normal"; 74 74 };

+1

arch/arm/boot/dts/qcom-pmx55.dtsi

··· 69 69 compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; 70 70 reg = <0xc000>; 71 71 gpio-controller; 72 + gpio-ranges = <&pmx55_gpios 0 0 11>; 72 73 #gpio-cells = <2>; 73 74 interrupt-controller; 74 75 #interrupt-cells = <2>;

+2 -1

arch/arm/boot/dts/qcom-pmx65.dtsi

··· 21 21 }; 22 22 23 23 pmx65_gpios: pinctrl@8800 { 24 - compatible = "qcom,pmx65-gpio"; 24 + compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; 25 25 reg = <0x8800>; 26 26 gpio-controller; 27 + gpio-ranges = <&pmx65_gpios 0 0 16>; 27 28 #gpio-cells = <2>; 28 29 interrupt-controller; 29 30 #interrupt-cells = <2>;

+4 -4

arch/arm/boot/dts/qcom-sdx55.dtsi

··· 206 206 blsp1_uart3: serial@831000 { 207 207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 208 208 reg = <0x00831000 0x200>; 209 - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>; 209 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 210 210 clocks = <&gcc 30>, 211 211 <&gcc 9>; 212 212 clock-names = "core", "iface"; ··· 388 388 reg = <0x01fc0000 0x1000>; 389 389 }; 390 390 391 - sdhc_1: sdhci@8804000 { 391 + sdhc_1: mmc@8804000 { 392 392 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; 393 393 reg = <0x08804000 0x1000>; 394 394 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, ··· 561 561 #interrupt-cells = <2>; 562 562 }; 563 563 564 - imem@1468f000 { 565 - compatible = "simple-mfd"; 564 + sram@1468f000 { 565 + compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; 566 566 reg = <0x1468f000 0x1000>; 567 567 568 568 #address-cells = <1>;

+53 -8

arch/arm/boot/dts/qcom-sdx65-mtp.dts

··· 64 64 }; 65 65 }; 66 66 67 - &blsp1_uart3 { 68 - status = "ok"; 69 - }; 70 - 71 67 &apps_rsc { 72 68 pmx65-rpmh-regulators { 73 69 compatible = "qcom,pmx65-rpmh-regulators"; ··· 119 123 regulator-max-microvolt = <1300000>; 120 124 }; 121 125 122 - ldo1 { 126 + vreg_l1b_1p2: ldo1 { 123 127 regulator-min-microvolt = <1200000>; 124 128 regulator-max-microvolt = <1200000>; 125 129 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ··· 137 141 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 138 142 }; 139 143 140 - ldo4 { 144 + vreg_l4b_0p88: ldo4 { 141 145 regulator-min-microvolt = <880000>; 142 146 regulator-max-microvolt = <912000>; 143 147 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 144 148 }; 145 149 146 - ldo5 { 150 + vreg_l5b_1p8: ldo5 { 147 151 regulator-min-microvolt = <1800000>; 148 152 regulator-max-microvolt = <1800000>; 149 153 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ··· 173 177 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 174 178 }; 175 179 176 - ldo10 { 180 + vreg_l10b_3p08: ldo10 { 177 181 regulator-min-microvolt = <3088000>; 178 182 regulator-max-microvolt = <3088000>; 179 183 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ··· 239 243 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 240 244 }; 241 245 }; 246 + }; 247 + 248 + &blsp1_uart3 { 249 + status = "okay"; 250 + }; 251 + 252 + &qpic_bam { 253 + status = "okay"; 254 + }; 255 + 256 + &qpic_nand { 257 + status = "okay"; 258 + 259 + nand@0 { 260 + reg = <0>; 261 + 262 + nand-ecc-strength = <4>; 263 + nand-ecc-step-size = <512>; 264 + nand-bus-width = <8>; 265 + /* ico and efs2 partitions are secured */ 266 + secure-regions = /bits/ 64 <0x500000 0x500000 267 + 0xa00000 0xb00000>; 268 + }; 269 + }; 270 + 271 + &remoteproc_mpss { 272 + status = "okay"; 273 + memory-region = <&mpss_adsp_mem>; 274 + }; 275 + 276 + &usb { 277 + status = "okay"; 278 + }; 279 + 280 + &usb_dwc3 { 281 + dr_mode = "peripheral"; 282 + }; 283 + 284 + &usb_hsphy { 285 + status = "okay"; 286 + vdda-pll-supply = <&vreg_l4b_0p88>; 287 + vdda33-supply = <&vreg_l10b_3p08>; 288 + vdda18-supply = <&vreg_l5b_1p8>; 289 + }; 290 + 291 + &usb_qmpphy { 292 + status = "okay"; 293 + vdda-phy-supply = <&vreg_l4b_0p88>; 294 + vdda-pll-supply = <&vreg_l1b_1p2>; 242 295 };

+269 -2

arch/arm/boot/dts/qcom-sdx65.dtsi

··· 37 37 clock-output-names = "sleep_clk"; 38 38 #clock-cells = <0>; 39 39 }; 40 + 41 + nand_clk_dummy: nand-clk-dummy { 42 + compatible = "fixed-clock"; 43 + clock-frequency = <32764>; 44 + #clock-cells = <0>; 45 + }; 40 46 }; 41 47 42 48 cpus { ··· 54 48 compatible = "arm,cortex-a7"; 55 49 reg = <0x0>; 56 50 enable-method = "psci"; 51 + clocks = <&apcs>; 52 + power-domains = <&rpmhpd SDX65_CX_AO>; 53 + power-domain-names = "rpmhpd"; 54 + operating-points-v2 = <&cpu_opp_table>; 57 55 }; 56 + }; 57 + 58 + cpu_opp_table: cpu-opp-table { 59 + compatible = "operating-points-v2"; 60 + opp-shared; 61 + 62 + opp-345600000 { 63 + opp-hz = /bits/ 64 <345600000>; 64 + required-opps = <&rpmhpd_opp_low_svs>; 65 + }; 66 + 67 + opp-576000000 { 68 + opp-hz = /bits/ 64 <576000000>; 69 + required-opps = <&rpmhpd_opp_svs>; 70 + }; 71 + 72 + opp-1094400000 { 73 + opp-hz = /bits/ 64 <1094400000>; 74 + required-opps = <&rpmhpd_opp_nom>; 75 + }; 76 + 77 + opp-1497600000 { 78 + opp-hz = /bits/ 64 <1497600000>; 79 + required-opps = <&rpmhpd_opp_turbo>; 80 + }; 81 + }; 82 + 83 + firmware { 84 + scm { 85 + compatible = "qcom,scm-sdx65", "qcom,scm"; 86 + }; 87 + }; 88 + 89 + mc_virt: interconnect-mc-virt { 90 + compatible = "qcom,sdx65-mc-virt"; 91 + #interconnect-cells = <1>; 92 + qcom,bcm-voters = <&apps_bcm_voter>; 58 93 }; 59 94 60 95 psci { ··· 134 87 }; 135 88 136 89 smem_mem: memory@8fe20000 { 137 - no-map; 90 + compatible = "qcom,smem"; 138 91 reg = <0x8fe20000 0xc0000>; 92 + hwlocks = <&tcsr_mutex 3>; 93 + no-map; 139 94 }; 140 95 141 96 cmd_db: reserved-memory@8fee0000 { ··· 162 113 }; 163 114 }; 164 115 116 + smp2p-mpss { 117 + compatible = "qcom,smp2p"; 118 + qcom,smem = <435>, <428>; 119 + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 120 + mboxes = <&apcs 14>; 121 + qcom,local-pid = <0>; 122 + qcom,remote-pid = <1>; 123 + 124 + modem_smp2p_out: master-kernel { 125 + qcom,entry-name = "master-kernel"; 126 + #qcom,smem-state-cells = <1>; 127 + }; 128 + 129 + modem_smp2p_in: slave-kernel { 130 + qcom,entry-name = "slave-kernel"; 131 + interrupt-controller; 132 + #interrupt-cells = <2>; 133 + }; 134 + 135 + ipa_smp2p_out: ipa-ap-to-modem { 136 + qcom,entry-name = "ipa"; 137 + #qcom,smem-state-cells = <1>; 138 + }; 139 + 140 + ipa_smp2p_in: ipa-modem-to-ap { 141 + qcom,entry-name = "ipa"; 142 + interrupt-controller; 143 + #interrupt-cells = <2>; 144 + }; 145 + }; 146 + 165 147 soc: soc { 166 148 #address-cells = <1>; 167 149 #size-cells = <1>; ··· 204 124 reg = <0x00100000 0x001f7400>; 205 125 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 206 126 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 127 + #power-domain-cells = <1>; 207 128 #clock-cells = <1>; 208 129 #reset-cells = <1>; 209 130 }; ··· 218 137 status = "disabled"; 219 138 }; 220 139 140 + usb_hsphy: phy@ff4000 { 141 + compatible = "qcom,usb-snps-hs-7nm-phy"; 142 + reg = <0xff4000 0x120>; 143 + #phy-cells = <0>; 144 + status = "disabled"; 145 + clocks = <&rpmhcc RPMH_CXO_CLK>; 146 + clock-names = "ref"; 147 + resets = <&gcc GCC_QUSB2PHY_BCR>; 148 + }; 149 + 150 + usb_qmpphy: phy@ff6000 { 151 + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; 152 + reg = <0x00ff6000 0x1c8>; 153 + status = "disabled"; 154 + #address-cells = <1>; 155 + #size-cells = <1>; 156 + ranges; 157 + 158 + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 159 + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 160 + <&gcc GCC_USB3_PRIM_CLKREF_EN>; 161 + clock-names = "aux", "cfg_ahb", "ref"; 162 + 163 + resets = <&gcc GCC_USB3PHY_PHY_BCR>, 164 + <&gcc GCC_USB3_PHY_BCR>; 165 + reset-names = "phy", "common"; 166 + 167 + usb_ssphy: phy@ff6200 { 168 + reg = <0x00ff6e00 0x160>, 169 + <0x00ff7000 0x1ec>, 170 + <0x00ff6200 0x1e00>; 171 + #phy-cells = <0>; 172 + #clock-cells = <0>; 173 + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 174 + clock-names = "pipe0"; 175 + clock-output-names = "usb3_uni_phy_pipe_clk_src"; 176 + }; 177 + }; 178 + 179 + system_noc: interconnect@1620000 { 180 + compatible = "qcom,sdx65-system-noc"; 181 + reg = <0x01620000 0x31200>; 182 + #interconnect-cells = <1>; 183 + qcom,bcm-voters = <&apps_bcm_voter>; 184 + }; 185 + 186 + qpic_bam: dma-controller@1b04000 { 187 + compatible = "qcom,bam-v1.7.0"; 188 + reg = <0x01b04000 0x1c000>; 189 + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 190 + clocks = <&rpmhcc RPMH_QPIC_CLK>; 191 + clock-names = "bam_clk"; 192 + #dma-cells = <1>; 193 + qcom,ee = <0>; 194 + qcom,controlled-remotely; 195 + status = "disabled"; 196 + }; 197 + 198 + qpic_nand: nand-controller@1b30000 { 199 + compatible = "qcom,sdx55-nand"; 200 + reg = <0x01b30000 0x10000>; 201 + #address-cells = <1>; 202 + #size-cells = <0>; 203 + clocks = <&rpmhcc RPMH_QPIC_CLK>, 204 + <&nand_clk_dummy>; 205 + clock-names = "core", "aon"; 206 + 207 + dmas = <&qpic_bam 0>, 208 + <&qpic_bam 1>, 209 + <&qpic_bam 2>; 210 + dma-names = "tx", "rx", "cmd"; 211 + status = "disabled"; 212 + }; 213 + 221 214 tcsr_mutex: hwlock@1f40000 { 222 215 compatible = "qcom,tcsr-mutex"; 223 216 reg = <0x01f40000 0x40000>; 224 217 #hwlock-cells = <1>; 225 218 }; 226 219 227 - sdhc_1: sdhci@8804000 { 220 + remoteproc_mpss: remoteproc@4080000 { 221 + compatible = "qcom,sdx55-mpss-pas"; 222 + reg = <0x04080000 0x4040>; 223 + 224 + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 225 + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 226 + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 227 + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 228 + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 229 + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 230 + interrupt-names = "wdog", "fatal", "ready", "handover", 231 + "stop-ack", "shutdown-ack"; 232 + 233 + clocks = <&rpmhcc RPMH_CXO_CLK>; 234 + clock-names = "xo"; 235 + 236 + power-domains = <&rpmhpd SDX65_CX>, 237 + <&rpmhpd SDX65_MSS>; 238 + power-domain-names = "cx", "mss"; 239 + 240 + qcom,smem-states = <&modem_smp2p_out 0>; 241 + qcom,smem-state-names = "stop"; 242 + 243 + status = "disabled"; 244 + 245 + glink-edge { 246 + interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 247 + label = "mpss"; 248 + qcom,remote-pid = <1>; 249 + mboxes = <&apcs 15>; 250 + }; 251 + }; 252 + 253 + sdhc_1: mmc@8804000 { 228 254 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 229 255 reg = <0x08804000 0x1000>; 230 256 reg-names = "hc_mem"; ··· 342 154 <&gcc GCC_SDCC1_AHB_CLK>; 343 155 clock-names = "core", "iface"; 344 156 status = "disabled"; 157 + }; 158 + 159 + mem_noc: interconnect@9680000 { 160 + compatible = "qcom,sdx65-mem-noc"; 161 + reg = <0x09680000 0x27200>; 162 + #interconnect-cells = <1>; 163 + qcom,bcm-voters = <&apps_bcm_voter>; 164 + }; 165 + 166 + usb: usb@a6f8800 { 167 + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; 168 + reg = <0x0a6f8800 0x400>; 169 + status = "disabled"; 170 + #address-cells = <1>; 171 + #size-cells = <1>; 172 + ranges; 173 + 174 + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 175 + <&gcc GCC_USB30_MASTER_CLK>, 176 + <&gcc GCC_USB30_MSTR_AXI_CLK>, 177 + <&gcc GCC_USB30_MOCK_UTMI_CLK>, 178 + <&gcc GCC_USB30_SLEEP_CLK>; 179 + clock-names = "cfg_noc", "core", "iface", "mock_utmi", 180 + "sleep"; 181 + 182 + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 183 + <&gcc GCC_USB30_MASTER_CLK>; 184 + assigned-clock-rates = <19200000>, <200000000>; 185 + 186 + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 187 + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, 188 + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, 189 + <&pdc 18 IRQ_TYPE_EDGE_BOTH>; 190 + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 191 + "ss_phy_irq", "dm_hs_phy_irq"; 192 + 193 + power-domains = <&gcc USB30_GDSC>; 194 + 195 + resets = <&gcc GCC_USB30_BCR>; 196 + 197 + usb_dwc3: usb@a600000 { 198 + compatible = "snps,dwc3"; 199 + reg = <0x0a600000 0xcd00>; 200 + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 201 + iommus = <&apps_smmu 0x1a0 0x0>; 202 + snps,dis_u2_susphy_quirk; 203 + snps,dis_enblslpm_quirk; 204 + phys = <&usb_hsphy>, <&usb_ssphy>; 205 + phy-names = "usb2-phy", "usb3-phy"; 206 + }; 207 + }; 208 + 209 + restart@c264000 { 210 + compatible = "qcom,pshold"; 211 + reg = <0x0c264000 0x1000>; 345 212 }; 346 213 347 214 spmi_bus: qcom,spmi@c440000 { ··· 437 194 #interrupt-cells = <2>; 438 195 interrupt-parent = <&intc>; 439 196 interrupt-controller; 197 + }; 198 + 199 + imem@1468f000 { 200 + compatible = "simple-mfd"; 201 + reg = <0x1468f000 0x1000>; 202 + ranges = <0x0 0x1468f000 0x1000>; 203 + #address-cells = <1>; 204 + #size-cells = <1>; 205 + 206 + pil-reloc@94c { 207 + compatible = "qcom,pil-reloc-info"; 208 + reg = <0x94c 0xc8>; 209 + }; 440 210 }; 441 211 442 212 apps_smmu: iommu@15000000 { ··· 516 260 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 517 261 clock-names = "ref", "pll", "aux"; 518 262 #clock-cells = <0>; 263 + }; 264 + 265 + watchdog@17817000 { 266 + compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; 267 + reg = <0x17817000 0x1000>; 268 + clocks = <&sleep_clk>; 519 269 }; 520 270 521 271 timer@17820000 { ··· 661 399 }; 662 400 }; 663 401 }; 402 + 403 + apps_bcm_voter: bcm-voter { 404 + compatible = "qcom,bcm-voter"; 405 + }; 406 + 664 407 }; 665 408 }; 666 409