Blackfin: bf537: demux port H mask A and emac rx ints

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The BF537 SIC combines the gpio port H mask A interrupts with the
emac rx interrupt, so we need to demux this in software.

It also combines the gpio port H mask B and the emac tx interrupts,
and the watchdog and port F mask B interrupts, but since we don't
support mask B yet, just add the defines for now.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Mike Frysinger 15 years ago 8c054103 e2a8092c

+77 -20

5 changed files

expand all

arch

blackfin

include

asm

irq_handler.h

kernel

bfin_gpio.c

mach-bf537

include

mach

irq.h

ints-priority.c

mach-common

ints-priority.c

arch/blackfin/include/asm/irq_handler.h

··· 60 60 61 61 struct irq_desc; 62 62 extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *); 63 + extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *); 63 64 64 65 #endif

+1 -1

arch/blackfin/kernel/bfin_gpio.c

··· 535 535 #if defined(BF533_FAMILY) 536 536 IRQ_PROG_INTB 537 537 #elif defined(BF537_FAMILY) 538 - IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX 538 + IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX 539 539 #elif defined(BF538_FAMILY) 540 540 IRQ_PORTF_INTB 541 541 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)

+26 -7

arch/blackfin/mach-bf537/include/mach/irq.h

··· 28 28 #define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */ 29 29 #define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */ 30 30 #define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */ 31 - #define IRQ_MAC_RX BFIN_IRQ(17) /* DMA1 (Ethernet RX) Interrupt */ 32 - #define IRQ_MAC_TX BFIN_IRQ(18) /* DMA2 (Ethernet TX) Interrupt */ 31 + #define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */ 32 + #define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */ 33 33 #define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */ 34 34 #define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */ 35 35 #define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */ ··· 38 38 #define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */ 39 39 #define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */ 40 40 #define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */ 41 - #define IRQ_PROG_INTA BFIN_IRQ(27) /* PF Ports F&G (PF15:0) Interrupt A */ 42 - #define IRQ_PORTG_INTB BFIN_IRQ(28) /* PF Port G (PF15:0) Interrupt B */ 41 + #define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */ 42 + #define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */ 43 43 #define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */ 44 44 #define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */ 45 - #define IRQ_PROG_INTB BFIN_IRQ(31) /* PF Ports F (PF15:0) Interrupt B */ 46 - #define IRQ_WATCH BFIN_IRQ(32) /* Watch Dog Timer */ 45 + #define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */ 47 46 48 47 #define SYS_IRQS 39 49 48 ··· 117 118 #define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ 118 119 #define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 119 120 120 - #define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 121 + #define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */ 122 + #define IRQ_PORTH_INTA 107 /* Port H Interrupt A */ 123 + 124 + #if 0 /* No Interrupt B support (yet) */ 125 + #define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */ 126 + #define IRQ_PORTH_INTB 109 /* Port H Interrupt B */ 127 + #else 128 + #define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX 129 + #endif 130 + 131 + #define IRQ_PORTF_INTA 110 /* Port F Interrupt A */ 132 + #define IRQ_PORTG_INTA 111 /* Port G Interrupt A */ 133 + 134 + #if 0 /* No Interrupt B support (yet) */ 135 + #define IRQ_WATCH 112 /* Watchdog Timer */ 136 + #define IRQ_PORTF_INTB 113 /* Port F Interrupt B */ 137 + #else 138 + #define IRQ_WATCH IRQ_PF_INTB_WATCH 139 + #endif 140 + 141 + #define NR_MACH_IRQS (113 + 1) 121 142 122 143 /* IAR0 BIT FIELDS */ 123 144 #define IRQ_PLL_WAKEUP_POS 0

+39

arch/blackfin/mach-bf537/ints-priority.c

··· 14 14 #include <asm/bfin5xx_spi.h> 15 15 #include <asm/bfin_sport.h> 16 16 #include <asm/bfin_can.h> 17 + #include <asm/bfin_dma.h> 17 18 #include <asm/dpmc.h> 18 19 19 20 void __init program_IAR(void) ··· 158 157 159 158 } 160 159 160 + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 161 + static int mac_rx_int_mask; 162 + 163 + static void bf537_mac_rx_mask_irq(struct irq_data *d) 164 + { 165 + mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX)); 166 + if (!mac_rx_int_mask) 167 + bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX); 168 + } 169 + 170 + static void bf537_mac_rx_unmask_irq(struct irq_data *d) 171 + { 172 + bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX); 173 + mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX); 174 + } 175 + 176 + static struct irq_chip bf537_mac_rx_irqchip = { 177 + .name = "ERROR", 178 + .irq_ack = bfin_ack_noop, 179 + .irq_mask_ack = bf537_mac_rx_mask_irq, 180 + .irq_mask = bf537_mac_rx_mask_irq, 181 + .irq_unmask = bf537_mac_rx_unmask_irq, 182 + }; 183 + 184 + static void bf537_demux_mac_rx_irq(unsigned int int_irq, 185 + struct irq_desc *desc) 186 + { 187 + if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR)) 188 + bfin_handle_irq(IRQ_MAC_RX); 189 + else 190 + bfin_demux_gpio_irq(int_irq, desc); 191 + } 192 + #endif 193 + 161 194 void __init init_mach_irq(void) 162 195 { 163 196 int irq; ··· 207 172 handle_level_irq); 208 173 209 174 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 175 + irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq); 176 + irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq); 177 + irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq); 178 + 210 179 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); 211 180 #endif 212 181 }

+10 -12

arch/blackfin/mach-common/ints-priority.c

··· 582 582 } 583 583 } 584 584 585 - static void bfin_demux_gpio_irq(unsigned int inta_irq, 586 - struct irq_desc *desc) 585 + void bfin_demux_gpio_irq(unsigned int inta_irq, 586 + struct irq_desc *desc) 587 587 { 588 588 unsigned int irq; 589 589 590 590 switch (inta_irq) { 591 591 #if defined(BF537_FAMILY) 592 - case IRQ_PROG_INTA: 592 + case IRQ_PF_INTA_PG_INTA: 593 593 bfin_demux_gpio_block(IRQ_PF0); 594 594 irq = IRQ_PG0; 595 595 break; 596 - # if !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 597 - case IRQ_MAC_RX: 596 + case IRQ_PH_INTA_MAC_RX: 598 597 irq = IRQ_PH0; 599 598 break; 600 - # endif 601 599 #elif defined(BF533_FAMILY) 602 600 case IRQ_PROG_INTA: 603 601 irq = IRQ_PF0; ··· 879 881 # define bfin_gpio_set_wake NULL 880 882 #endif 881 883 882 - static void bfin_demux_gpio_irq(unsigned int inta_irq, 883 - struct irq_desc *desc) 884 + void bfin_demux_gpio_irq(unsigned int inta_irq, 885 + struct irq_desc *desc) 884 886 { 885 887 u32 bank, pint_val; 886 888 u32 request, irq; ··· 999 1001 irq_set_chip(irq, &bfin_internal_irqchip); 1000 1002 1001 1003 switch (irq) { 1002 - #if defined(CONFIG_BF53x) 1004 + #if defined(BF537_FAMILY) 1005 + case IRQ_PH_INTA_MAC_RX: 1006 + case IRQ_PF_INTA_PG_INTA: 1007 + #elif defined(BF533_FAMILY) 1003 1008 case IRQ_PROG_INTA: 1004 - # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 1005 - case IRQ_MAC_RX: 1006 - # endif 1007 1009 #elif defined(CONFIG_BF54x) 1008 1010 case IRQ_PINT0: 1009 1011 case IRQ_PINT1: