ARM: dts: meson: move the L2 cache-controller inside the SoC node

All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.

Signed-off-by: Martin Blumenstingl <[e-mail]>
Signed-off-by: Kevin Hilman <[e-mail]>
Tested-by: Kevin Hilman <[e-mail]>
Reviewed-by: Neil Armstrong <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]

arch/arm/boot/dts/meson.dtsi

···
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
-	L2: cache-controller@c4200000 {
-		compatible = "arm,pl310-cache";
-		reg = <0xc4200000 0x1000>;
-		cache-unified;
-		cache-level = <2>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
···
 					     <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
 					     <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
 			};
+		};
+
+		L2: cache-controller@c4200000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xc4200000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
 		};
 
 		periph: bus@c4300000 {