tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: SOF: Intel: hda: Add sof_tgl_ops for TGL platforms
Separate the dsp ops for TGL ops to specify the use of ICCMAX
FW boot sequence in the run op. All other ops are identical.
Also separate the TGL descriptors into a separate file to make
it easier to follow.
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20200826184532.1612070-8-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Ranjani Sridharan
and committed by
Mark Brown
8b98491a
acf705a4
+147
-22
+1
-1
sound/soc/sof/intel/Makefile
+1
-1
sound/soc/sof/intel/Makefile
···
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snd-sof-intel-hda-common-objs := hda.o hda-loader.o hda-stream.o hda-trace.o \
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hda-dsp.o hda-ipc.o hda-ctrl.o hda-pcm.o \
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hda-dai.o hda-bus.o \
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-
apl.o cnl.o
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apl.o cnl.o tgl.o
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snd-sof-intel-hda-common-$(CONFIG_SND_SOC_SOF_HDA_PROBES) += hda-compress.o
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snd-sof-intel-hda-objs := hda-codec.o
+3
-20
sound/soc/sof/intel/cnl.c
+3
-20
sound/soc/sof/intel/cnl.c
···
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
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static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
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irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 hipci;
···
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return false;
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}
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static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg)
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int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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struct sof_ipc_cmd_hdr *hdr;
···
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return 0;
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}
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static void cnl_ipc_dump(struct snd_sof_dev *sdev)
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void cnl_ipc_dump(struct snd_sof_dev *sdev)
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{
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u32 hipcctl;
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u32 hipcida;
···
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc tgl_chip_info = {
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/* Tigerlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc ehl_chip_info = {
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/* Elkhartlake */
+4
sound/soc/sof/intel/hda-ipc.h
+4
sound/soc/sof/intel/hda-ipc.h
+1
sound/soc/sof/intel/hda.h
+1
sound/soc/sof/intel/hda.h
···
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*/
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extern const struct snd_sof_dsp_ops sof_apl_ops;
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extern const struct snd_sof_dsp_ops sof_cnl_ops;
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extern const struct snd_sof_dsp_ops sof_tgl_ops;
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extern const struct sof_intel_dsp_desc apl_chip_info;
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extern const struct sof_intel_dsp_desc cnl_chip_info;
+137
sound/soc/sof/intel/tgl.c
+137
sound/soc/sof/intel/tgl.c
···
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+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2020 Intel Corporation. All rights reserved.
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//
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// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Tigerlake.
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*/
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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/* Tigerlake ops */
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const struct snd_sof_dsp_ops sof_tgl_ops = {
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/* probe and remove */
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.probe = hda_dsp_probe,
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.remove = hda_dsp_remove,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* Block IO */
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.block_read = sof_block_read,
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.block_write = sof_block_write,
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/* doorbell */
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.irq_thread = cnl_ipc_irq_thread,
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/* ipc */
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.send_msg = cnl_ipc_send_msg,
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.fw_ready = sof_fw_ready,
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.get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
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.get_window_offset = hda_dsp_ipc_get_window_offset,
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.ipc_msg_data = hda_ipc_msg_data,
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.ipc_pcm_params = hda_ipc_pcm_params,
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/* machine driver */
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.machine_select = hda_machine_select,
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.machine_register = sof_machine_register,
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.machine_unregister = sof_machine_unregister,
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.set_mach_params = hda_set_mach_params,
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/* debug */
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.debug_map = tgl_dsp_debugfs,
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.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs),
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.dbg_dump = hda_dsp_dump,
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.ipc_dump = cnl_ipc_dump,
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/* stream callbacks */
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.pcm_open = hda_dsp_pcm_open,
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.pcm_close = hda_dsp_pcm_close,
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.pcm_hw_params = hda_dsp_pcm_hw_params,
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.pcm_hw_free = hda_dsp_stream_hw_free,
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.pcm_trigger = hda_dsp_pcm_trigger,
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.pcm_pointer = hda_dsp_pcm_pointer,
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
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/* probe callbacks */
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.probe_assign = hda_probe_compr_assign,
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.probe_free = hda_probe_compr_free,
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.probe_set_params = hda_probe_compr_set_params,
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.probe_trigger = hda_probe_compr_trigger,
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.probe_pointer = hda_probe_compr_pointer,
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#endif
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/* firmware loading */
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.load_firmware = snd_sof_load_firmware_raw,
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/* pre/post fw run */
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.pre_fw_run = hda_dsp_pre_fw_run,
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.post_fw_run = hda_dsp_post_fw_run,
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/* dsp core power up/down */
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.core_power_up = hda_dsp_enable_core,
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.core_power_down = hda_dsp_core_reset_power_down,
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/* firmware run */
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.run = hda_dsp_cl_boot_firmware_iccmax,
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/* trace callback */
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.trace_init = hda_dsp_trace_init,
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.trace_release = hda_dsp_trace_release,
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.trace_trigger = hda_dsp_trace_trigger,
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/* DAI drivers */
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.drv = skl_dai,
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.num_drv = SOF_SKL_NUM_DAIS,
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/* PM */
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.suspend = hda_dsp_suspend,
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.resume = hda_dsp_resume,
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.runtime_suspend = hda_dsp_runtime_suspend,
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.runtime_resume = hda_dsp_runtime_resume,
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.runtime_idle = hda_dsp_runtime_idle,
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.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
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.set_power_state = hda_dsp_set_power_state,
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/* ALSA HW info flags */
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.hw_info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
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.arch_ops = &sof_xtensa_arch_ops,
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};
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EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc tgl_chip_info = {
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/* Tigerlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);