···2020#define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)2121#define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)2222#define AIU_RST_SOFT_I2S_FAST BIT(0)2323+#define AIU_I2S_MISC_HOLD_EN BIT(2)2424+#define AIU_I2S_MISC_FORCE_LEFT_RIGHT BIT(4)23252426#define AIU_FIFO_I2S_BLOCK 2562527···9290 unsigned int val;9391 int ret;94929393+ snd_soc_component_update_bits(component, AIU_I2S_MISC,9494+ AIU_I2S_MISC_HOLD_EN,9595+ AIU_I2S_MISC_HOLD_EN);9696+9597 ret = aiu_fifo_hw_params(substream, params, dai);9698 if (ret)9799 return ret;···122116 val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);123117 snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,124118 AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);119119+120120+ /*121121+ * Most (all?) supported SoCs have this bit set by default. The vendor122122+ * driver however sets it manually (depending on the version either123123+ * while un-setting AIU_I2S_MISC_HOLD_EN or right before that). Follow124124+ * the same approach for consistency with the vendor driver.125125+ */126126+ snd_soc_component_update_bits(component, AIU_I2S_MISC,127127+ AIU_I2S_MISC_FORCE_LEFT_RIGHT,128128+ AIU_I2S_MISC_FORCE_LEFT_RIGHT);129129+130130+ snd_soc_component_update_bits(component, AIU_I2S_MISC,131131+ AIU_I2S_MISC_HOLD_EN, 0);125132126133 return 0;127134}