Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'tegra-for-3.16-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

Merge "ARM: tegra: device tree changes for 3.16" from Stephen Warren:

The bulk of Tegra changes for 3.16 are to device trees. Highlights are:

- New board support for:
- Jetson TK1.
- SHIELD.
- Tegra Note 7.
- Colibri T30 module.
- HDMI support on Venice2.
- SD card write-protect GPIOs added to some boards.
- Numerous regulator cleanups.

* tag 'tegra-for-3.16-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: initial add of Colibri T30
ARM: tegra: add device tree for SHIELD
ARM: tegra: add SD wp-gpios to Venice2 DT
ARM: tegra: add Tegra Note 7 device tree
ARM: tegra: add SD wp-gpios to Dalmore DT
ARM: tegra: add SD wp-gpios to Jetson TK1 DT
ARM: tegra: use correct audio CODEC on Jetson TK1
ARM: tegra: dalmore - Add DSI power supply
ARM: tegra: dalmore - Add +5V HDMI supply
ARM: tegra: beaver - Add +5V HDMI supply
ARM: tegra: harmony - Add +5V HDMI supply
ARM: tegra: jetson-tk1 - Enable HDMI support
ARM: tegra: venice2 - Enable HDMI
ARM: tegra: Add Tegra124 HDMI support
ARM: tegra: fix Venice2 SD card VQMMC supply
ARM: tegra: make Venice's +3.3V_RUN regulator always on
ARM: tegra: fix Jetson TK1 SD card supply
ARM: tegra: define Jetson TK1 regulators
ARM: tegra: add Jetson TK1 device tree

Signed-off-by: Olof Johansson <olof@lixom.net>

+3965 -8
+4
arch/arm/boot/dts/Makefile
··· 370 370 tegra30-beaver.dtb \ 371 371 tegra30-cardhu-a02.dtb \ 372 372 tegra30-cardhu-a04.dtb \ 373 + tegra30-colibri-eval-v3.dtb \ 373 374 tegra114-dalmore.dtb \ 375 + tegra114-roth.dtb \ 376 + tegra114-tn7.dtb \ 377 + tegra124-jetson-tk1.dtb \ 374 378 tegra124-venice2.dtb 375 379 dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 376 380 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
+16 -5
arch/arm/boot/dts/tegra114-dalmore.dts
··· 25 25 hdmi@54280000 { 26 26 status = "okay"; 27 27 28 + hdmi-supply = <&vdd_5v0_hdmi>; 28 29 vdd-supply = <&vdd_hdmi_reg>; 29 30 pll-supply = <&palmas_smps3_reg>; 30 31 ··· 36 35 37 36 dsi@54300000 { 38 37 status = "okay"; 38 + 39 + avdd-dsi-csi-supply = <&avdd_1v2_reg>; 39 40 40 41 panel@0 { 41 42 compatible = "panasonic,vvx10f004b00", ··· 985 982 regulator-max-microvolt = <2800000>; 986 983 }; 987 984 988 - ldo3 { 985 + avdd_1v2_reg: ldo3 { 989 986 regulator-name = "avdd-dsi-csi"; 990 987 regulator-min-microvolt = <1200000>; 991 988 regulator-max-microvolt = <1200000>; 992 - regulator-always-on; 993 - regulator-boot-on; 994 989 }; 995 990 996 991 ldo4 { ··· 1106 1105 1107 1106 sdhci@78000400 { 1108 1107 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1108 + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; 1109 1109 bus-width = <4>; 1110 1110 status = "okay"; 1111 1111 }; ··· 1233 1231 regulator-name = "vdd_hdmi_5v0"; 1234 1232 regulator-min-microvolt = <5000000>; 1235 1233 regulator-max-microvolt = <5000000>; 1236 - enable-active-high; 1237 - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1238 1234 vin-supply = <&tps65090_dcdc1_reg>; 1239 1235 }; 1240 1236 ··· 1244 1244 regulator-max-microvolt = <1800000>; 1245 1245 enable-active-high; 1246 1246 gpio = <&palmas_gpio 6 0>; 1247 + }; 1248 + 1249 + vdd_5v0_hdmi: regulator@7 { 1250 + compatible = "regulator-fixed"; 1251 + reg = <7>; 1252 + regulator-name = "VDD_5V0_HDMI_CON"; 1253 + regulator-min-microvolt = <5000000>; 1254 + regulator-max-microvolt = <5000000>; 1255 + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1256 + enable-active-high; 1257 + vin-supply = <&tps65090_dcdc1_reg>; 1247 1258 }; 1248 1259 }; 1249 1260
+1113
arch/arm/boot/dts/tegra114-roth.dts
··· 1 + /dts-v1/; 2 + 3 + #include <dt-bindings/input/input.h> 4 + #include "tegra114.dtsi" 5 + 6 + / { 7 + model = "NVIDIA SHIELD"; 8 + compatible = "nvidia,roth", "nvidia,tegra114"; 9 + 10 + chosen { 11 + /* SHIELD's bootloader's arguments need to be overridden */ 12 + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; 13 + /* SHIELD's bootloader will place initrd at this address */ 14 + linux,initrd-start = <0x82000000>; 15 + linux,initrd-end = <0x82800000>; 16 + }; 17 + 18 + firmware { 19 + trusted-foundations { 20 + compatible = "tlm,trusted-foundations"; 21 + tlm,version-major = <2>; 22 + tlm,version-minor = <8>; 23 + }; 24 + }; 25 + 26 + memory { 27 + /* memory >= 0x79600000 is reserved for firmware usage */ 28 + reg = <0x80000000 0x79600000>; 29 + }; 30 + 31 + pinmux@70000868 { 32 + pinctrl-names = "default"; 33 + pinctrl-0 = <&state_default>; 34 + 35 + state_default: pinmux { 36 + clk1_out_pw4 { 37 + nvidia,pins = "clk1_out_pw4"; 38 + nvidia,function = "extperiph1"; 39 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 40 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 41 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 42 + }; 43 + dap1_din_pn1 { 44 + nvidia,pins = "dap1_din_pn1"; 45 + nvidia,function = "i2s0"; 46 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 47 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 48 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 49 + }; 50 + dap1_dout_pn2 { 51 + nvidia,pins = "dap1_dout_pn2", 52 + "dap1_fs_pn0", 53 + "dap1_sclk_pn3"; 54 + nvidia,function = "i2s0"; 55 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 56 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 57 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 58 + }; 59 + dap2_din_pa4 { 60 + nvidia,pins = "dap2_din_pa4"; 61 + nvidia,function = "i2s1"; 62 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 63 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 64 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 65 + }; 66 + dap2_dout_pa5 { 67 + nvidia,pins = "dap2_dout_pa5", 68 + "dap2_fs_pa2", 69 + "dap2_sclk_pa3"; 70 + nvidia,function = "i2s1"; 71 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 72 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 73 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 74 + }; 75 + dap4_din_pp5 { 76 + nvidia,pins = "dap4_din_pp5", 77 + "dap4_dout_pp6", 78 + "dap4_fs_pp4", 79 + "dap4_sclk_pp7"; 80 + nvidia,function = "i2s3"; 81 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 82 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 83 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 84 + }; 85 + dvfs_pwm_px0 { 86 + nvidia,pins = "dvfs_pwm_px0", 87 + "dvfs_clk_px2"; 88 + nvidia,function = "cldvfs"; 89 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 90 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 91 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 92 + }; 93 + ulpi_clk_py0 { 94 + nvidia,pins = "ulpi_clk_py0", 95 + "ulpi_data0_po1", 96 + "ulpi_data1_po2", 97 + "ulpi_data2_po3", 98 + "ulpi_data3_po4", 99 + "ulpi_data4_po5", 100 + "ulpi_data5_po6", 101 + "ulpi_data6_po7", 102 + "ulpi_data7_po0"; 103 + nvidia,function = "ulpi"; 104 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 105 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 106 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 107 + }; 108 + ulpi_dir_py1 { 109 + nvidia,pins = "ulpi_dir_py1", 110 + "ulpi_nxt_py2"; 111 + nvidia,function = "ulpi"; 112 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 113 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 114 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 115 + }; 116 + ulpi_stp_py3 { 117 + nvidia,pins = "ulpi_stp_py3"; 118 + nvidia,function = "ulpi"; 119 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 121 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 122 + }; 123 + cam_i2c_scl_pbb1 { 124 + nvidia,pins = "cam_i2c_scl_pbb1", 125 + "cam_i2c_sda_pbb2"; 126 + nvidia,function = "i2c3"; 127 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 128 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 129 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 130 + nvidia,lock = <TEGRA_PIN_DISABLE>; 131 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 132 + }; 133 + cam_mclk_pcc0 { 134 + nvidia,pins = "cam_mclk_pcc0", 135 + "pbb0"; 136 + nvidia,function = "vi_alt3"; 137 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 139 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 140 + nvidia,lock = <TEGRA_PIN_DISABLE>; 141 + }; 142 + pbb4 { 143 + nvidia,pins = "pbb4"; 144 + nvidia,function = "vgp4"; 145 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 146 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 147 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 148 + nvidia,lock = <TEGRA_PIN_DISABLE>; 149 + }; 150 + gen2_i2c_scl_pt5 { 151 + nvidia,pins = "gen2_i2c_scl_pt5", 152 + "gen2_i2c_sda_pt6"; 153 + nvidia,function = "i2c2"; 154 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 155 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 156 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 157 + nvidia,lock = <TEGRA_PIN_DISABLE>; 158 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 159 + }; 160 + gmi_a16_pj7 { 161 + nvidia,pins = "gmi_a16_pj7", 162 + "gmi_a19_pk7"; 163 + nvidia,function = "uartd"; 164 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 166 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 167 + }; 168 + gmi_a17_pb0 { 169 + nvidia,pins = "gmi_a17_pb0", 170 + "gmi_a18_pb1"; 171 + nvidia,function = "uartd"; 172 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 174 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 175 + }; 176 + gmi_ad5_pg5 { 177 + nvidia,pins = "gmi_ad5_pg5", 178 + "gmi_wr_n_pi0"; 179 + nvidia,function = "spi4"; 180 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 181 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 182 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 183 + }; 184 + gmi_ad6_pg6 { 185 + nvidia,pins = "gmi_ad6_pg6", 186 + "gmi_ad7_pg7"; 187 + nvidia,function = "spi4"; 188 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 189 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 190 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 191 + }; 192 + gmi_ad12_ph4 { 193 + nvidia,pins = "gmi_ad12_ph4"; 194 + nvidia,function = "rsvd4"; 195 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 196 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 197 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 198 + }; 199 + gmi_cs6_n_pi13 { 200 + nvidia,pins = "gmi_cs6_n_pi3"; 201 + nvidia,function = "nand"; 202 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 203 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 204 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 205 + }; 206 + gmi_ad9_ph1 { 207 + nvidia,pins = "gmi_ad9_ph1"; 208 + nvidia,function = "pwm1"; 209 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 210 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 211 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 212 + }; 213 + gmi_cs1_n_pj2 { 214 + nvidia,pins = "gmi_cs1_n_pj2", 215 + "gmi_oe_n_pi1"; 216 + nvidia,function = "soc"; 217 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 218 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 219 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 220 + }; 221 + gmi_rst_n_pi4 { 222 + nvidia,pins = "gmi_rst_n_pi4"; 223 + nvidia,function = "gmi"; 224 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 225 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 226 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 227 + }; 228 + gmi_iordy_pi5 { 229 + nvidia,pins = "gmi_iordy_pi5"; 230 + nvidia,function = "gmi"; 231 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 232 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 233 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 234 + }; 235 + clk2_out_pw5 { 236 + nvidia,pins = "clk2_out_pw5"; 237 + nvidia,function = "extperiph2"; 238 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 239 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 240 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 241 + }; 242 + sdmmc1_clk_pz0 { 243 + nvidia,pins = "sdmmc1_clk_pz0"; 244 + nvidia,function = "sdmmc1"; 245 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 246 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 247 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 248 + }; 249 + sdmmc1_cmd_pz1 { 250 + nvidia,pins = "sdmmc1_cmd_pz1", 251 + "sdmmc1_dat0_py7", 252 + "sdmmc1_dat1_py6", 253 + "sdmmc1_dat2_py5", 254 + "sdmmc1_dat3_py4"; 255 + nvidia,function = "sdmmc1"; 256 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 257 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 258 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 259 + }; 260 + sdmmc3_clk_pa6 { 261 + nvidia,pins = "sdmmc3_clk_pa6"; 262 + nvidia,function = "sdmmc3"; 263 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 264 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 265 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 266 + }; 267 + sdmmc3_cmd_pa7 { 268 + nvidia,pins = "sdmmc3_cmd_pa7", 269 + "sdmmc3_dat0_pb7", 270 + "sdmmc3_dat1_pb6", 271 + "sdmmc3_dat2_pb5", 272 + "sdmmc3_dat3_pb4", 273 + "sdmmc3_cd_n_pv2", 274 + "sdmmc3_clk_lb_out_pee4", 275 + "sdmmc3_clk_lb_in_pee5"; 276 + nvidia,function = "sdmmc3"; 277 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 278 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 279 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 280 + }; 281 + kb_col4_pq4 { 282 + nvidia,pins = "kb_col4_pq4"; 283 + nvidia,function = "sdmmc3"; 284 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 285 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 286 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 287 + }; 288 + sdmmc4_clk_pcc4 { 289 + nvidia,pins = "sdmmc4_clk_pcc4"; 290 + nvidia,function = "sdmmc4"; 291 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 292 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 293 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 294 + }; 295 + sdmmc4_cmd_pt7 { 296 + nvidia,pins = "sdmmc4_cmd_pt7", 297 + "sdmmc4_dat0_paa0", 298 + "sdmmc4_dat1_paa1", 299 + "sdmmc4_dat2_paa2", 300 + "sdmmc4_dat3_paa3", 301 + "sdmmc4_dat4_paa4", 302 + "sdmmc4_dat5_paa5", 303 + "sdmmc4_dat6_paa6", 304 + "sdmmc4_dat7_paa7"; 305 + nvidia,function = "sdmmc4"; 306 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 307 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 308 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 309 + }; 310 + clk_32k_out_pa0 { 311 + nvidia,pins = "clk_32k_out_pa0"; 312 + nvidia,function = "blink"; 313 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 314 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 315 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 316 + }; 317 + kb_col0_pq0 { 318 + nvidia,pins = "kb_col0_pq0", 319 + "kb_col1_pq1", 320 + "kb_col2_pq2", 321 + "kb_row0_pr0", 322 + "kb_row1_pr1", 323 + "kb_row2_pr2", 324 + "kb_row8_ps0"; 325 + nvidia,function = "kbc"; 326 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 327 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 328 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 329 + }; 330 + kb_row7_pr7 { 331 + nvidia,pins = "kb_row7_pr7"; 332 + nvidia,function = "rsvd2"; 333 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 334 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 335 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 336 + }; 337 + kb_row10_ps2 { 338 + nvidia,pins = "kb_row10_ps2"; 339 + nvidia,function = "uarta"; 340 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 341 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 342 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 343 + }; 344 + kb_row9_ps1 { 345 + nvidia,pins = "kb_row9_ps1"; 346 + nvidia,function = "uarta"; 347 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 348 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 349 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 350 + }; 351 + pwr_i2c_scl_pz6 { 352 + nvidia,pins = "pwr_i2c_scl_pz6", 353 + "pwr_i2c_sda_pz7"; 354 + nvidia,function = "i2cpwr"; 355 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 356 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 357 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 358 + nvidia,lock = <TEGRA_PIN_DISABLE>; 359 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 360 + }; 361 + sys_clk_req_pz5 { 362 + nvidia,pins = "sys_clk_req_pz5"; 363 + nvidia,function = "sysclk"; 364 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 365 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 366 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 367 + }; 368 + core_pwr_req { 369 + nvidia,pins = "core_pwr_req"; 370 + nvidia,function = "pwron"; 371 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 372 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 373 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 374 + }; 375 + cpu_pwr_req { 376 + nvidia,pins = "cpu_pwr_req"; 377 + nvidia,function = "cpu"; 378 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 379 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 380 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381 + }; 382 + pwr_int_n { 383 + nvidia,pins = "pwr_int_n"; 384 + nvidia,function = "pmi"; 385 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 386 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 387 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 388 + }; 389 + reset_out_n { 390 + nvidia,pins = "reset_out_n"; 391 + nvidia,function = "reset_out_n"; 392 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 393 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 394 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 395 + }; 396 + clk3_out_pee0 { 397 + nvidia,pins = "clk3_out_pee0"; 398 + nvidia,function = "extperiph3"; 399 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 400 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 401 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 402 + }; 403 + gen1_i2c_scl_pc4 { 404 + nvidia,pins = "gen1_i2c_scl_pc4", 405 + "gen1_i2c_sda_pc5"; 406 + nvidia,function = "i2c1"; 407 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 408 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 409 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 410 + nvidia,lock = <TEGRA_PIN_DISABLE>; 411 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 412 + }; 413 + uart2_cts_n_pj5 { 414 + nvidia,pins = "uart2_cts_n_pj5"; 415 + nvidia,function = "uartb"; 416 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 417 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 418 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 419 + }; 420 + uart2_rts_n_pj6 { 421 + nvidia,pins = "uart2_rts_n_pj6"; 422 + nvidia,function = "uartb"; 423 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 424 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 425 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 426 + }; 427 + uart2_rxd_pc3 { 428 + nvidia,pins = "uart2_rxd_pc3"; 429 + nvidia,function = "irda"; 430 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 431 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 432 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 433 + }; 434 + uart2_txd_pc2 { 435 + nvidia,pins = "uart2_txd_pc2"; 436 + nvidia,function = "irda"; 437 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 438 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 439 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 440 + }; 441 + uart3_cts_n_pa1 { 442 + nvidia,pins = "uart3_cts_n_pa1", 443 + "uart3_rxd_pw7"; 444 + nvidia,function = "uartc"; 445 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 446 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 447 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 448 + }; 449 + uart3_rts_n_pc0 { 450 + nvidia,pins = "uart3_rts_n_pc0", 451 + "uart3_txd_pw6"; 452 + nvidia,function = "uartc"; 453 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 454 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 455 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 456 + }; 457 + owr { 458 + nvidia,pins = "owr"; 459 + nvidia,function = "owr"; 460 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 461 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 462 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 463 + }; 464 + hdmi_cec_pee3 { 465 + nvidia,pins = "hdmi_cec_pee3"; 466 + nvidia,function = "cec"; 467 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 468 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 469 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 470 + nvidia,lock = <TEGRA_PIN_DISABLE>; 471 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 472 + }; 473 + ddc_scl_pv4 { 474 + nvidia,pins = "ddc_scl_pv4", 475 + "ddc_sda_pv5"; 476 + nvidia,function = "i2c4"; 477 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 478 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 479 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 480 + nvidia,lock = <TEGRA_PIN_DISABLE>; 481 + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 482 + }; 483 + spdif_in_pk6 { 484 + nvidia,pins = "spdif_in_pk6"; 485 + nvidia,function = "usb"; 486 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 487 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 488 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489 + nvidia,lock = <TEGRA_PIN_DISABLE>; 490 + }; 491 + usb_vbus_en0_pn4 { 492 + nvidia,pins = "usb_vbus_en0_pn4"; 493 + nvidia,function = "usb"; 494 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 495 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 496 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 497 + nvidia,lock = <TEGRA_PIN_DISABLE>; 498 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 499 + }; 500 + gpio_x6_aud_px6 { 501 + nvidia,pins = "gpio_x6_aud_px6"; 502 + nvidia,function = "spi6"; 503 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 504 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 505 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506 + }; 507 + gpio_x1_aud_px1 { 508 + nvidia,pins = "gpio_x1_aud_px1"; 509 + nvidia,function = "rsvd2"; 510 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 511 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 512 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 513 + }; 514 + gpio_x7_aud_px7 { 515 + nvidia,pins = "gpio_x7_aud_px7"; 516 + nvidia,function = "rsvd1"; 517 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 518 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 519 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 520 + }; 521 + gmi_adv_n_pk0 { 522 + nvidia,pins = "gmi_adv_n_pk0"; 523 + nvidia,function = "gmi"; 524 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 525 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 526 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 527 + }; 528 + gmi_cs0_n_pj0 { 529 + nvidia,pins = "gmi_cs0_n_pj0"; 530 + nvidia,function = "gmi"; 531 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 532 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 533 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 534 + }; 535 + pu3 { 536 + nvidia,pins = "pu3"; 537 + nvidia,function = "pwm0"; 538 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 539 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 540 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 541 + }; 542 + gpio_x4_aud_px4 { 543 + nvidia,pins = "gpio_x4_aud_px4", 544 + "gpio_x5_aud_px5"; 545 + nvidia,function = "rsvd1"; 546 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 547 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 548 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 549 + }; 550 + gpio_x3_aud_px3 { 551 + nvidia,pins = "gpio_x3_aud_px3"; 552 + nvidia,function = "rsvd4"; 553 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 554 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 555 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 556 + }; 557 + gpio_w2_aud_pw2 { 558 + nvidia,pins = "gpio_w2_aud_pw2"; 559 + nvidia,function = "rsvd2"; 560 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 561 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 562 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 563 + }; 564 + gpio_w3_aud_pw3 { 565 + nvidia,pins = "gpio_w3_aud_pw3"; 566 + nvidia,function = "spi6"; 567 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 568 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 569 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 570 + }; 571 + dap3_fs_pp0 { 572 + nvidia,pins = "dap3_fs_pp0", 573 + "dap3_din_pp1", 574 + "dap3_dout_pp2", 575 + "dap3_sclk_pp3"; 576 + nvidia,function = "i2s2"; 577 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 578 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 579 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 580 + }; 581 + pv0 { 582 + nvidia,pins = "pv0"; 583 + nvidia,function = "rsvd4"; 584 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 585 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 586 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 587 + }; 588 + pv1 { 589 + nvidia,pins = "pv1"; 590 + nvidia,function = "rsvd1"; 591 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 592 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 593 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 594 + }; 595 + pbb3 { 596 + nvidia,pins = "pbb3", 597 + "pbb5", 598 + "pbb6", 599 + "pbb7"; 600 + nvidia,function = "rsvd4"; 601 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 602 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 603 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 604 + }; 605 + pcc1 { 606 + nvidia,pins = "pcc1", 607 + "pcc2"; 608 + nvidia,function = "rsvd4"; 609 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 610 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 611 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 612 + }; 613 + gmi_ad0_pg0 { 614 + nvidia,pins = "gmi_ad0_pg0", 615 + "gmi_ad1_pg1"; 616 + nvidia,function = "gmi"; 617 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 618 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 619 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 620 + }; 621 + gmi_ad10_ph2 { 622 + nvidia,pins = "gmi_ad10_ph2", 623 + "gmi_ad12_ph4", 624 + "gmi_ad15_ph7", 625 + "gmi_cs3_n_pk4"; 626 + nvidia,function = "gmi"; 627 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 628 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 629 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 630 + }; 631 + gmi_ad11_ph3 { 632 + nvidia,pins = "gmi_ad11_ph3", 633 + "gmi_ad13_ph5", 634 + "gmi_ad8_ph0", 635 + "gmi_clk_pk1", 636 + "gmi_cs2_n_pk3"; 637 + nvidia,function = "gmi"; 638 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 639 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 640 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 641 + }; 642 + gmi_ad14_ph6 { 643 + nvidia,pins = "gmi_ad14_ph6", 644 + "gmi_cs0_n_pj0", 645 + "gmi_cs4_n_pk2", 646 + "gmi_cs7_n_pi6", 647 + "gmi_dqs_p_pj3", 648 + "gmi_wp_n_pc7"; 649 + nvidia,function = "gmi"; 650 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 651 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 652 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 653 + }; 654 + gmi_ad2_pg2 { 655 + nvidia,pins = "gmi_ad2_pg2", 656 + "gmi_ad3_pg3"; 657 + nvidia,function = "gmi"; 658 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 659 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 660 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 661 + }; 662 + sdmmc1_wp_n_pv3 { 663 + nvidia,pins = "sdmmc1_wp_n_pv3"; 664 + nvidia,function = "spi4"; 665 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 666 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 667 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 668 + }; 669 + clk2_req_pcc5 { 670 + nvidia,pins = "clk2_req_pcc5"; 671 + nvidia,function = "rsvd4"; 672 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 673 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 674 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 675 + }; 676 + kb_col3_pq3 { 677 + nvidia,pins = "kb_col3_pq3"; 678 + nvidia,function = "pwm2"; 679 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 680 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 681 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 682 + }; 683 + kb_col5_pq5 { 684 + nvidia,pins = "kb_col5_pq5"; 685 + nvidia,function = "kbc"; 686 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 687 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 688 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 689 + }; 690 + kb_col6_pq6 { 691 + nvidia,pins = "kb_col6_pq6", 692 + "kb_col7_pq7"; 693 + nvidia,function = "kbc"; 694 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 695 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 696 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 697 + }; 698 + kb_row3_pr3 { 699 + nvidia,pins = "kb_row3_pr3", 700 + "kb_row4_pr4", 701 + "kb_row6_pr6"; 702 + nvidia,function = "kbc"; 703 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 704 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 705 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 706 + }; 707 + clk3_req_pee1 { 708 + nvidia,pins = "clk3_req_pee1"; 709 + nvidia,function = "rsvd4"; 710 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 712 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 713 + }; 714 + pu2 { 715 + nvidia,pins = "pu2"; 716 + nvidia,function = "rsvd1"; 717 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 718 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 719 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 720 + }; 721 + hdmi_int_pn7 { 722 + nvidia,pins = "hdmi_int_pn7"; 723 + nvidia,function = "rsvd1"; 724 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 725 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 726 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 727 + }; 728 + 729 + drive_sdio1 { 730 + nvidia,pins = "drive_sdio1"; 731 + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 732 + nvidia,schmitt = <TEGRA_PIN_DISABLE>; 733 + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 734 + nvidia,pull-down-strength = <36>; 735 + nvidia,pull-up-strength = <20>; 736 + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 737 + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 738 + }; 739 + drive_sdio3 { 740 + nvidia,pins = "drive_sdio3"; 741 + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 742 + nvidia,schmitt = <TEGRA_PIN_DISABLE>; 743 + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 744 + nvidia,pull-down-strength = <36>; 745 + nvidia,pull-up-strength = <20>; 746 + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 747 + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 748 + }; 749 + drive_gma { 750 + nvidia,pins = "drive_gma"; 751 + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 752 + nvidia,schmitt = <TEGRA_PIN_DISABLE>; 753 + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 754 + nvidia,pull-down-strength = <2>; 755 + nvidia,pull-up-strength = <2>; 756 + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 757 + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 758 + nvidia,drive-type = <1>; 759 + }; 760 + }; 761 + }; 762 + 763 + /* Usable on reworked devices only */ 764 + serial@70006300 { 765 + status = "okay"; 766 + }; 767 + 768 + pwm@7000a000 { 769 + status = "okay"; 770 + }; 771 + 772 + i2c@7000d000 { 773 + status = "okay"; 774 + clock-frequency = <400000>; 775 + 776 + regulator@43 { 777 + compatible = "ti,tps51632"; 778 + reg = <0x43>; 779 + regulator-name = "vdd-cpu"; 780 + regulator-min-microvolt = <500000>; 781 + regulator-max-microvolt = <1520000>; 782 + regulator-always-on; 783 + regulator-boot-on; 784 + }; 785 + 786 + palmas: pmic@58 { 787 + compatible = "ti,palmas"; 788 + reg = <0x58>; 789 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 790 + 791 + #interrupt-cells = <2>; 792 + interrupt-controller; 793 + 794 + ti,system-power-controller; 795 + 796 + palmas_gpio: gpio { 797 + compatible = "ti,palmas-gpio"; 798 + gpio-controller; 799 + #gpio-cells = <2>; 800 + }; 801 + 802 + pmic { 803 + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 804 + 805 + regulators { 806 + smps12 { 807 + regulator-name = "vdd-ddr"; 808 + regulator-min-microvolt = <1200000>; 809 + regulator-max-microvolt = <1500000>; 810 + regulator-always-on; 811 + regulator-boot-on; 812 + }; 813 + 814 + vdd_1v8: smps3 { 815 + regulator-name = "vdd-1v8"; 816 + regulator-min-microvolt = <1800000>; 817 + regulator-max-microvolt = <1800000>; 818 + regulator-always-on; 819 + regulator-boot-on; 820 + }; 821 + 822 + smps457 { 823 + regulator-name = "vdd-soc"; 824 + regulator-min-microvolt = <900000>; 825 + regulator-max-microvolt = <1400000>; 826 + regulator-always-on; 827 + regulator-boot-on; 828 + }; 829 + 830 + smps8 { 831 + regulator-name = "avdd-pll-1v05"; 832 + regulator-min-microvolt = <1050000>; 833 + regulator-max-microvolt = <1050000>; 834 + regulator-always-on; 835 + regulator-boot-on; 836 + }; 837 + 838 + smps9 { 839 + regulator-name = "vdd-2v85-emmc"; 840 + regulator-min-microvolt = <2800000>; 841 + regulator-max-microvolt = <2800000>; 842 + regulator-always-on; 843 + }; 844 + 845 + smps10_out1 { 846 + regulator-name = "vdd-fan"; 847 + regulator-min-microvolt = <5000000>; 848 + regulator-max-microvolt = <5000000>; 849 + regulator-always-on; 850 + regulator-boot-on; 851 + }; 852 + 853 + smps10_out2 { 854 + regulator-name = "vdd-5v0-sys"; 855 + regulator-min-microvolt = <5000000>; 856 + regulator-max-microvolt = <5000000>; 857 + regulator-always-on; 858 + regulator-boot-on; 859 + }; 860 + 861 + ldo2 { 862 + regulator-name = "vdd-2v8-display"; 863 + regulator-min-microvolt = <2800000>; 864 + regulator-max-microvolt = <2800000>; 865 + regulator-boot-on; 866 + }; 867 + 868 + ldo3 { 869 + regulator-name = "avdd-1v2"; 870 + regulator-min-microvolt = <1200000>; 871 + regulator-max-microvolt = <1200000>; 872 + regulator-always-on; 873 + regulator-boot-on; 874 + }; 875 + 876 + ldo4 { 877 + regulator-name = "vpp-fuse"; 878 + regulator-min-microvolt = <1800000>; 879 + regulator-max-microvolt = <1800000>; 880 + }; 881 + 882 + ldo5 { 883 + regulator-name = "avdd-hdmi-pll"; 884 + regulator-min-microvolt = <1200000>; 885 + regulator-max-microvolt = <1200000>; 886 + }; 887 + 888 + ldo6 { 889 + regulator-name = "vdd-sensor-2v8"; 890 + regulator-min-microvolt = <2850000>; 891 + regulator-max-microvolt = <2850000>; 892 + }; 893 + 894 + ldo8 { 895 + regulator-name = "vdd-rtc"; 896 + regulator-min-microvolt = <1100000>; 897 + regulator-max-microvolt = <1100000>; 898 + regulator-always-on; 899 + regulator-boot-on; 900 + ti,enable-ldo8-tracking; 901 + }; 902 + 903 + vddio_sdmmc3: ldo9 { 904 + regulator-name = "vddio-sdmmc3"; 905 + regulator-min-microvolt = <1800000>; 906 + regulator-max-microvolt = <3300000>; 907 + regulator-always-on; 908 + regulator-boot-on; 909 + }; 910 + 911 + ldousb { 912 + regulator-name = "avdd-usb-hdmi"; 913 + regulator-min-microvolt = <3300000>; 914 + regulator-max-microvolt = <3300000>; 915 + regulator-always-on; 916 + regulator-boot-on; 917 + }; 918 + 919 + vdd_3v3_sys: regen1 { 920 + regulator-name = "rail-3v3"; 921 + regulator-max-microvolt = <3300000>; 922 + regulator-always-on; 923 + regulator-boot-on; 924 + }; 925 + 926 + regen2 { 927 + regulator-name = "rail-5v0"; 928 + regulator-max-microvolt = <5000000>; 929 + regulator-always-on; 930 + regulator-boot-on; 931 + }; 932 + 933 + }; 934 + }; 935 + 936 + rtc { 937 + compatible = "ti,palmas-rtc"; 938 + interrupt-parent = <&palmas>; 939 + interrupts = <8 0>; 940 + }; 941 + 942 + }; 943 + }; 944 + 945 + pmc@7000e400 { 946 + nvidia,invert-interrupt; 947 + }; 948 + 949 + /* SD card */ 950 + sdhci@78000400 { 951 + status = "okay"; 952 + bus-width = <4>; 953 + vmmc-supply = <&vddio_sdmmc3>; 954 + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 955 + power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 956 + }; 957 + 958 + /* eMMC */ 959 + sdhci@78000600 { 960 + status = "okay"; 961 + bus-width = <8>; 962 + vmmc-supply = <&vdd_1v8>; 963 + non-removable; 964 + }; 965 + 966 + /* External USB port (must be powered) */ 967 + usb@7d000000 { 968 + status = "okay"; 969 + }; 970 + 971 + usb-phy@7d000000 { 972 + status = "okay"; 973 + nvidia,xcvr-setup = <7>; 974 + nvidia,xcvr-lsfslew = <2>; 975 + nvidia,xcvr-lsrslew = <2>; 976 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 977 + /* Should be changed to "otg" once we have vbus_supply */ 978 + /* As of now, USB devices need to be powered externally */ 979 + dr_mode = "host"; 980 + }; 981 + 982 + /* SHIELD controller */ 983 + usb@7d008000 { 984 + status = "okay"; 985 + }; 986 + 987 + usb-phy@7d008000 { 988 + status = "okay"; 989 + nvidia,xcvr-setup = <7>; 990 + nvidia,xcvr-lsfslew = <2>; 991 + nvidia,xcvr-lsrslew = <2>; 992 + }; 993 + 994 + backlight: backlight { 995 + compatible = "pwm-backlight"; 996 + pwms = <&pwm 1 40000>; 997 + 998 + brightness-levels = <0 4 8 16 32 64 128 255>; 999 + default-brightness-level = <6>; 1000 + 1001 + power-supply = <&lcd_bl_en>; 1002 + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1003 + }; 1004 + 1005 + clocks { 1006 + compatible = "simple-bus"; 1007 + #address-cells = <1>; 1008 + #size-cells = <0>; 1009 + 1010 + clk32k_in: clock { 1011 + compatible = "fixed-clock"; 1012 + reg=<0>; 1013 + #clock-cells = <0>; 1014 + clock-frequency = <32768>; 1015 + }; 1016 + }; 1017 + 1018 + gpio-keys { 1019 + compatible = "gpio-keys"; 1020 + 1021 + back { 1022 + label = "Back"; 1023 + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1024 + linux,code = <KEY_BACK>; 1025 + }; 1026 + 1027 + home { 1028 + label = "Home"; 1029 + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1030 + linux,code = <KEY_HOME>; 1031 + }; 1032 + 1033 + power { 1034 + label = "Power"; 1035 + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1036 + linux,code = <KEY_POWER>; 1037 + gpio-key,wakeup; 1038 + }; 1039 + }; 1040 + 1041 + regulators { 1042 + compatible = "simple-bus"; 1043 + #address-cells = <1>; 1044 + #size-cells = <0>; 1045 + 1046 + lcd_bl_en: regulator@0 { 1047 + compatible = "regulator-fixed"; 1048 + reg = <0>; 1049 + regulator-name = "lcd_bl_en"; 1050 + regulator-min-microvolt = <5000000>; 1051 + regulator-max-microvolt = <5000000>; 1052 + regulator-boot-on; 1053 + }; 1054 + 1055 + regulator@1 { 1056 + compatible = "regulator-fixed"; 1057 + reg = <1>; 1058 + regulator-name = "vdd_lcd_1v8"; 1059 + regulator-min-microvolt = <1800000>; 1060 + regulator-max-microvolt = <1800000>; 1061 + vin-supply = <&vdd_1v8>; 1062 + enable-active-high; 1063 + gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 1064 + regulator-boot-on; 1065 + }; 1066 + 1067 + regulator@2 { 1068 + compatible = "regulator-fixed"; 1069 + reg = <2>; 1070 + regulator-name = "vdd_1v8_ts"; 1071 + regulator-min-microvolt = <1800000>; 1072 + regulator-max-microvolt = <1800000>; 1073 + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; 1074 + regulator-boot-on; 1075 + }; 1076 + 1077 + regulator@3 { 1078 + compatible = "regulator-fixed"; 1079 + reg = <3>; 1080 + regulator-name = "vdd_3v3_ts"; 1081 + regulator-min-microvolt = <3300000>; 1082 + regulator-max-microvolt = <3300000>; 1083 + enable-active-high; 1084 + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; 1085 + regulator-boot-on; 1086 + }; 1087 + 1088 + regulator@4 { 1089 + compatible = "regulator-fixed"; 1090 + reg = <4>; 1091 + regulator-name = "vdd_1v8_com"; 1092 + regulator-min-microvolt = <1800000>; 1093 + regulator-max-microvolt = <1800000>; 1094 + vin-supply = <&vdd_1v8>; 1095 + enable-active-high; 1096 + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 1097 + regulator-boot-on; 1098 + }; 1099 + 1100 + regulator@5 { 1101 + compatible = "regulator-fixed"; 1102 + reg = <5>; 1103 + regulator-name = "vdd_3v3_com"; 1104 + regulator-min-microvolt = <3300000>; 1105 + regulator-max-microvolt = <3300000>; 1106 + vin-supply = <&vdd_3v3_sys>; 1107 + enable-active-high; 1108 + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; 1109 + regulator-always-on; 1110 + regulator-boot-on; 1111 + }; 1112 + }; 1113 + };
+348
arch/arm/boot/dts/tegra114-tn7.dts
··· 1 + /dts-v1/; 2 + 3 + #include <dt-bindings/input/input.h> 4 + #include "tegra114.dtsi" 5 + 6 + / { 7 + model = "Tegra Note 7"; 8 + compatible = "nvidia,tn7", "nvidia,tegra114"; 9 + 10 + chosen { 11 + /* TN7's bootloader's arguments need to be overridden */ 12 + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; 13 + /* TN7's bootloader will place initrd at this address */ 14 + linux,initrd-start = <0x82000000>; 15 + linux,initrd-end = <0x82800000>; 16 + }; 17 + 18 + firmware { 19 + trusted-foundations { 20 + compatible = "tlm,trusted-foundations"; 21 + tlm,version-major = <2>; 22 + tlm,version-minor = <8>; 23 + }; 24 + }; 25 + 26 + memory { 27 + /* memory >= 0x37e00000 is reserved for firmware usage */ 28 + reg = <0x80000000 0x37e00000>; 29 + }; 30 + 31 + host1x@50000000 { 32 + dsi@54300000 { 33 + status = "okay"; 34 + 35 + vdd-supply = <&vdd_1v2_ap>; 36 + 37 + panel@0 { 38 + compatible = "lg,ld070wx3-sl01"; 39 + reg = <0>; 40 + 41 + power-supply = <&vdd_lcd>; 42 + backlight = <&backlight>; 43 + }; 44 + }; 45 + }; 46 + 47 + serial@70006300 { 48 + status = "okay"; 49 + }; 50 + 51 + pwm@7000a000 { 52 + status = "okay"; 53 + }; 54 + 55 + i2c@7000d000 { 56 + status = "okay"; 57 + clock-frequency = <400000>; 58 + 59 + palmas: pmic@58 { 60 + compatible = "ti,palmas"; 61 + reg = <0x58>; 62 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 63 + 64 + #interrupt-cells = <2>; 65 + interrupt-controller; 66 + 67 + ti,system-power-controller; 68 + 69 + palmas_gpio: gpio { 70 + compatible = "ti,palmas-gpio"; 71 + gpio-controller; 72 + #gpio-cells = <2>; 73 + }; 74 + 75 + pmic { 76 + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 77 + 78 + ldoln-in-supply = <&vdd_smps10_out2>; 79 + 80 + regulators { 81 + smps123 { 82 + regulator-name = "vd-cpu"; 83 + regulator-min-microvolt = <1000000>; 84 + regulator-max-microvolt = <1000000>; 85 + regulator-always-on; 86 + regulator-boot-on; 87 + }; 88 + 89 + smps45 { 90 + regulator-name = "vd-soc"; 91 + regulator-min-microvolt = <1100000>; 92 + regulator-max-microvolt = <1100000>; 93 + regulator-always-on; 94 + regulator-boot-on; 95 + }; 96 + 97 + smps6 { 98 + regulator-name = "va-lcd-hv"; 99 + regulator-min-microvolt = <3000000>; 100 + regulator-max-microvolt = <3000000>; 101 + regulator-always-on; 102 + regulator-boot-on; 103 + }; 104 + 105 + smps7 { 106 + regulator-name = "vd-ddr"; 107 + regulator-min-microvolt = <1350000>; 108 + regulator-max-microvolt = <1350000>; 109 + regulator-always-on; 110 + regulator-boot-on; 111 + }; 112 + 113 + vdd_1v8: smps8 { 114 + regulator-name = "vs-pmu-1v8"; 115 + regulator-min-microvolt = <1800000>; 116 + regulator-max-microvolt = <1800000>; 117 + regulator-always-on; 118 + regulator-boot-on; 119 + }; 120 + 121 + vdd_2v9_sys: smps9 { 122 + regulator-name = "vs-sys-2v9"; 123 + regulator-min-microvolt = <2900000>; 124 + regulator-max-microvolt = <2900000>; 125 + regulator-always-on; 126 + regulator-boot-on; 127 + }; 128 + 129 + vdd_smps10_out1: smps10_out1 { 130 + regulator-name = "vd-smps10-out1"; 131 + regulator-min-microvolt = <5000000>; 132 + regulator-max-microvolt = <5000000>; 133 + regulator-always-on; 134 + regulator-boot-on; 135 + }; 136 + 137 + vdd_smps10_out2: smps10_out2 { 138 + regulator-name = "vd-smps10-out2"; 139 + regulator-min-microvolt = <5000000>; 140 + regulator-max-microvolt = <5000000>; 141 + regulator-always-on; 142 + regulator-boot-on; 143 + }; 144 + 145 + ldo1 { 146 + regulator-name = "va-pllx"; 147 + regulator-min-microvolt = <1050000>; 148 + regulator-max-microvolt = <1050000>; 149 + regulator-always-on; 150 + regulator-boot-on; 151 + }; 152 + 153 + vdd_1v2_ap: ldo2 { 154 + regulator-name = "va-ap-1v2"; 155 + regulator-min-microvolt = <1200000>; 156 + regulator-max-microvolt = <1200000>; 157 + regulator-always-on; 158 + regulator-boot-on; 159 + }; 160 + 161 + ldo3 { 162 + regulator-name = "vd-fuse"; 163 + regulator-min-microvolt = <1800000>; 164 + regulator-max-microvolt = <1800000>; 165 + regulator-always-on; 166 + regulator-boot-on; 167 + }; 168 + 169 + ldo4 { 170 + regulator-name = "vd-ts-hv"; 171 + regulator-min-microvolt = <3200000>; 172 + regulator-max-microvolt = <3200000>; 173 + regulator-always-on; 174 + regulator-boot-on; 175 + }; 176 + 177 + ldo5 { 178 + regulator-name = "va-cam2-hv"; 179 + regulator-min-microvolt = <2700000>; 180 + regulator-max-microvolt = <2700000>; 181 + }; 182 + 183 + ldo6 { 184 + regulator-name = "va-sns-hv"; 185 + regulator-min-microvolt = <2850000>; 186 + regulator-max-microvolt = <2850000>; 187 + }; 188 + 189 + ldo7 { 190 + regulator-name = "va-cam1-hv"; 191 + regulator-min-microvolt = <2700000>; 192 + regulator-max-microvolt = <2700000>; 193 + }; 194 + 195 + ldo8 { 196 + regulator-name = "va-ap-rtc"; 197 + regulator-min-microvolt = <1100000>; 198 + regulator-max-microvolt = <1100000>; 199 + ti,enable-ldo8-tracking; 200 + regulator-always-on; 201 + regulator-boot-on; 202 + }; 203 + 204 + ldo9 { 205 + regulator-name = "vi-sdcard"; 206 + regulator-min-microvolt = <2900000>; 207 + regulator-max-microvolt = <2900000>; 208 + }; 209 + 210 + ldousb { 211 + regulator-name = "avdd-usb"; 212 + regulator-min-microvolt = <3300000>; 213 + regulator-max-microvolt = <3300000>; 214 + regulator-always-on; 215 + regulator-boot-on; 216 + }; 217 + 218 + ldoln { 219 + regulator-name = "va-hdmi"; 220 + regulator-min-microvolt = <3300000>; 221 + regulator-max-microvolt = <3300000>; 222 + }; 223 + }; 224 + }; 225 + 226 + rtc { 227 + compatible = "ti,palmas-rtc"; 228 + interrupt-parent = <&palmas>; 229 + interrupts = <8 0>; 230 + }; 231 + 232 + }; 233 + }; 234 + 235 + pmc@7000e400 { 236 + nvidia,invert-interrupt; 237 + }; 238 + 239 + /* eMMC */ 240 + sdhci@78000600 { 241 + status = "okay"; 242 + bus-width = <8>; 243 + vmmc-supply = <&vdd_1v8>; 244 + non-removable; 245 + }; 246 + 247 + usb@7d000000 { 248 + status = "okay"; 249 + }; 250 + 251 + usb-phy@7d000000 { 252 + status = "okay"; 253 + nvidia,xcvr-setup = <7>; 254 + nvidia,xcvr-lsfslew = <2>; 255 + nvidia,xcvr-lsrslew = <2>; 256 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 257 + /* Should be changed to "otg" once we have vbus_supply */ 258 + /* As of now, USB devices need to be powered externally */ 259 + dr_mode = "host"; 260 + }; 261 + 262 + backlight: backlight { 263 + compatible = "pwm-backlight"; 264 + pwms = <&pwm 1 40000>; 265 + 266 + brightness-levels = <0 4 8 16 32 64 128 255>; 267 + default-brightness-level = <6>; 268 + 269 + power-supply = <&lcd_bl_en>; 270 + }; 271 + 272 + clocks { 273 + compatible = "simple-bus"; 274 + #address-cells = <1>; 275 + #size-cells = <0>; 276 + 277 + clk32k_in: clock { 278 + compatible = "fixed-clock"; 279 + reg = <0>; 280 + #clock-cells = <0>; 281 + clock-frequency = <32768>; 282 + }; 283 + }; 284 + 285 + gpio-keys { 286 + compatible = "gpio-keys"; 287 + 288 + power { 289 + label = "Power"; 290 + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 291 + linux,code = <KEY_POWER>; 292 + gpio-key,wakeup; 293 + }; 294 + 295 + volume_down { 296 + label = "Volume Down"; 297 + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 298 + linux,code = <KEY_VOLUMEDOWN>; 299 + }; 300 + 301 + volume_up { 302 + label = "Volume Up"; 303 + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 304 + linux,code = <KEY_VOLUMEUP>; 305 + }; 306 + }; 307 + 308 + regulators { 309 + compatible = "simple-bus"; 310 + #address-cells = <1>; 311 + #size-cells = <0>; 312 + 313 + /* FIXME: output of BQ24192 */ 314 + vs_sys: regulator@0 { 315 + compatible = "regulator-fixed"; 316 + reg = <0>; 317 + regulator-name = "VS_SYS"; 318 + regulator-min-microvolt = <4200000>; 319 + regulator-max-microvolt = <4200000>; 320 + regulator-always-on; 321 + regulator-boot-on; 322 + }; 323 + 324 + lcd_bl_en: regulator@1 { 325 + compatible = "regulator-fixed"; 326 + reg = <1>; 327 + regulator-name = "VDD_LCD_BL"; 328 + regulator-min-microvolt = <16500000>; 329 + regulator-max-microvolt = <16500000>; 330 + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 331 + enable-active-high; 332 + vin-supply = <&vs_sys>; 333 + regulator-boot-on; 334 + }; 335 + 336 + vdd_lcd: regulator@2 { 337 + compatible = "regulator-fixed"; 338 + reg = <2>; 339 + regulator-name = "VD_LCD_1V8"; 340 + regulator-min-microvolt = <1800000>; 341 + regulator-max-microvolt = <1800000>; 342 + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; 343 + enable-active-high; 344 + vin-supply = <&vdd_1v8>; 345 + regulator-boot-on; 346 + }; 347 + }; 348 + };
+1827
arch/arm/boot/dts/tegra124-jetson-tk1.dts
··· 1 + /dts-v1/; 2 + 3 + #include <dt-bindings/input/input.h> 4 + #include "tegra124.dtsi" 5 + 6 + / { 7 + model = "NVIDIA Tegra124 Jetson TK1"; 8 + compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; 9 + 10 + aliases { 11 + rtc0 = "/i2c@0,7000d000/pmic@40"; 12 + rtc1 = "/rtc@0,7000e000"; 13 + }; 14 + 15 + memory { 16 + reg = <0x0 0x80000000 0x0 0x80000000>; 17 + }; 18 + 19 + host1x@0,50000000 { 20 + hdmi@0,54280000 { 21 + status = "okay"; 22 + 23 + hdmi-supply = <&vdd_5v0_hdmi>; 24 + pll-supply = <&vdd_hdmi_pll>; 25 + vdd-supply = <&vdd_3v3_hdmi>; 26 + 27 + nvidia,ddc-i2c-bus = <&hdmi_ddc>; 28 + nvidia,hpd-gpio = 29 + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 30 + }; 31 + }; 32 + 33 + pinmux: pinmux@0,70000868 { 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&state_default>; 36 + 37 + state_default: pinmux { 38 + clk_32k_out_pa0 { 39 + nvidia,pins = "clk_32k_out_pa0"; 40 + nvidia,function = "soc"; 41 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 42 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 43 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 44 + }; 45 + uart3_cts_n_pa1 { 46 + nvidia,pins = "uart3_cts_n_pa1"; 47 + nvidia,function = "uartc"; 48 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 49 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 50 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 51 + }; 52 + dap2_fs_pa2 { 53 + nvidia,pins = "dap2_fs_pa2"; 54 + nvidia,function = "i2s1"; 55 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 56 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 57 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 58 + }; 59 + dap2_sclk_pa3 { 60 + nvidia,pins = "dap2_sclk_pa3"; 61 + nvidia,function = "i2s1"; 62 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 63 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 64 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 65 + }; 66 + dap2_din_pa4 { 67 + nvidia,pins = "dap2_din_pa4"; 68 + nvidia,function = "i2s1"; 69 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 70 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 71 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 72 + }; 73 + dap2_dout_pa5 { 74 + nvidia,pins = "dap2_dout_pa5"; 75 + nvidia,function = "i2s1"; 76 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 77 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 78 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 79 + }; 80 + sdmmc3_clk_pa6 { 81 + nvidia,pins = "sdmmc3_clk_pa6"; 82 + nvidia,function = "sdmmc3"; 83 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 84 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 85 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 86 + }; 87 + sdmmc3_cmd_pa7 { 88 + nvidia,pins = "sdmmc3_cmd_pa7"; 89 + nvidia,function = "sdmmc3"; 90 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 91 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 92 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 93 + }; 94 + pb0 { 95 + nvidia,pins = "pb0"; 96 + nvidia,function = "uartd"; 97 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 98 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 99 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 100 + }; 101 + pb1 { 102 + nvidia,pins = "pb1"; 103 + nvidia,function = "uartd"; 104 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 105 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 106 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 107 + }; 108 + sdmmc3_dat3_pb4 { 109 + nvidia,pins = "sdmmc3_dat3_pb4"; 110 + nvidia,function = "sdmmc3"; 111 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 112 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 113 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 114 + }; 115 + sdmmc3_dat2_pb5 { 116 + nvidia,pins = "sdmmc3_dat2_pb5"; 117 + nvidia,function = "sdmmc3"; 118 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 119 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 120 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 121 + }; 122 + sdmmc3_dat1_pb6 { 123 + nvidia,pins = "sdmmc3_dat1_pb6"; 124 + nvidia,function = "sdmmc3"; 125 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 126 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 127 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 128 + }; 129 + sdmmc3_dat0_pb7 { 130 + nvidia,pins = "sdmmc3_dat0_pb7"; 131 + nvidia,function = "sdmmc3"; 132 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 133 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 134 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 135 + }; 136 + uart3_rts_n_pc0 { 137 + nvidia,pins = "uart3_rts_n_pc0"; 138 + nvidia,function = "uartc"; 139 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 141 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 142 + }; 143 + uart2_txd_pc2 { 144 + nvidia,pins = "uart2_txd_pc2"; 145 + nvidia,function = "irda"; 146 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 147 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 148 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 149 + }; 150 + uart2_rxd_pc3 { 151 + nvidia,pins = "uart2_rxd_pc3"; 152 + nvidia,function = "irda"; 153 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 154 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 155 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 156 + }; 157 + gen1_i2c_scl_pc4 { 158 + nvidia,pins = "gen1_i2c_scl_pc4"; 159 + nvidia,function = "i2c1"; 160 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 162 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 163 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 164 + }; 165 + gen1_i2c_sda_pc5 { 166 + nvidia,pins = "gen1_i2c_sda_pc5"; 167 + nvidia,function = "i2c1"; 168 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 169 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 170 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 171 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 172 + }; 173 + pc7 { 174 + nvidia,pins = "pc7"; 175 + nvidia,function = "rsvd1"; 176 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 177 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 178 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 179 + }; 180 + pg0 { 181 + nvidia,pins = "pg0"; 182 + nvidia,function = "rsvd1"; 183 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 184 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 185 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 186 + }; 187 + pg1 { 188 + nvidia,pins = "pg1"; 189 + nvidia,function = "rsvd1"; 190 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 191 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 192 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 193 + }; 194 + pg2 { 195 + nvidia,pins = "pg2"; 196 + nvidia,function = "rsvd1"; 197 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 198 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 199 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 200 + }; 201 + pg3 { 202 + nvidia,pins = "pg3"; 203 + nvidia,function = "rsvd1"; 204 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 205 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 206 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 207 + }; 208 + pg4 { 209 + nvidia,pins = "pg4"; 210 + nvidia,function = "spi4"; 211 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 212 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 213 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 214 + }; 215 + pg5 { 216 + nvidia,pins = "pg5"; 217 + nvidia,function = "spi4"; 218 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 219 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 220 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 221 + }; 222 + pg6 { 223 + nvidia,pins = "pg6"; 224 + nvidia,function = "spi4"; 225 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 226 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 227 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 228 + }; 229 + pg7 { 230 + nvidia,pins = "pg7"; 231 + nvidia,function = "spi4"; 232 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 233 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 234 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 235 + }; 236 + ph0 { 237 + nvidia,pins = "ph0"; 238 + nvidia,function = "gmi"; 239 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 240 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 241 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 242 + }; 243 + ph1 { 244 + nvidia,pins = "ph1"; 245 + nvidia,function = "pwm1"; 246 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 248 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 249 + }; 250 + ph2 { 251 + nvidia,pins = "ph2"; 252 + nvidia,function = "gmi"; 253 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 254 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 255 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 256 + }; 257 + ph3 { 258 + nvidia,pins = "ph3"; 259 + nvidia,function = "gmi"; 260 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 261 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 262 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 263 + }; 264 + ph4 { 265 + nvidia,pins = "ph4"; 266 + nvidia,function = "rsvd2"; 267 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 268 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 269 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 270 + }; 271 + ph5 { 272 + nvidia,pins = "ph5"; 273 + nvidia,function = "rsvd2"; 274 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 275 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 276 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 277 + }; 278 + ph6 { 279 + nvidia,pins = "ph6"; 280 + nvidia,function = "gmi"; 281 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 282 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 283 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 284 + }; 285 + ph7 { 286 + nvidia,pins = "ph7"; 287 + nvidia,function = "gmi"; 288 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 289 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 290 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 291 + }; 292 + pi0 { 293 + nvidia,pins = "pi0"; 294 + nvidia,function = "rsvd1"; 295 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 296 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 297 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 298 + }; 299 + pi1 { 300 + nvidia,pins = "pi1"; 301 + nvidia,function = "rsvd1"; 302 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 303 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 304 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 305 + }; 306 + pi2 { 307 + nvidia,pins = "pi2"; 308 + nvidia,function = "rsvd4"; 309 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 310 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 311 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 312 + }; 313 + pi3 { 314 + nvidia,pins = "pi3"; 315 + nvidia,function = "spi4"; 316 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 317 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 318 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 319 + }; 320 + pi4 { 321 + nvidia,pins = "pi4"; 322 + nvidia,function = "gmi"; 323 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 324 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 325 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 326 + }; 327 + pi5 { 328 + nvidia,pins = "pi5"; 329 + nvidia,function = "rsvd2"; 330 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 331 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 332 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 333 + }; 334 + pi6 { 335 + nvidia,pins = "pi6"; 336 + nvidia,function = "rsvd1"; 337 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 338 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 339 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 340 + }; 341 + pi7 { 342 + nvidia,pins = "pi7"; 343 + nvidia,function = "rsvd1"; 344 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 345 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 346 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 347 + }; 348 + pj0 { 349 + nvidia,pins = "pj0"; 350 + nvidia,function = "rsvd1"; 351 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 352 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 353 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 354 + }; 355 + pj2 { 356 + nvidia,pins = "pj2"; 357 + nvidia,function = "rsvd1"; 358 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 359 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 360 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 361 + }; 362 + uart2_cts_n_pj5 { 363 + nvidia,pins = "uart2_cts_n_pj5"; 364 + nvidia,function = "uartb"; 365 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 366 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 367 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 368 + }; 369 + uart2_rts_n_pj6 { 370 + nvidia,pins = "uart2_rts_n_pj6"; 371 + nvidia,function = "uartb"; 372 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 373 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 374 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 375 + }; 376 + pj7 { 377 + nvidia,pins = "pj7"; 378 + nvidia,function = "uartd"; 379 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 380 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 381 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 382 + }; 383 + pk0 { 384 + nvidia,pins = "pk0"; 385 + nvidia,function = "soc"; 386 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 387 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 388 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 389 + }; 390 + pk1 { 391 + nvidia,pins = "pk1"; 392 + nvidia,function = "rsvd4"; 393 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 394 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 396 + }; 397 + pk2 { 398 + nvidia,pins = "pk2"; 399 + nvidia,function = "rsvd1"; 400 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 401 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 402 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403 + }; 404 + pk3 { 405 + nvidia,pins = "pk3"; 406 + nvidia,function = "gmi"; 407 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 408 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 409 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 410 + }; 411 + pk4 { 412 + nvidia,pins = "pk4"; 413 + nvidia,function = "rsvd2"; 414 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 416 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 417 + }; 418 + spdif_out_pk5 { 419 + nvidia,pins = "spdif_out_pk5"; 420 + nvidia,function = "rsvd2"; 421 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 423 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 424 + }; 425 + spdif_in_pk6 { 426 + nvidia,pins = "spdif_in_pk6"; 427 + nvidia,function = "rsvd2"; 428 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 429 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 430 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 431 + }; 432 + pk7 { 433 + nvidia,pins = "pk7"; 434 + nvidia,function = "uartd"; 435 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 436 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 437 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 438 + }; 439 + dap1_fs_pn0 { 440 + nvidia,pins = "dap1_fs_pn0"; 441 + nvidia,function = "i2s0"; 442 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 443 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 444 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 445 + }; 446 + dap1_din_pn1 { 447 + nvidia,pins = "dap1_din_pn1"; 448 + nvidia,function = "i2s0"; 449 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 450 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 451 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 452 + }; 453 + dap1_dout_pn2 { 454 + nvidia,pins = "dap1_dout_pn2"; 455 + nvidia,function = "sata"; 456 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 457 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 458 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 459 + }; 460 + dap1_sclk_pn3 { 461 + nvidia,pins = "dap1_sclk_pn3"; 462 + nvidia,function = "i2s0"; 463 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 464 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 465 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 466 + }; 467 + usb_vbus_en0_pn4 { 468 + nvidia,pins = "usb_vbus_en0_pn4"; 469 + nvidia,function = "usb"; 470 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 471 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 472 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 473 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 474 + }; 475 + usb_vbus_en1_pn5 { 476 + nvidia,pins = "usb_vbus_en1_pn5"; 477 + nvidia,function = "usb"; 478 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 479 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 480 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 481 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 482 + }; 483 + hdmi_int_pn7 { 484 + nvidia,pins = "hdmi_int_pn7"; 485 + nvidia,function = "rsvd1"; 486 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 487 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 488 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489 + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 490 + }; 491 + ulpi_data7_po0 { 492 + nvidia,pins = "ulpi_data7_po0"; 493 + nvidia,function = "ulpi"; 494 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 495 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 496 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 497 + }; 498 + ulpi_data0_po1 { 499 + nvidia,pins = "ulpi_data0_po1"; 500 + nvidia,function = "ulpi"; 501 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 502 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 503 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 504 + }; 505 + ulpi_data1_po2 { 506 + nvidia,pins = "ulpi_data1_po2"; 507 + nvidia,function = "ulpi"; 508 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 509 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 510 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 511 + }; 512 + ulpi_data2_po3 { 513 + nvidia,pins = "ulpi_data2_po3"; 514 + nvidia,function = "ulpi"; 515 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 516 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 517 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 518 + }; 519 + ulpi_data3_po4 { 520 + nvidia,pins = "ulpi_data3_po4"; 521 + nvidia,function = "ulpi"; 522 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 523 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 524 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 525 + }; 526 + ulpi_data4_po5 { 527 + nvidia,pins = "ulpi_data4_po5"; 528 + nvidia,function = "ulpi"; 529 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 530 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 531 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 532 + }; 533 + ulpi_data5_po6 { 534 + nvidia,pins = "ulpi_data5_po6"; 535 + nvidia,function = "ulpi"; 536 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 537 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 538 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 539 + }; 540 + ulpi_data6_po7 { 541 + nvidia,pins = "ulpi_data6_po7"; 542 + nvidia,function = "ulpi"; 543 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 544 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 545 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 546 + }; 547 + dap3_fs_pp0 { 548 + nvidia,pins = "dap3_fs_pp0"; 549 + nvidia,function = "i2s2"; 550 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 551 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 552 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 553 + }; 554 + dap3_din_pp1 { 555 + nvidia,pins = "dap3_din_pp1"; 556 + nvidia,function = "i2s2"; 557 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 558 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 559 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 560 + }; 561 + dap3_dout_pp2 { 562 + nvidia,pins = "dap3_dout_pp2"; 563 + nvidia,function = "rsvd4"; 564 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 566 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 567 + }; 568 + dap3_sclk_pp3 { 569 + nvidia,pins = "dap3_sclk_pp3"; 570 + nvidia,function = "rsvd3"; 571 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 572 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 573 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 574 + }; 575 + dap4_fs_pp4 { 576 + nvidia,pins = "dap4_fs_pp4"; 577 + nvidia,function = "i2s3"; 578 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 579 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 580 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 581 + }; 582 + dap4_din_pp5 { 583 + nvidia,pins = "dap4_din_pp5"; 584 + nvidia,function = "i2s3"; 585 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 586 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 587 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 588 + }; 589 + dap4_dout_pp6 { 590 + nvidia,pins = "dap4_dout_pp6"; 591 + nvidia,function = "i2s3"; 592 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 593 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 594 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 595 + }; 596 + dap4_sclk_pp7 { 597 + nvidia,pins = "dap4_sclk_pp7"; 598 + nvidia,function = "i2s3"; 599 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 600 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 601 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 602 + }; 603 + kb_col0_pq0 { 604 + nvidia,pins = "kb_col0_pq0"; 605 + nvidia,function = "rsvd2"; 606 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 607 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 608 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 609 + }; 610 + kb_col1_pq1 { 611 + nvidia,pins = "kb_col1_pq1"; 612 + nvidia,function = "rsvd2"; 613 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 614 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 615 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 616 + }; 617 + kb_col2_pq2 { 618 + nvidia,pins = "kb_col2_pq2"; 619 + nvidia,function = "rsvd2"; 620 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 621 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 622 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 623 + }; 624 + kb_col3_pq3 { 625 + nvidia,pins = "kb_col3_pq3"; 626 + nvidia,function = "kbc"; 627 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 628 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 629 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 630 + }; 631 + kb_col4_pq4 { 632 + nvidia,pins = "kb_col4_pq4"; 633 + nvidia,function = "sdmmc3"; 634 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 635 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 636 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 637 + }; 638 + kb_col5_pq5 { 639 + nvidia,pins = "kb_col5_pq5"; 640 + nvidia,function = "rsvd2"; 641 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 642 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 643 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 644 + }; 645 + kb_col6_pq6 { 646 + nvidia,pins = "kb_col6_pq6"; 647 + nvidia,function = "rsvd2"; 648 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 649 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 650 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 651 + }; 652 + kb_col7_pq7 { 653 + nvidia,pins = "kb_col7_pq7"; 654 + nvidia,function = "rsvd2"; 655 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 656 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 657 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 658 + }; 659 + kb_row0_pr0 { 660 + nvidia,pins = "kb_row0_pr0"; 661 + nvidia,function = "rsvd2"; 662 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 663 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 664 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 665 + }; 666 + kb_row1_pr1 { 667 + nvidia,pins = "kb_row1_pr1"; 668 + nvidia,function = "rsvd2"; 669 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 670 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 671 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 672 + }; 673 + kb_row2_pr2 { 674 + nvidia,pins = "kb_row2_pr2"; 675 + nvidia,function = "rsvd2"; 676 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 678 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 679 + }; 680 + kb_row3_pr3 { 681 + nvidia,pins = "kb_row3_pr3"; 682 + nvidia,function = "sys"; 683 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 684 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 685 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 686 + }; 687 + kb_row4_pr4 { 688 + nvidia,pins = "kb_row4_pr4"; 689 + nvidia,function = "rsvd3"; 690 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 691 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 692 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 693 + }; 694 + kb_row5_pr5 { 695 + nvidia,pins = "kb_row5_pr5"; 696 + nvidia,function = "rsvd3"; 697 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 698 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 699 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 700 + }; 701 + kb_row6_pr6 { 702 + nvidia,pins = "kb_row6_pr6"; 703 + nvidia,function = "displaya_alt"; 704 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 705 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 706 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 707 + }; 708 + kb_row7_pr7 { 709 + nvidia,pins = "kb_row7_pr7"; 710 + nvidia,function = "rsvd2"; 711 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 712 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 713 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 714 + }; 715 + kb_row8_ps0 { 716 + nvidia,pins = "kb_row8_ps0"; 717 + nvidia,function = "rsvd2"; 718 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 719 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 720 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 721 + }; 722 + kb_row9_ps1 { 723 + nvidia,pins = "kb_row9_ps1"; 724 + nvidia,function = "rsvd2"; 725 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 726 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 727 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 728 + }; 729 + kb_row10_ps2 { 730 + nvidia,pins = "kb_row10_ps2"; 731 + nvidia,function = "rsvd2"; 732 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 733 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 734 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 735 + }; 736 + kb_row11_ps3 { 737 + nvidia,pins = "kb_row11_ps3"; 738 + nvidia,function = "rsvd2"; 739 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 741 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742 + }; 743 + kb_row12_ps4 { 744 + nvidia,pins = "kb_row12_ps4"; 745 + nvidia,function = "rsvd2"; 746 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 747 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 748 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 749 + }; 750 + kb_row13_ps5 { 751 + nvidia,pins = "kb_row13_ps5"; 752 + nvidia,function = "rsvd2"; 753 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 754 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 755 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 756 + }; 757 + kb_row14_ps6 { 758 + nvidia,pins = "kb_row14_ps6"; 759 + nvidia,function = "rsvd2"; 760 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 761 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 762 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 763 + }; 764 + kb_row15_ps7 { 765 + nvidia,pins = "kb_row15_ps7"; 766 + nvidia,function = "soc"; 767 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 768 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 769 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 770 + }; 771 + kb_row16_pt0 { 772 + nvidia,pins = "kb_row16_pt0"; 773 + nvidia,function = "rsvd2"; 774 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 775 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 776 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 777 + }; 778 + kb_row17_pt1 { 779 + nvidia,pins = "kb_row17_pt1"; 780 + nvidia,function = "rsvd2"; 781 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 782 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 783 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 784 + }; 785 + gen2_i2c_scl_pt5 { 786 + nvidia,pins = "gen2_i2c_scl_pt5"; 787 + nvidia,function = "i2c2"; 788 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 789 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 790 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 791 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 792 + }; 793 + gen2_i2c_sda_pt6 { 794 + nvidia,pins = "gen2_i2c_sda_pt6"; 795 + nvidia,function = "i2c2"; 796 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 797 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 798 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 799 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 800 + }; 801 + sdmmc4_cmd_pt7 { 802 + nvidia,pins = "sdmmc4_cmd_pt7"; 803 + nvidia,function = "sdmmc4"; 804 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 805 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 806 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 807 + }; 808 + pu0 { 809 + nvidia,pins = "pu0"; 810 + nvidia,function = "rsvd4"; 811 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 812 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 813 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 814 + }; 815 + pu1 { 816 + nvidia,pins = "pu1"; 817 + nvidia,function = "rsvd1"; 818 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 819 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 820 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 821 + }; 822 + pu2 { 823 + nvidia,pins = "pu2"; 824 + nvidia,function = "rsvd1"; 825 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 826 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 827 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 828 + }; 829 + pu3 { 830 + nvidia,pins = "pu3"; 831 + nvidia,function = "gmi"; 832 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 833 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 834 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 835 + }; 836 + pu4 { 837 + nvidia,pins = "pu4"; 838 + nvidia,function = "gmi"; 839 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 840 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 841 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 842 + }; 843 + pu5 { 844 + nvidia,pins = "pu5"; 845 + nvidia,function = "gmi"; 846 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 847 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 848 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 849 + }; 850 + pu6 { 851 + nvidia,pins = "pu6"; 852 + nvidia,function = "rsvd3"; 853 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 854 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 855 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 856 + }; 857 + pv0 { 858 + nvidia,pins = "pv0"; 859 + nvidia,function = "rsvd1"; 860 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 861 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 862 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 863 + }; 864 + pv1 { 865 + nvidia,pins = "pv1"; 866 + nvidia,function = "rsvd1"; 867 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 868 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 869 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 870 + }; 871 + sdmmc3_cd_n_pv2 { 872 + nvidia,pins = "sdmmc3_cd_n_pv2"; 873 + nvidia,function = "sdmmc3"; 874 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 875 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 876 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 877 + }; 878 + sdmmc1_wp_n_pv3 { 879 + nvidia,pins = "sdmmc1_wp_n_pv3"; 880 + nvidia,function = "sdmmc1"; 881 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 882 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 883 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 884 + }; 885 + ddc_scl_pv4 { 886 + nvidia,pins = "ddc_scl_pv4"; 887 + nvidia,function = "i2c4"; 888 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 889 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 890 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 891 + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 892 + }; 893 + ddc_sda_pv5 { 894 + nvidia,pins = "ddc_sda_pv5"; 895 + nvidia,function = "i2c4"; 896 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 897 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 898 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 899 + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 900 + }; 901 + gpio_w2_aud_pw2 { 902 + nvidia,pins = "gpio_w2_aud_pw2"; 903 + nvidia,function = "rsvd2"; 904 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 905 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 906 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 907 + }; 908 + gpio_w3_aud_pw3 { 909 + nvidia,pins = "gpio_w3_aud_pw3"; 910 + nvidia,function = "spi6"; 911 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 912 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 913 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 914 + }; 915 + dap_mclk1_pw4 { 916 + nvidia,pins = "dap_mclk1_pw4"; 917 + nvidia,function = "extperiph1"; 918 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 919 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 920 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 921 + }; 922 + clk2_out_pw5 { 923 + nvidia,pins = "clk2_out_pw5"; 924 + nvidia,function = "extperiph2"; 925 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 926 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 927 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 928 + }; 929 + uart3_txd_pw6 { 930 + nvidia,pins = "uart3_txd_pw6"; 931 + nvidia,function = "uartc"; 932 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 933 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 934 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 935 + }; 936 + uart3_rxd_pw7 { 937 + nvidia,pins = "uart3_rxd_pw7"; 938 + nvidia,function = "uartc"; 939 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 940 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 941 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 942 + }; 943 + dvfs_pwm_px0 { 944 + nvidia,pins = "dvfs_pwm_px0"; 945 + nvidia,function = "cldvfs"; 946 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 947 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 948 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 949 + }; 950 + gpio_x1_aud_px1 { 951 + nvidia,pins = "gpio_x1_aud_px1"; 952 + nvidia,function = "rsvd2"; 953 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 954 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 955 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 956 + }; 957 + dvfs_clk_px2 { 958 + nvidia,pins = "dvfs_clk_px2"; 959 + nvidia,function = "cldvfs"; 960 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 961 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 962 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 963 + }; 964 + gpio_x3_aud_px3 { 965 + nvidia,pins = "gpio_x3_aud_px3"; 966 + nvidia,function = "rsvd4"; 967 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 968 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 969 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 970 + }; 971 + gpio_x4_aud_px4 { 972 + nvidia,pins = "gpio_x4_aud_px4"; 973 + nvidia,function = "gmi"; 974 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 975 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 976 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 977 + }; 978 + gpio_x5_aud_px5 { 979 + nvidia,pins = "gpio_x5_aud_px5"; 980 + nvidia,function = "rsvd4"; 981 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 982 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 983 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 984 + }; 985 + gpio_x6_aud_px6 { 986 + nvidia,pins = "gpio_x6_aud_px6"; 987 + nvidia,function = "gmi"; 988 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 989 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 990 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 991 + }; 992 + gpio_x7_aud_px7 { 993 + nvidia,pins = "gpio_x7_aud_px7"; 994 + nvidia,function = "rsvd1"; 995 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 996 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 997 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 998 + }; 999 + ulpi_clk_py0 { 1000 + nvidia,pins = "ulpi_clk_py0"; 1001 + nvidia,function = "spi1"; 1002 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1003 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1004 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1005 + }; 1006 + ulpi_dir_py1 { 1007 + nvidia,pins = "ulpi_dir_py1"; 1008 + nvidia,function = "spi1"; 1009 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1010 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1011 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1012 + }; 1013 + ulpi_nxt_py2 { 1014 + nvidia,pins = "ulpi_nxt_py2"; 1015 + nvidia,function = "spi1"; 1016 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1017 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1018 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1019 + }; 1020 + ulpi_stp_py3 { 1021 + nvidia,pins = "ulpi_stp_py3"; 1022 + nvidia,function = "spi1"; 1023 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1024 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1025 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1026 + }; 1027 + sdmmc1_dat3_py4 { 1028 + nvidia,pins = "sdmmc1_dat3_py4"; 1029 + nvidia,function = "sdmmc1"; 1030 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1031 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1032 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1033 + }; 1034 + sdmmc1_dat2_py5 { 1035 + nvidia,pins = "sdmmc1_dat2_py5"; 1036 + nvidia,function = "sdmmc1"; 1037 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1038 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1039 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1040 + }; 1041 + sdmmc1_dat1_py6 { 1042 + nvidia,pins = "sdmmc1_dat1_py6"; 1043 + nvidia,function = "sdmmc1"; 1044 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1045 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1046 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1047 + }; 1048 + sdmmc1_dat0_py7 { 1049 + nvidia,pins = "sdmmc1_dat0_py7"; 1050 + nvidia,function = "sdmmc1"; 1051 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1052 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1053 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1054 + }; 1055 + sdmmc1_clk_pz0 { 1056 + nvidia,pins = "sdmmc1_clk_pz0"; 1057 + nvidia,function = "sdmmc1"; 1058 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1059 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1060 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1061 + }; 1062 + sdmmc1_cmd_pz1 { 1063 + nvidia,pins = "sdmmc1_cmd_pz1"; 1064 + nvidia,function = "sdmmc1"; 1065 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1066 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1067 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1068 + }; 1069 + pwr_i2c_scl_pz6 { 1070 + nvidia,pins = "pwr_i2c_scl_pz6"; 1071 + nvidia,function = "i2cpwr"; 1072 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1073 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1074 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1075 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1076 + }; 1077 + pwr_i2c_sda_pz7 { 1078 + nvidia,pins = "pwr_i2c_sda_pz7"; 1079 + nvidia,function = "i2cpwr"; 1080 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1081 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1082 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1083 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1084 + }; 1085 + sdmmc4_dat0_paa0 { 1086 + nvidia,pins = "sdmmc4_dat0_paa0"; 1087 + nvidia,function = "sdmmc4"; 1088 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1089 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1090 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1091 + }; 1092 + sdmmc4_dat1_paa1 { 1093 + nvidia,pins = "sdmmc4_dat1_paa1"; 1094 + nvidia,function = "sdmmc4"; 1095 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1096 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1097 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1098 + }; 1099 + sdmmc4_dat2_paa2 { 1100 + nvidia,pins = "sdmmc4_dat2_paa2"; 1101 + nvidia,function = "sdmmc4"; 1102 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1103 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1104 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1105 + }; 1106 + sdmmc4_dat3_paa3 { 1107 + nvidia,pins = "sdmmc4_dat3_paa3"; 1108 + nvidia,function = "sdmmc4"; 1109 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1110 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1111 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1112 + }; 1113 + sdmmc4_dat4_paa4 { 1114 + nvidia,pins = "sdmmc4_dat4_paa4"; 1115 + nvidia,function = "sdmmc4"; 1116 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1117 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1118 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1119 + }; 1120 + sdmmc4_dat5_paa5 { 1121 + nvidia,pins = "sdmmc4_dat5_paa5"; 1122 + nvidia,function = "sdmmc4"; 1123 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1124 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1125 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1126 + }; 1127 + sdmmc4_dat6_paa6 { 1128 + nvidia,pins = "sdmmc4_dat6_paa6"; 1129 + nvidia,function = "sdmmc4"; 1130 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1131 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1132 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1133 + }; 1134 + sdmmc4_dat7_paa7 { 1135 + nvidia,pins = "sdmmc4_dat7_paa7"; 1136 + nvidia,function = "sdmmc4"; 1137 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1138 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1139 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1140 + }; 1141 + pbb0 { 1142 + nvidia,pins = "pbb0"; 1143 + nvidia,function = "vimclk2_alt"; 1144 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1145 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1146 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1147 + }; 1148 + cam_i2c_scl_pbb1 { 1149 + nvidia,pins = "cam_i2c_scl_pbb1"; 1150 + nvidia,function = "i2c3"; 1151 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1152 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1153 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1154 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1155 + }; 1156 + cam_i2c_sda_pbb2 { 1157 + nvidia,pins = "cam_i2c_sda_pbb2"; 1158 + nvidia,function = "i2c3"; 1159 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1160 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1161 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1162 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1163 + }; 1164 + pbb3 { 1165 + nvidia,pins = "pbb3"; 1166 + nvidia,function = "vgp3"; 1167 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1168 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1169 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1170 + }; 1171 + pbb4 { 1172 + nvidia,pins = "pbb4"; 1173 + nvidia,function = "vgp4"; 1174 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1175 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1176 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1177 + }; 1178 + pbb5 { 1179 + nvidia,pins = "pbb5"; 1180 + nvidia,function = "rsvd3"; 1181 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1182 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1183 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1184 + }; 1185 + pbb6 { 1186 + nvidia,pins = "pbb6"; 1187 + nvidia,function = "rsvd2"; 1188 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1189 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1190 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1191 + }; 1192 + pbb7 { 1193 + nvidia,pins = "pbb7"; 1194 + nvidia,function = "rsvd2"; 1195 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1196 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1197 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1198 + }; 1199 + cam_mclk_pcc0 { 1200 + nvidia,pins = "cam_mclk_pcc0"; 1201 + nvidia,function = "vi_alt3"; 1202 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1203 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1204 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1205 + }; 1206 + pcc1 { 1207 + nvidia,pins = "pcc1"; 1208 + nvidia,function = "rsvd2"; 1209 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1210 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1211 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1212 + }; 1213 + pcc2 { 1214 + nvidia,pins = "pcc2"; 1215 + nvidia,function = "rsvd2"; 1216 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1217 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1218 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1219 + }; 1220 + sdmmc4_clk_pcc4 { 1221 + nvidia,pins = "sdmmc4_clk_pcc4"; 1222 + nvidia,function = "sdmmc4"; 1223 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1224 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1225 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1226 + }; 1227 + clk2_req_pcc5 { 1228 + nvidia,pins = "clk2_req_pcc5"; 1229 + nvidia,function = "rsvd2"; 1230 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1231 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1232 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1233 + }; 1234 + clk3_out_pee0 { 1235 + nvidia,pins = "clk3_out_pee0"; 1236 + nvidia,function = "extperiph3"; 1237 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1238 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1239 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1240 + }; 1241 + clk3_req_pee1 { 1242 + nvidia,pins = "clk3_req_pee1"; 1243 + nvidia,function = "rsvd2"; 1244 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1245 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1246 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1247 + }; 1248 + dap_mclk1_req_pee2 { 1249 + nvidia,pins = "dap_mclk1_req_pee2"; 1250 + nvidia,function = "sata"; 1251 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1252 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1253 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1254 + }; 1255 + hdmi_cec_pee3 { 1256 + nvidia,pins = "hdmi_cec_pee3"; 1257 + nvidia,function = "cec"; 1258 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1259 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1260 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1261 + nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1262 + }; 1263 + sdmmc3_clk_lb_out_pee4 { 1264 + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1265 + nvidia,function = "sdmmc3"; 1266 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1267 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1268 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1269 + }; 1270 + sdmmc3_clk_lb_in_pee5 { 1271 + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 1272 + nvidia,function = "sdmmc3"; 1273 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1274 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1275 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1276 + }; 1277 + dp_hpd_pff0 { 1278 + nvidia,pins = "dp_hpd_pff0"; 1279 + nvidia,function = "dp"; 1280 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1281 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1282 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1283 + }; 1284 + usb_vbus_en2_pff1 { 1285 + nvidia,pins = "usb_vbus_en2_pff1"; 1286 + nvidia,function = "rsvd2"; 1287 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1288 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1289 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1290 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1291 + }; 1292 + pff2 { 1293 + nvidia,pins = "pff2"; 1294 + nvidia,function = "rsvd2"; 1295 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1296 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1297 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1298 + nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1299 + }; 1300 + core_pwr_req { 1301 + nvidia,pins = "core_pwr_req"; 1302 + nvidia,function = "pwron"; 1303 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1304 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1305 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1306 + }; 1307 + cpu_pwr_req { 1308 + nvidia,pins = "cpu_pwr_req"; 1309 + nvidia,function = "rsvd2"; 1310 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1311 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1312 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1313 + }; 1314 + pwr_int_n { 1315 + nvidia,pins = "pwr_int_n"; 1316 + nvidia,function = "pmi"; 1317 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1318 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1319 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1320 + }; 1321 + reset_out_n { 1322 + nvidia,pins = "reset_out_n"; 1323 + nvidia,function = "reset_out_n"; 1324 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1325 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1326 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1327 + }; 1328 + owr { 1329 + nvidia,pins = "owr"; 1330 + nvidia,function = "rsvd2"; 1331 + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1332 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 1333 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1334 + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 1335 + }; 1336 + clk_32k_in { 1337 + nvidia,pins = "clk_32k_in"; 1338 + nvidia,function = "rsvd2"; 1339 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1340 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1341 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1342 + }; 1343 + jtag_rtck { 1344 + nvidia,pins = "jtag_rtck"; 1345 + nvidia,function = "rtck"; 1346 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 1347 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 1348 + nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1349 + }; 1350 + }; 1351 + }; 1352 + 1353 + /* DB9 serial port */ 1354 + serial@0,70006300 { 1355 + status = "okay"; 1356 + }; 1357 + 1358 + /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ 1359 + i2c@0,7000c000 { 1360 + status = "okay"; 1361 + clock-frequency = <100000>; 1362 + 1363 + rt5639: audio-codec@1c { 1364 + compatible = "realtek,rt5639"; 1365 + reg = <0x1c>; 1366 + interrupt-parent = <&gpio>; 1367 + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; 1368 + realtek,ldo1-en-gpios = 1369 + <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; 1370 + }; 1371 + 1372 + temperature-sensor@4c { 1373 + compatible = "ti,tmp451"; 1374 + reg = <0x4c>; 1375 + interrupt-parent = <&gpio>; 1376 + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; 1377 + }; 1378 + 1379 + eeprom@56 { 1380 + compatible = "atmel,24c02"; 1381 + reg = <0x56>; 1382 + pagesize = <8>; 1383 + }; 1384 + }; 1385 + 1386 + /* Expansion GEN2_I2C_* */ 1387 + i2c@0,7000c400 { 1388 + status = "okay"; 1389 + clock-frequency = <100000>; 1390 + }; 1391 + 1392 + /* Expansion CAM_I2C_* */ 1393 + i2c@0,7000c500 { 1394 + status = "okay"; 1395 + clock-frequency = <100000>; 1396 + }; 1397 + 1398 + /* HDMI DDC */ 1399 + hdmi_ddc: i2c@0,7000c700 { 1400 + status = "okay"; 1401 + clock-frequency = <100000>; 1402 + }; 1403 + 1404 + /* Expansion PWR_I2C_*, on-board components */ 1405 + i2c@0,7000d000 { 1406 + status = "okay"; 1407 + clock-frequency = <400000>; 1408 + 1409 + pmic: pmic@40 { 1410 + compatible = "ams,as3722"; 1411 + reg = <0x40>; 1412 + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1413 + 1414 + ams,system-power-controller; 1415 + 1416 + #interrupt-cells = <2>; 1417 + interrupt-controller; 1418 + 1419 + gpio-controller; 1420 + #gpio-cells = <2>; 1421 + 1422 + pinctrl-names = "default"; 1423 + pinctrl-0 = <&as3722_default>; 1424 + 1425 + as3722_default: pinmux { 1426 + gpio0 { 1427 + pins = "gpio0"; 1428 + function = "gpio"; 1429 + bias-pull-down; 1430 + }; 1431 + 1432 + gpio1_2_4_7 { 1433 + pins = "gpio1", "gpio2", "gpio4", "gpio7"; 1434 + function = "gpio"; 1435 + bias-pull-up; 1436 + }; 1437 + 1438 + gpio3_5_6 { 1439 + pins = "gpio3", "gpio5", "gpio6"; 1440 + bias-high-impedance; 1441 + }; 1442 + }; 1443 + 1444 + regulators { 1445 + vsup-sd2-supply = <&vdd_5v0_sys>; 1446 + vsup-sd3-supply = <&vdd_5v0_sys>; 1447 + vsup-sd4-supply = <&vdd_5v0_sys>; 1448 + vsup-sd5-supply = <&vdd_5v0_sys>; 1449 + vin-ldo0-supply = <&vdd_1v35_lp0>; 1450 + vin-ldo1-6-supply = <&vdd_3v3_run>; 1451 + vin-ldo2-5-7-supply = <&vddio_1v8>; 1452 + vin-ldo3-4-supply = <&vdd_3v3_sys>; 1453 + vin-ldo9-10-supply = <&vdd_5v0_sys>; 1454 + vin-ldo11-supply = <&vdd_3v3_run>; 1455 + 1456 + sd0 { 1457 + regulator-name = "+VDD_CPU_AP"; 1458 + regulator-min-microvolt = <700000>; 1459 + regulator-max-microvolt = <1400000>; 1460 + regulator-min-microamp = <3500000>; 1461 + regulator-max-microamp = <3500000>; 1462 + regulator-always-on; 1463 + regulator-boot-on; 1464 + ams,external-control = <2>; 1465 + }; 1466 + 1467 + sd1 { 1468 + regulator-name = "+VDD_CORE"; 1469 + regulator-min-microvolt = <700000>; 1470 + regulator-max-microvolt = <1350000>; 1471 + regulator-min-microamp = <2500000>; 1472 + regulator-max-microamp = <2500000>; 1473 + regulator-always-on; 1474 + regulator-boot-on; 1475 + ams,external-control = <1>; 1476 + }; 1477 + 1478 + vdd_1v35_lp0: sd2 { 1479 + regulator-name = "+1.35V_LP0(sd2)"; 1480 + regulator-min-microvolt = <1350000>; 1481 + regulator-max-microvolt = <1350000>; 1482 + regulator-always-on; 1483 + regulator-boot-on; 1484 + }; 1485 + 1486 + sd3 { 1487 + regulator-name = "+1.35V_LP0(sd3)"; 1488 + regulator-min-microvolt = <1350000>; 1489 + regulator-max-microvolt = <1350000>; 1490 + regulator-always-on; 1491 + regulator-boot-on; 1492 + }; 1493 + 1494 + vdd_1v05_run: sd4 { 1495 + regulator-name = "+1.05V_RUN"; 1496 + regulator-min-microvolt = <1050000>; 1497 + regulator-max-microvolt = <1050000>; 1498 + }; 1499 + 1500 + vddio_1v8: sd5 { 1501 + regulator-name = "+1.8V_VDDIO"; 1502 + regulator-min-microvolt = <1800000>; 1503 + regulator-max-microvolt = <1800000>; 1504 + regulator-boot-on; 1505 + regulator-always-on; 1506 + }; 1507 + 1508 + sd6 { 1509 + regulator-name = "+VDD_GPU_AP"; 1510 + regulator-min-microvolt = <650000>; 1511 + regulator-max-microvolt = <1200000>; 1512 + regulator-min-microamp = <3500000>; 1513 + regulator-max-microamp = <3500000>; 1514 + regulator-boot-on; 1515 + regulator-always-on; 1516 + }; 1517 + 1518 + ldo0 { 1519 + regulator-name = "+1.05V_RUN_AVDD"; 1520 + regulator-min-microvolt = <1050000>; 1521 + regulator-max-microvolt = <1050000>; 1522 + regulator-boot-on; 1523 + regulator-always-on; 1524 + ams,external-control = <1>; 1525 + }; 1526 + 1527 + ldo1 { 1528 + regulator-name = "+1.8V_RUN_CAM"; 1529 + regulator-min-microvolt = <1800000>; 1530 + regulator-max-microvolt = <1800000>; 1531 + }; 1532 + 1533 + ldo2 { 1534 + regulator-name = "+1.2V_GEN_AVDD"; 1535 + regulator-min-microvolt = <1200000>; 1536 + regulator-max-microvolt = <1200000>; 1537 + regulator-boot-on; 1538 + regulator-always-on; 1539 + }; 1540 + 1541 + ldo3 { 1542 + regulator-name = "+1.05V_LP0_VDD_RTC"; 1543 + regulator-min-microvolt = <1000000>; 1544 + regulator-max-microvolt = <1000000>; 1545 + regulator-boot-on; 1546 + regulator-always-on; 1547 + ams,enable-tracking; 1548 + }; 1549 + 1550 + ldo4 { 1551 + regulator-name = "+2.8V_RUN_CAM"; 1552 + regulator-min-microvolt = <2800000>; 1553 + regulator-max-microvolt = <2800000>; 1554 + }; 1555 + 1556 + ldo5 { 1557 + regulator-name = "+1.2V_RUN_CAM_FRONT"; 1558 + regulator-min-microvolt = <1200000>; 1559 + regulator-max-microvolt = <1200000>; 1560 + }; 1561 + 1562 + vddio_sdmmc3: ldo6 { 1563 + regulator-name = "+VDDIO_SDMMC3"; 1564 + regulator-min-microvolt = <1800000>; 1565 + regulator-max-microvolt = <3300000>; 1566 + }; 1567 + 1568 + ldo7 { 1569 + regulator-name = "+1.05V_RUN_CAM_REAR"; 1570 + regulator-min-microvolt = <1050000>; 1571 + regulator-max-microvolt = <1050000>; 1572 + }; 1573 + 1574 + ldo9 { 1575 + regulator-name = "+3.3V_RUN_TOUCH"; 1576 + regulator-min-microvolt = <2800000>; 1577 + regulator-max-microvolt = <2800000>; 1578 + }; 1579 + 1580 + ldo10 { 1581 + regulator-name = "+2.8V_RUN_CAM_AF"; 1582 + regulator-min-microvolt = <2800000>; 1583 + regulator-max-microvolt = <2800000>; 1584 + }; 1585 + 1586 + ldo11 { 1587 + regulator-name = "+1.8V_RUN_VPP_FUSE"; 1588 + regulator-min-microvolt = <1800000>; 1589 + regulator-max-microvolt = <1800000>; 1590 + }; 1591 + }; 1592 + }; 1593 + }; 1594 + 1595 + /* Expansion TS_SPI_* */ 1596 + spi@0,7000d400 { 1597 + status = "okay"; 1598 + }; 1599 + 1600 + /* Internal SPI */ 1601 + spi@0,7000da00 { 1602 + status = "okay"; 1603 + spi-max-frequency = <25000000>; 1604 + spi-flash@0 { 1605 + compatible = "winbond,w25q32dw"; 1606 + reg = <0>; 1607 + spi-max-frequency = <20000000>; 1608 + }; 1609 + }; 1610 + 1611 + pmc@0,7000e400 { 1612 + nvidia,invert-interrupt; 1613 + nvidia,suspend-mode = <1>; 1614 + nvidia,cpu-pwr-good-time = <500>; 1615 + nvidia,cpu-pwr-off-time = <300>; 1616 + nvidia,core-pwr-good-time = <641 3845>; 1617 + nvidia,core-pwr-off-time = <61036>; 1618 + nvidia,core-power-req-active-high; 1619 + nvidia,sys-clock-req-active-high; 1620 + }; 1621 + 1622 + /* SD card */ 1623 + sdhci@0,700b0400 { 1624 + status = "okay"; 1625 + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1626 + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1627 + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; 1628 + bus-width = <4>; 1629 + vqmmc-supply = <&vddio_sdmmc3>; 1630 + }; 1631 + 1632 + /* eMMC */ 1633 + sdhci@0,700b0600 { 1634 + status = "okay"; 1635 + bus-width = <8>; 1636 + }; 1637 + 1638 + ahub@0,70300000 { 1639 + i2s@0,70301100 { 1640 + status = "okay"; 1641 + }; 1642 + }; 1643 + 1644 + /* mini-PCIe USB */ 1645 + usb@0,7d004000 { 1646 + status = "okay"; 1647 + }; 1648 + 1649 + usb-phy@0,7d004000 { 1650 + status = "okay"; 1651 + }; 1652 + 1653 + /* USB A connector */ 1654 + usb@0,7d008000 { 1655 + status = "okay"; 1656 + }; 1657 + 1658 + usb-phy@0,7d008000 { 1659 + status = "okay"; 1660 + vbus-supply = <&vdd_usb3_vbus>; 1661 + }; 1662 + 1663 + clocks { 1664 + compatible = "simple-bus"; 1665 + #address-cells = <1>; 1666 + #size-cells = <0>; 1667 + 1668 + clk32k_in: clock@0 { 1669 + compatible = "fixed-clock"; 1670 + reg = <0>; 1671 + #clock-cells = <0>; 1672 + clock-frequency = <32768>; 1673 + }; 1674 + }; 1675 + 1676 + gpio-keys { 1677 + compatible = "gpio-keys"; 1678 + 1679 + power { 1680 + label = "Power"; 1681 + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1682 + linux,code = <KEY_POWER>; 1683 + debounce-interval = <10>; 1684 + gpio-key,wakeup; 1685 + }; 1686 + }; 1687 + 1688 + regulators { 1689 + compatible = "simple-bus"; 1690 + #address-cells = <1>; 1691 + #size-cells = <0>; 1692 + 1693 + vdd_mux: regulator@0 { 1694 + compatible = "regulator-fixed"; 1695 + reg = <0>; 1696 + regulator-name = "+VDD_MUX"; 1697 + regulator-min-microvolt = <12000000>; 1698 + regulator-max-microvolt = <12000000>; 1699 + regulator-always-on; 1700 + regulator-boot-on; 1701 + }; 1702 + 1703 + vdd_5v0_sys: regulator@1 { 1704 + compatible = "regulator-fixed"; 1705 + reg = <1>; 1706 + regulator-name = "+5V_SYS"; 1707 + regulator-min-microvolt = <5000000>; 1708 + regulator-max-microvolt = <5000000>; 1709 + regulator-always-on; 1710 + regulator-boot-on; 1711 + vin-supply = <&vdd_mux>; 1712 + }; 1713 + 1714 + vdd_3v3_sys: regulator@2 { 1715 + compatible = "regulator-fixed"; 1716 + reg = <2>; 1717 + regulator-name = "+3.3V_SYS"; 1718 + regulator-min-microvolt = <3300000>; 1719 + regulator-max-microvolt = <3300000>; 1720 + regulator-always-on; 1721 + regulator-boot-on; 1722 + vin-supply = <&vdd_mux>; 1723 + }; 1724 + 1725 + vdd_3v3_run: regulator@3 { 1726 + compatible = "regulator-fixed"; 1727 + reg = <3>; 1728 + regulator-name = "+3.3V_RUN"; 1729 + regulator-min-microvolt = <3300000>; 1730 + regulator-max-microvolt = <3300000>; 1731 + regulator-always-on; 1732 + regulator-boot-on; 1733 + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 1734 + enable-active-high; 1735 + vin-supply = <&vdd_3v3_sys>; 1736 + }; 1737 + 1738 + vdd_3v3_hdmi: regulator@4 { 1739 + compatible = "regulator-fixed"; 1740 + reg = <4>; 1741 + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; 1742 + regulator-min-microvolt = <3300000>; 1743 + regulator-max-microvolt = <3300000>; 1744 + vin-supply = <&vdd_3v3_run>; 1745 + }; 1746 + 1747 + vdd_usb1_vbus: regulator@7 { 1748 + compatible = "regulator-fixed"; 1749 + reg = <7>; 1750 + regulator-name = "+USB0_VBUS_SW"; 1751 + regulator-min-microvolt = <5000000>; 1752 + regulator-max-microvolt = <5000000>; 1753 + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 1754 + enable-active-high; 1755 + gpio-open-drain; 1756 + vin-supply = <&vdd_5v0_sys>; 1757 + }; 1758 + 1759 + vdd_usb3_vbus: regulator@8 { 1760 + compatible = "regulator-fixed"; 1761 + reg = <8>; 1762 + regulator-name = "+5V_USB_HS"; 1763 + regulator-min-microvolt = <5000000>; 1764 + regulator-max-microvolt = <5000000>; 1765 + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; 1766 + enable-active-high; 1767 + gpio-open-drain; 1768 + vin-supply = <&vdd_5v0_sys>; 1769 + }; 1770 + 1771 + vdd_3v3_lp0: regulator@10 { 1772 + compatible = "regulator-fixed"; 1773 + reg = <10>; 1774 + regulator-name = "+3.3V_LP0"; 1775 + regulator-min-microvolt = <3300000>; 1776 + regulator-max-microvolt = <3300000>; 1777 + regulator-always-on; 1778 + regulator-boot-on; 1779 + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 1780 + enable-active-high; 1781 + vin-supply = <&vdd_3v3_sys>; 1782 + }; 1783 + 1784 + vdd_hdmi_pll: regulator@11 { 1785 + compatible = "regulator-fixed"; 1786 + reg = <11>; 1787 + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; 1788 + regulator-min-microvolt = <1050000>; 1789 + regulator-max-microvolt = <1050000>; 1790 + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1791 + vin-supply = <&vdd_1v05_run>; 1792 + }; 1793 + 1794 + vdd_5v0_hdmi: regulator@12 { 1795 + compatible = "regulator-fixed"; 1796 + reg = <12>; 1797 + regulator-name = "+5V_HDMI_CON"; 1798 + regulator-min-microvolt = <5000000>; 1799 + regulator-max-microvolt = <5000000>; 1800 + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1801 + enable-active-high; 1802 + vin-supply = <&vdd_5v0_sys>; 1803 + }; 1804 + }; 1805 + 1806 + sound { 1807 + compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", 1808 + "nvidia,tegra-audio-rt5640"; 1809 + nvidia,model = "NVIDIA Tegra Jetson TK1"; 1810 + 1811 + nvidia,audio-routing = 1812 + "Headphones", "HPOR", 1813 + "Headphones", "HPOL", 1814 + "Mic Jack", "MICBIAS1", 1815 + "IN2P", "Mic Jack"; 1816 + 1817 + nvidia,i2s-controller = <&tegra_i2s1>; 1818 + nvidia,audio-codec = <&rt5639>; 1819 + 1820 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; 1821 + 1822 + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 1823 + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 1824 + <&tegra_car TEGRA124_CLK_EXTERN1>; 1825 + clock-names = "pll_a", "pll_a_out0", "mclk"; 1826 + }; 1827 + };
+39 -3
arch/arm/boot/dts/tegra124-venice2.dts
··· 17 17 }; 18 18 19 19 host1x@0,50000000 { 20 + hdmi@0,54280000 { 21 + status = "okay"; 22 + 23 + vdd-supply = <&vdd_3v3_hdmi>; 24 + pll-supply = <&vdd_hdmi_pll>; 25 + hdmi-supply = <&vdd_5v0_hdmi>; 26 + 27 + nvidia,ddc-i2c-bus = <&hdmi_ddc>; 28 + nvidia,hpd-gpio = 29 + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 30 + }; 31 + 20 32 sor@0,54540000 { 21 33 status = "okay"; 22 34 ··· 613 601 clock-frequency = <100000>; 614 602 }; 615 603 616 - i2c@0,7000c700 { 604 + hdmi_ddc: i2c@0,7000c700 { 617 605 status = "okay"; 618 606 clock-frequency = <100000>; 619 607 }; ··· 712 700 regulator-boot-on; 713 701 }; 714 702 715 - sd4 { 703 + vdd_1v05_run: sd4 { 716 704 regulator-name = "+1.05V_RUN"; 717 705 regulator-min-microvolt = <1050000>; 718 706 regulator-max-microvolt = <1050000>; ··· 943 931 sdhci@0,700b0400 { 944 932 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 945 933 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 934 + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 946 935 status = "okay"; 947 936 bus-width = <4>; 948 - vmmc-supply = <&vddio_sdmmc3>; 937 + vqmmc-supply = <&vddio_sdmmc3>; 949 938 }; 950 939 951 940 sdhci@0,700b0600 { ··· 1073 1060 regulator-name = "+3.3V_RUN"; 1074 1061 regulator-min-microvolt = <3300000>; 1075 1062 regulator-max-microvolt = <3300000>; 1063 + regulator-always-on; 1064 + regulator-boot-on; 1076 1065 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 1077 1066 enable-active-high; 1078 1067 vin-supply = <&vdd_3v3_sys>; ··· 1159 1144 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 1160 1145 enable-active-high; 1161 1146 vin-supply = <&vdd_3v3_sys>; 1147 + }; 1148 + 1149 + vdd_hdmi_pll: regulator@11 { 1150 + compatible = "regulator-fixed"; 1151 + reg = <11>; 1152 + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; 1153 + regulator-min-microvolt = <1050000>; 1154 + regulator-max-microvolt = <1050000>; 1155 + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1156 + vin-supply = <&vdd_1v05_run>; 1157 + }; 1158 + 1159 + vdd_5v0_hdmi: regulator@12 { 1160 + compatible = "regulator-fixed"; 1161 + reg = <12>; 1162 + regulator-name = "+5V_HDMI_CON"; 1163 + regulator-min-microvolt = <5000000>; 1164 + regulator-max-microvolt = <5000000>; 1165 + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1166 + enable-active-high; 1167 + vin-supply = <&vdd_5v0_sys>; 1162 1168 }; 1163 1169 }; 1164 1170
+12
arch/arm/boot/dts/tegra124.dtsi
··· 51 51 nvidia,head = <1>; 52 52 }; 53 53 54 + hdmi@0,54280000 { 55 + compatible = "nvidia,tegra124-hdmi"; 56 + reg = <0x0 0x54280000 0x0 0x00040000>; 57 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 58 + clocks = <&tegra_car TEGRA124_CLK_HDMI>, 59 + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 60 + clock-names = "hdmi", "parent"; 61 + resets = <&tegra_car 51>; 62 + reset-names = "hdmi"; 63 + status = "disabled"; 64 + }; 65 + 54 66 sor@0,54540000 { 55 67 compatible = "nvidia,tegra124-sor"; 56 68 reg = <0x0 0x54540000 0x0 0x00040000>;
+12
arch/arm/boot/dts/tegra20-harmony.dts
··· 28 28 hdmi@54280000 { 29 29 status = "okay"; 30 30 31 + hdmi-supply = <&vdd_5v0_hdmi>; 31 32 vdd-supply = <&hdmi_vdd_reg>; 32 33 pll-supply = <&hdmi_pll_reg>; 33 34 ··· 724 723 regulator-max-microvolt = <2800000>; 725 724 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 726 725 enable-active-high; 726 + }; 727 + 728 + vdd_5v0_hdmi: regulator@6 { 729 + compatible = "regulator-fixed"; 730 + reg = <6>; 731 + regulator-name = "VDDIO_HDMI"; 732 + regulator-min-microvolt = <5000000>; 733 + regulator-max-microvolt = <5000000>; 734 + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; 735 + enable-active-high; 736 + vin-supply = <&vdd_5v0_reg>; 727 737 }; 728 738 }; 729 739
+12
arch/arm/boot/dts/tegra30-beaver.dts
··· 40 40 hdmi@54280000 { 41 41 status = "okay"; 42 42 43 + hdmi-supply = <&vdd_5v0_hdmi>; 43 44 vdd-supply = <&sys_3v3_reg>; 44 45 pll-supply = <&vio_reg>; 45 46 ··· 477 476 regulator-boot-on; 478 477 enable-active-high; 479 478 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; 479 + vin-supply = <&sys_3v3_reg>; 480 + }; 481 + 482 + vdd_5v0_hdmi: regulator@8 { 483 + compatible = "regulator-fixed"; 484 + reg = <8>; 485 + regulator-name = "+VDD_5V_HDMI"; 486 + regulator-min-microvolt = <5000000>; 487 + regulator-max-microvolt = <5000000>; 488 + regulator-always-on; 489 + regulator-boot-on; 480 490 vin-supply = <&sys_3v3_reg>; 481 491 }; 482 492 };
+205
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
··· 1 + /dts-v1/; 2 + 3 + #include "tegra30-colibri.dtsi" 4 + 5 + / { 6 + model = "Toradex Colibri T30 on Colibri Evaluation Board"; 7 + compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; 8 + 9 + aliases { 10 + rtc0 = "/i2c@7000c000/rtc@68"; 11 + rtc1 = "/i2c@7000d000/tps65911@2d"; 12 + rtc2 = "/rtc@7000e000"; 13 + }; 14 + 15 + host1x@50000000 { 16 + dc@54200000 { 17 + rgb { 18 + status = "okay"; 19 + nvidia,panel = <&panel>; 20 + }; 21 + }; 22 + hdmi@54280000 { 23 + status = "okay"; 24 + }; 25 + }; 26 + 27 + serial@70006000 { 28 + status = "okay"; 29 + }; 30 + 31 + serial@70006040 { 32 + compatible = "nvidia,tegra30-hsuart"; 33 + status = "okay"; 34 + }; 35 + 36 + serial@70006300 { 37 + compatible = "nvidia,tegra30-hsuart"; 38 + status = "okay"; 39 + }; 40 + 41 + pwm@7000a000 { 42 + status = "okay"; 43 + }; 44 + 45 + /* 46 + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier 47 + * board) 48 + */ 49 + i2c@7000c000 { 50 + status = "okay"; 51 + clock-frequency = <100000>; 52 + 53 + /* M41T0M6 real time clock on carrier board */ 54 + rtc@68 { 55 + compatible = "stm,m41t00"; 56 + reg = <0x68>; 57 + }; 58 + }; 59 + 60 + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ 61 + hdmiddc: i2c@7000c700 { 62 + status = "okay"; 63 + }; 64 + 65 + /* SPI1: Colibri SSP */ 66 + spi@7000d400 { 67 + status = "okay"; 68 + spi-max-frequency = <25000000>; 69 + can0: can@0 { 70 + compatible = "microchip,mcp2515"; 71 + reg = <0>; 72 + clocks = <&clk16m>; 73 + interrupt-parent = <&gpio>; 74 + interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 75 + spi-max-frequency = <10000000>; 76 + }; 77 + spidev0: spi@1 { 78 + compatible = "spidev"; 79 + reg = <1>; 80 + spi-max-frequency = <25000000>; 81 + }; 82 + }; 83 + 84 + sdhci@78000200 { 85 + status = "okay"; 86 + bus-width = <4>; 87 + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; 88 + no-1-8-v; 89 + }; 90 + 91 + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ 92 + usb@7d000000 { 93 + status = "okay"; 94 + }; 95 + 96 + usb-phy@7d000000 { 97 + status = "okay"; 98 + dr_mode = "otg"; 99 + vbus-supply = <&usbc_vbus_reg>; 100 + }; 101 + 102 + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ 103 + usb@7d008000 { 104 + status = "okay"; 105 + }; 106 + 107 + usb-phy@7d008000 { 108 + status = "okay"; 109 + vbus-supply = <&usbh_vbus_reg>; 110 + }; 111 + 112 + backlight: backlight { 113 + compatible = "pwm-backlight"; 114 + 115 + /* PWM<A> */ 116 + pwms = <&pwm 0 5000000>; 117 + brightness-levels = <255 128 64 32 16 8 4 0>; 118 + default-brightness-level = <6>; 119 + /* BL_ON */ 120 + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 121 + }; 122 + 123 + clocks { 124 + clk16m: clk@1 { 125 + compatible = "fixed-clock"; 126 + reg=<1>; 127 + #clock-cells = <0>; 128 + clock-frequency = <16000000>; 129 + clock-output-names = "clk16m"; 130 + }; 131 + }; 132 + 133 + gpio-keys { 134 + compatible = "gpio-keys"; 135 + 136 + power { 137 + label = "Power"; 138 + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 139 + linux,code = <KEY_POWER>; 140 + debounce-interval = <10>; 141 + gpio-key,wakeup; 142 + }; 143 + }; 144 + 145 + panel: panel { 146 + /* 147 + * edt,et057090dhu: EDT 5.7" LCD TFT 148 + * edt,et070080dh6: EDT 7.0" LCD TFT 149 + */ 150 + compatible = "edt,et057090dhu", "simple-panel"; 151 + 152 + backlight = <&backlight>; 153 + }; 154 + 155 + pwmleds { 156 + compatible = "pwm-leds"; 157 + 158 + pwmb { 159 + label = "PWM<B>"; 160 + pwms = <&pwm 1 19600>; 161 + max-brightness = <255>; 162 + }; 163 + pwmc { 164 + label = "PWM<C>"; 165 + pwms = <&pwm 2 19600>; 166 + max-brightness = <255>; 167 + }; 168 + pwmd { 169 + label = "PWM<D>"; 170 + pwms = <&pwm 3 19600>; 171 + max-brightness = <255>; 172 + }; 173 + }; 174 + 175 + regulators { 176 + sys_5v0_reg: regulator@1 { 177 + compatible = "regulator-fixed"; 178 + reg = <1>; 179 + regulator-name = "5v0"; 180 + regulator-min-microvolt = <5000000>; 181 + regulator-max-microvolt = <5000000>; 182 + regulator-always-on; 183 + }; 184 + 185 + usbc_vbus_reg: regulator@2 { 186 + compatible = "regulator-fixed"; 187 + reg = <2>; 188 + regulator-name = "usbc_vbus"; 189 + regulator-min-microvolt = <5000000>; 190 + regulator-max-microvolt = <5000000>; 191 + vin-supply = <&sys_5v0_reg>; 192 + }; 193 + 194 + /* USBH_PEN */ 195 + usbh_vbus_reg: regulator@3 { 196 + compatible = "regulator-fixed"; 197 + reg = <3>; 198 + regulator-name = "usbh_vbus"; 199 + regulator-min-microvolt = <5000000>; 200 + regulator-max-microvolt = <5000000>; 201 + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 202 + vin-supply = <&sys_5v0_reg>; 203 + }; 204 + }; 205 + };
+377
arch/arm/boot/dts/tegra30-colibri.dtsi
··· 1 + #include <dt-bindings/input/input.h> 2 + #include "tegra30.dtsi" 3 + 4 + /* 5 + * Toradex Colibri T30 Device Tree 6 + * Compatible for Revisions 1.1B/1.1C/1.1D 7 + */ 8 + / { 9 + model = "Toradex Colibri T30"; 10 + compatible = "toradex,colibri_t30", "nvidia,tegra30"; 11 + 12 + memory { 13 + reg = <0x80000000 0x40000000>; 14 + }; 15 + 16 + host1x@50000000 { 17 + hdmi@54280000 { 18 + vdd-supply = <&sys_3v3_reg>; 19 + pll-supply = <&vio_reg>; 20 + 21 + nvidia,hpd-gpio = 22 + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 23 + nvidia,ddc-i2c-bus = <&hdmiddc>; 24 + }; 25 + }; 26 + 27 + pinmux@70000868 { 28 + pinctrl-names = "default"; 29 + pinctrl-0 = <&state_default>; 30 + 31 + state_default: pinmux { 32 + /* Colibri BL_ON */ 33 + pv2 { 34 + nvidia,pins = "pv2"; 35 + nvidia,function = "rsvd4"; 36 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 37 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 38 + }; 39 + 40 + /* Colibri Backlight PWM<A> */ 41 + sdmmc3_dat3_pb4 { 42 + nvidia,pins = "sdmmc3_dat3_pb4"; 43 + nvidia,function = "pwm0"; 44 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 45 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 46 + }; 47 + 48 + /* Colibri CAN_INT */ 49 + kb_row8_ps0 { 50 + nvidia,pins = "kb_row8_ps0"; 51 + nvidia,function = "kbc"; 52 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 53 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 54 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 55 + }; 56 + 57 + /* 58 + * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE 59 + * todays display need DE, disable LCD_M1 60 + */ 61 + lcd_m1_pw1 { 62 + nvidia,pins = "lcd_m1_pw1"; 63 + nvidia,function = "rsvd3"; 64 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 65 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 66 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 67 + }; 68 + 69 + /* Thermal alert, need to be disabled */ 70 + lcd_dc1_pd2 { 71 + nvidia,pins = "lcd_dc1_pd2"; 72 + nvidia,function = "rsvd3"; 73 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 74 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 75 + nvidia,enable-input = <TEGRA_PIN_ENABLE>; 76 + }; 77 + 78 + /* Colibri MMC */ 79 + kb_row10_ps2 { 80 + nvidia,pins = "kb_row10_ps2"; 81 + nvidia,function = "sdmmc2"; 82 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 83 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 84 + }; 85 + kb_row11_ps3 { 86 + nvidia,pins = "kb_row11_ps3", 87 + "kb_row12_ps4", 88 + "kb_row13_ps5", 89 + "kb_row14_ps6", 90 + "kb_row15_ps7"; 91 + nvidia,function = "sdmmc2"; 92 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 93 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 94 + }; 95 + 96 + /* Colibri SSP */ 97 + ulpi_clk_py0 { 98 + nvidia,pins = "ulpi_clk_py0", 99 + "ulpi_dir_py1", 100 + "ulpi_nxt_py2", 101 + "ulpi_stp_py3"; 102 + nvidia,function = "spi1"; 103 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 104 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 105 + }; 106 + sdmmc3_dat6_pd3 { 107 + nvidia,pins = "sdmmc3_dat6_pd3", 108 + "sdmmc3_dat7_pd4"; 109 + nvidia,function = "spdif"; 110 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 111 + nvidia,tristate = <TEGRA_PIN_ENABLE>; 112 + }; 113 + 114 + /* Colibri UART_A */ 115 + ulpi_data0 { 116 + nvidia,pins = "ulpi_data0_po1", 117 + "ulpi_data1_po2", 118 + "ulpi_data2_po3", 119 + "ulpi_data3_po4", 120 + "ulpi_data4_po5", 121 + "ulpi_data5_po6", 122 + "ulpi_data6_po7", 123 + "ulpi_data7_po0"; 124 + nvidia,function = "uarta"; 125 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 126 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 127 + }; 128 + 129 + /* Colibri UART_B */ 130 + gmi_a16_pj7 { 131 + nvidia,pins = "gmi_a16_pj7", 132 + "gmi_a17_pb0", 133 + "gmi_a18_pb1", 134 + "gmi_a19_pk7"; 135 + nvidia,function = "uartd"; 136 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 137 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 138 + }; 139 + 140 + /* Colibri UART_C */ 141 + uart2_rxd { 142 + nvidia,pins = "uart2_rxd_pc3", 143 + "uart2_txd_pc2"; 144 + nvidia,function = "uartb"; 145 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 146 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 147 + }; 148 + 149 + /* eMMC */ 150 + sdmmc4_clk_pcc4 { 151 + nvidia,pins = "sdmmc4_clk_pcc4", 152 + "sdmmc4_rst_n_pcc3"; 153 + nvidia,function = "sdmmc4"; 154 + nvidia,pull = <TEGRA_PIN_PULL_NONE>; 155 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 156 + }; 157 + sdmmc4_dat0_paa0 { 158 + nvidia,pins = "sdmmc4_dat0_paa0", 159 + "sdmmc4_dat1_paa1", 160 + "sdmmc4_dat2_paa2", 161 + "sdmmc4_dat3_paa3", 162 + "sdmmc4_dat4_paa4", 163 + "sdmmc4_dat5_paa5", 164 + "sdmmc4_dat6_paa6", 165 + "sdmmc4_dat7_paa7"; 166 + nvidia,function = "sdmmc4"; 167 + nvidia,pull = <TEGRA_PIN_PULL_UP>; 168 + nvidia,tristate = <TEGRA_PIN_DISABLE>; 169 + }; 170 + }; 171 + }; 172 + 173 + hdmiddc: i2c@7000c700 { 174 + clock-frequency = <100000>; 175 + }; 176 + 177 + /* 178 + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 179 + * touch screen controller 180 + */ 181 + i2c@7000d000 { 182 + status = "okay"; 183 + clock-frequency = <100000>; 184 + 185 + pmic: tps65911@2d { 186 + compatible = "ti,tps65911"; 187 + reg = <0x2d>; 188 + 189 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 190 + #interrupt-cells = <2>; 191 + interrupt-controller; 192 + 193 + ti,system-power-controller; 194 + 195 + #gpio-cells = <2>; 196 + gpio-controller; 197 + 198 + vcc1-supply = <&sys_3v3_reg>; 199 + vcc2-supply = <&sys_3v3_reg>; 200 + vcc3-supply = <&vio_reg>; 201 + vcc4-supply = <&sys_3v3_reg>; 202 + vcc5-supply = <&sys_3v3_reg>; 203 + vcc6-supply = <&vio_reg>; 204 + vcc7-supply = <&sys_5v0_reg>; 205 + vccio-supply = <&sys_3v3_reg>; 206 + 207 + regulators { 208 + /* SW1: +V1.35_VDDIO_DDR */ 209 + vdd1_reg: vdd1 { 210 + regulator-name = "vddio_ddr_1v35"; 211 + regulator-min-microvolt = <1350000>; 212 + regulator-max-microvolt = <1350000>; 213 + regulator-always-on; 214 + }; 215 + 216 + /* SW2: unused */ 217 + 218 + /* SW CTRL: +V1.0_VDD_CPU */ 219 + vddctrl_reg: vddctrl { 220 + regulator-name = "vdd_cpu,vdd_sys"; 221 + regulator-min-microvolt = <1150000>; 222 + regulator-max-microvolt = <1150000>; 223 + regulator-always-on; 224 + }; 225 + 226 + /* SWIO: +V1.8 */ 227 + vio_reg: vio { 228 + regulator-name = "vdd_1v8_gen"; 229 + regulator-min-microvolt = <1800000>; 230 + regulator-max-microvolt = <1800000>; 231 + regulator-always-on; 232 + }; 233 + 234 + /* LDO1: unused */ 235 + 236 + /* 237 + * EN_+V3.3 switching via FET: 238 + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 239 + * see also v3_3 fixed supply 240 + */ 241 + ldo2_reg: ldo2 { 242 + regulator-name = "en_3v3"; 243 + regulator-min-microvolt = <3300000>; 244 + regulator-max-microvolt = <3300000>; 245 + regulator-always-on; 246 + }; 247 + 248 + /* LDO3: unused */ 249 + 250 + /* +V1.2_VDD_RTC */ 251 + ldo4_reg: ldo4 { 252 + regulator-name = "vdd_rtc"; 253 + regulator-min-microvolt = <1200000>; 254 + regulator-max-microvolt = <1200000>; 255 + regulator-always-on; 256 + }; 257 + 258 + /* 259 + * +V2.8_AVDD_VDAC: 260 + * only required for analog RGB 261 + */ 262 + ldo5_reg: ldo5 { 263 + regulator-name = "avdd_vdac"; 264 + regulator-min-microvolt = <2800000>; 265 + regulator-max-microvolt = <2800000>; 266 + regulator-always-on; 267 + }; 268 + 269 + /* 270 + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 271 + * but LDO6 can't set voltage in 50mV 272 + * granularity 273 + */ 274 + ldo6_reg: ldo6 { 275 + regulator-name = "avdd_plle"; 276 + regulator-min-microvolt = <1100000>; 277 + regulator-max-microvolt = <1100000>; 278 + }; 279 + 280 + /* +V1.2_AVDD_PLL */ 281 + ldo7_reg: ldo7 { 282 + regulator-name = "avdd_pll"; 283 + regulator-min-microvolt = <1200000>; 284 + regulator-max-microvolt = <1200000>; 285 + regulator-always-on; 286 + }; 287 + 288 + /* +V1.0_VDD_DDR_HS */ 289 + ldo8_reg: ldo8 { 290 + regulator-name = "vdd_ddr_hs"; 291 + regulator-min-microvolt = <1000000>; 292 + regulator-max-microvolt = <1000000>; 293 + regulator-always-on; 294 + }; 295 + }; 296 + }; 297 + 298 + /* 299 + * LM95245 temperature sensor 300 + * Note: OVERT_N directly connected to PMIC PWRDN 301 + */ 302 + temp-sensor@4c { 303 + compatible = "national,lm95245"; 304 + reg = <0x4c>; 305 + }; 306 + 307 + /* SW: +V1.2_VDD_CORE */ 308 + tps62362@60 { 309 + compatible = "ti,tps62362"; 310 + reg = <0x60>; 311 + 312 + regulator-name = "tps62362-vout"; 313 + regulator-min-microvolt = <900000>; 314 + regulator-max-microvolt = <1400000>; 315 + regulator-boot-on; 316 + regulator-always-on; 317 + ti,vsel0-state-low; 318 + /* VSEL1: EN_CORE_DVFS_N low for DVFS */ 319 + ti,vsel1-state-low; 320 + }; 321 + }; 322 + 323 + pmc@7000e400 { 324 + nvidia,invert-interrupt; 325 + nvidia,suspend-mode = <1>; 326 + nvidia,cpu-pwr-good-time = <5000>; 327 + nvidia,cpu-pwr-off-time = <5000>; 328 + nvidia,core-pwr-good-time = <3845 3845>; 329 + nvidia,core-pwr-off-time = <0>; 330 + nvidia,core-power-req-active-high; 331 + nvidia,sys-clock-req-active-high; 332 + }; 333 + 334 + emmc: sdhci@78000600 { 335 + status = "okay"; 336 + bus-width = <8>; 337 + non-removable; 338 + }; 339 + 340 + /* EHCI instance 1: USB2_DP/N -> AX88772B */ 341 + usb@7d004000 { 342 + status = "okay"; 343 + }; 344 + 345 + usb-phy@7d004000 { 346 + status = "okay"; 347 + nvidia,is-wired = <1>; 348 + }; 349 + 350 + clocks { 351 + compatible = "simple-bus"; 352 + #address-cells = <1>; 353 + #size-cells = <0>; 354 + 355 + clk32k_in: clk@0 { 356 + compatible = "fixed-clock"; 357 + reg=<0>; 358 + #clock-cells = <0>; 359 + clock-frequency = <32768>; 360 + }; 361 + }; 362 + 363 + regulators { 364 + compatible = "simple-bus"; 365 + #address-cells = <1>; 366 + #size-cells = <0>; 367 + 368 + sys_3v3_reg: regulator@100 { 369 + compatible = "regulator-fixed"; 370 + reg = <100>; 371 + regulator-name = "3v3"; 372 + regulator-min-microvolt = <3300000>; 373 + regulator-max-microvolt = <3300000>; 374 + regulator-always-on; 375 + }; 376 + }; 377 + };