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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dmaengine: shdma: separate DMA headers.
Separate SH DMA headers into ones, commonly used by both drivers, and ones,
specific to each of them. This will make the future development of the
dmaengine driver easier.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Guennadi Liakhovetski
and committed by
Paul Mundt
8b1935e6
027811b9
+415
-258
+51
arch/sh/include/asm/dma-register.h
+51
arch/sh/include/asm/dma-register.h
···
1
+
/*
2
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* Common header for the legacy SH DMA driver and the new dmaengine driver
3
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*
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* extracted from arch/sh/include/asm/dma-sh.h:
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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+
*/
13
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#ifndef DMA_REGISTER_H
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#define DMA_REGISTER_H
15
+
16
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/* DMA register */
17
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
20
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#define CHCR 0x0C
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#define DMAOR 0x40
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+
23
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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+
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define DM_FIX 0x0000c000
40
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define SM_FIX 0x00003000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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+
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#endif
+2
-93
arch/sh/include/asm/dma-sh.h
+2
-93
arch/sh/include/asm/dma-sh.h
···
11
11
#ifndef __DMA_SH_H
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12
#define __DMA_SH_H
13
13
14
-
#include <asm/dma.h>
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#include <asm/dma-register.h>
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#include <cpu/dma-register.h>
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#include <cpu/dma.h>
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/* DMAOR contorl: The DMAOR access size is different by CPU.*/
···
54
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#endif
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};
56
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57
-
/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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-
#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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-
#define DM_FIX 0x0000c000
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-
#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define SM_FIX 0x00003000
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#define RS_IN 0x00000200
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-
#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
77
-
#define CHCR_TE 0x00000002
78
-
#define CHCR_IE 0x00000004
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-
80
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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-
85
56
/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
···
82
109
SH_DMAC_BASE1 + 0x50,
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SH_DMAC_BASE1 + 0x60, /* channel 11 */
84
111
#endif
85
-
};
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-
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/* DMA register */
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#define SAR 0x00
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-
#define DAR 0x04
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#define TCR 0x08
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-
#define CHCR 0x0C
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#define DMAOR 0x40
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-
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/*
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* for dma engine
96
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*
97
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* SuperH DMA mode
98
-
*/
99
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#define SHDMA_MIX_IRQ (1 << 1)
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#define SHDMA_DMAOR1 (1 << 2)
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#define SHDMA_DMAE1 (1 << 3)
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-
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enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SIUA_TX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_NUMBER, /* Must stay last */
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-
};
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-
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struct sh_dmae_slave_config {
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enum sh_dmae_slave_chan_id slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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-
};
129
-
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
134
-
};
135
-
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struct sh_dmae_pdata {
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struct sh_dmae_slave_config *slave;
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int slave_num;
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struct sh_dmae_channel *channel;
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int channel_num;
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-
};
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-
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struct device;
144
-
145
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struct sh_dmae_slave {
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enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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struct sh_dmae_slave_config *config; /* Set by the driver */
149
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};
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#endif /* __DMA_SH_H */
+73
arch/sh/include/asm/dmaengine.h
+73
arch/sh/include/asm/dmaengine.h
···
1
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/*
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* Header for the new SH dmaengine driver
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
7
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* it under the terms of the GNU General Public License version 2 as
8
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* published by the Free Software Foundation.
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*/
10
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#ifndef ASM_DMAENGINE_H
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#define ASM_DMAENGINE_H
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13
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#include <asm/dma-register.h>
14
+
15
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#define SH_DMAC_MAX_CHANNELS 6
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17
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enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SIUA_TX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_NUMBER, /* Must stay last */
35
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};
36
+
37
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struct sh_dmae_slave_config {
38
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enum sh_dmae_slave_chan_id slave_id;
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dma_addr_t addr;
40
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u32 chcr;
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char mid_rid;
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};
43
+
44
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struct sh_dmae_channel {
45
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unsigned int offset;
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unsigned int dmars;
47
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unsigned int dmars_bit;
48
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};
49
+
50
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struct sh_dmae_pdata {
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struct sh_dmae_slave_config *slave;
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int slave_num;
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struct sh_dmae_channel *channel;
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int channel_num;
55
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unsigned int ts_low_shift;
56
+
unsigned int ts_low_mask;
57
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unsigned int ts_high_shift;
58
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unsigned int ts_high_mask;
59
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unsigned int *ts_shift;
60
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int ts_shift_num;
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u16 dmaor_init;
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};
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+
64
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struct device;
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+
66
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
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struct sh_dmae_slave {
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enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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struct sh_dmae_slave_config *config; /* Set by the driver */
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};
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+
73
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#endif
+1
-1
arch/sh/include/asm/siu.h
+1
-1
arch/sh/include/asm/siu.h
+41
arch/sh/include/cpu-sh3/cpu/dma-register.h
+41
arch/sh/include/cpu-sh3/cpu/dma-register.h
···
1
+
/*
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* SH3 CPU-specific DMA definitions, used by both DMA drivers
3
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5
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*
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* This program is free software; you can redistribute it and/or modify
7
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* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
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*/
10
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#ifndef CPU_DMA_REGISTER_H
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#define CPU_DMA_REGISTER_H
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+
13
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#define CHCR_TS_LOW_MASK 0x18
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#define DMAOR_INIT DMAOR_DME
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+
20
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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* with their respective values as they appear in the CHCR registers.
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*/
24
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enum {
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_128BIT,
29
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};
30
+
31
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_128BIT] = 4, \
37
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}
38
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39
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#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
40
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41
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#endif
-27
arch/sh/include/cpu-sh3/cpu/dma.h
-27
arch/sh/include/cpu-sh3/cpu/dma.h
···
20
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#define TS_32 0x00000010
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#define TS_128 0x00000018
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22
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#define CHCR_TS_LOW_MASK 0x18
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
27
-
28
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#define DMAOR_INIT DMAOR_DME
29
-
30
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
32
-
* with their respective values as they appear in the CHCR registers.
33
-
*/
34
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enum {
35
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XMIT_SZ_8BIT,
36
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XMIT_SZ_16BIT,
37
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XMIT_SZ_32BIT,
38
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XMIT_SZ_128BIT,
39
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};
40
-
41
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#define TS_SHIFT { \
42
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[XMIT_SZ_8BIT] = 0, \
43
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[XMIT_SZ_16BIT] = 1, \
44
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[XMIT_SZ_32BIT] = 2, \
45
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[XMIT_SZ_128BIT] = 4, \
46
-
}
47
-
48
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#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
49
-
50
23
#endif /* __ASM_CPU_SH3_DMA_H */
+116
arch/sh/include/cpu-sh4/cpu/dma-register.h
+116
arch/sh/include/cpu-sh4/cpu/dma-register.h
···
1
+
/*
2
+
* SH4 CPU-specific DMA definitions, used by both DMA drivers
3
+
*
4
+
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
#ifndef CPU_DMA_REGISTER_H
11
+
#define CPU_DMA_REGISTER_H
12
+
13
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/* SH7751/7760/7780 DMA IRQ sources */
14
+
15
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#ifdef CONFIG_CPU_SH4A
16
+
17
+
#define DMAOR_INIT DMAOR_DME
18
+
19
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#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
20
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defined(CONFIG_CPU_SUBTYPE_SH7730)
21
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#define CHCR_TS_LOW_MASK 0x00000018
22
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#define CHCR_TS_LOW_SHIFT 3
23
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#define CHCR_TS_HIGH_MASK 0
24
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#define CHCR_TS_HIGH_SHIFT 0
25
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
26
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#define CHCR_TS_LOW_MASK 0x00000018
27
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#define CHCR_TS_LOW_SHIFT 3
28
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#define CHCR_TS_HIGH_MASK 0x00300000
29
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#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
30
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
31
+
defined(CONFIG_CPU_SUBTYPE_SH7764)
32
+
#define CHCR_TS_LOW_MASK 0x00000018
33
+
#define CHCR_TS_LOW_SHIFT 3
34
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#define CHCR_TS_HIGH_MASK 0
35
+
#define CHCR_TS_HIGH_SHIFT 0
36
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
37
+
#define CHCR_TS_LOW_MASK 0x00000018
38
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#define CHCR_TS_LOW_SHIFT 3
39
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#define CHCR_TS_HIGH_MASK 0
40
+
#define CHCR_TS_HIGH_SHIFT 0
41
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
42
+
#define CHCR_TS_LOW_MASK 0x00000018
43
+
#define CHCR_TS_LOW_SHIFT 3
44
+
#define CHCR_TS_HIGH_MASK 0x00600000
45
+
#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
46
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
47
+
#define CHCR_TS_LOW_MASK 0x00000018
48
+
#define CHCR_TS_LOW_SHIFT 3
49
+
#define CHCR_TS_HIGH_MASK 0
50
+
#define CHCR_TS_HIGH_SHIFT 0
51
+
#else /* SH7785 */
52
+
#define CHCR_TS_LOW_MASK 0x00000018
53
+
#define CHCR_TS_LOW_SHIFT 3
54
+
#define CHCR_TS_HIGH_MASK 0
55
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#define CHCR_TS_HIGH_SHIFT 0
56
+
#endif
57
+
58
+
/* Transmit sizes and respective CHCR register values */
59
+
enum {
60
+
XMIT_SZ_8BIT = 0,
61
+
XMIT_SZ_16BIT = 1,
62
+
XMIT_SZ_32BIT = 2,
63
+
XMIT_SZ_64BIT = 7,
64
+
XMIT_SZ_128BIT = 3,
65
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XMIT_SZ_256BIT = 4,
66
+
XMIT_SZ_128BIT_BLK = 0xb,
67
+
XMIT_SZ_256BIT_BLK = 0xc,
68
+
};
69
+
70
+
/* log2(size / 8) - used to calculate number of transfers */
71
+
#define TS_SHIFT { \
72
+
[XMIT_SZ_8BIT] = 0, \
73
+
[XMIT_SZ_16BIT] = 1, \
74
+
[XMIT_SZ_32BIT] = 2, \
75
+
[XMIT_SZ_64BIT] = 3, \
76
+
[XMIT_SZ_128BIT] = 4, \
77
+
[XMIT_SZ_256BIT] = 5, \
78
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[XMIT_SZ_128BIT_BLK] = 4, \
79
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[XMIT_SZ_256BIT_BLK] = 5, \
80
+
}
81
+
82
+
#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
83
+
((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
84
+
85
+
#else /* CONFIG_CPU_SH4A */
86
+
87
+
#define DMAOR_INIT (0x8000 | DMAOR_DME)
88
+
89
+
#define CHCR_TS_LOW_MASK 0x70
90
+
#define CHCR_TS_LOW_SHIFT 4
91
+
#define CHCR_TS_HIGH_MASK 0
92
+
#define CHCR_TS_HIGH_SHIFT 0
93
+
94
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/* Transmit sizes and respective CHCR register values */
95
+
enum {
96
+
XMIT_SZ_8BIT = 1,
97
+
XMIT_SZ_16BIT = 2,
98
+
XMIT_SZ_32BIT = 3,
99
+
XMIT_SZ_64BIT = 0,
100
+
XMIT_SZ_256BIT = 4,
101
+
};
102
+
103
+
/* log2(size / 8) - used to calculate number of transfers */
104
+
#define TS_SHIFT { \
105
+
[XMIT_SZ_8BIT] = 0, \
106
+
[XMIT_SZ_16BIT] = 1, \
107
+
[XMIT_SZ_32BIT] = 2, \
108
+
[XMIT_SZ_64BIT] = 3, \
109
+
[XMIT_SZ_256BIT] = 5, \
110
+
}
111
+
112
+
#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
113
+
114
+
#endif /* CONFIG_CPU_SH4A */
115
+
116
+
#endif
-62
arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
-62
arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
···
8
8
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
9
9
#define SH_DMAC_BASE0 0xFE008020
10
10
#define SH_DMARS_BASE0 0xFE009000
11
-
#define CHCR_TS_LOW_MASK 0x00000018
12
-
#define CHCR_TS_LOW_SHIFT 3
13
-
#define CHCR_TS_HIGH_MASK 0
14
-
#define CHCR_TS_HIGH_SHIFT 0
15
11
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
16
12
#define DMTE0_IRQ 48
17
13
#define DMTE4_IRQ 76
18
14
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
19
15
#define SH_DMAC_BASE0 0xFE008020
20
16
#define SH_DMARS_BASE0 0xFE009000
21
-
#define CHCR_TS_LOW_MASK 0x00000018
22
-
#define CHCR_TS_LOW_SHIFT 3
23
-
#define CHCR_TS_HIGH_MASK 0x00300000
24
-
#define CHCR_TS_HIGH_SHIFT 20
25
17
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26
18
defined(CONFIG_CPU_SUBTYPE_SH7764)
27
19
#define DMTE0_IRQ 34
···
21
29
#define DMAE0_IRQ 38
22
30
#define SH_DMAC_BASE0 0xFF608020
23
31
#define SH_DMARS_BASE0 0xFF609000
24
-
#define CHCR_TS_LOW_MASK 0x00000018
25
-
#define CHCR_TS_LOW_SHIFT 3
26
-
#define CHCR_TS_HIGH_MASK 0
27
-
#define CHCR_TS_HIGH_SHIFT 0
28
32
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
29
33
#define DMTE0_IRQ 48 /* DMAC0A*/
30
34
#define DMTE4_IRQ 76 /* DMAC0B */
···
34
46
#define SH_DMAC_BASE0 0xFE008020
35
47
#define SH_DMAC_BASE1 0xFDC08020
36
48
#define SH_DMARS_BASE0 0xFDC09000
37
-
#define CHCR_TS_LOW_MASK 0x00000018
38
-
#define CHCR_TS_LOW_SHIFT 3
39
-
#define CHCR_TS_HIGH_MASK 0
40
-
#define CHCR_TS_HIGH_SHIFT 0
41
49
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
42
50
#define DMTE0_IRQ 48 /* DMAC0A*/
43
51
#define DMTE4_IRQ 76 /* DMAC0B */
···
48
64
#define SH_DMAC_BASE1 0xFDC08020
49
65
#define SH_DMARS_BASE0 0xFE009000
50
66
#define SH_DMARS_BASE1 0xFDC09000
51
-
#define CHCR_TS_LOW_MASK 0x00000018
52
-
#define CHCR_TS_LOW_SHIFT 3
53
-
#define CHCR_TS_HIGH_MASK 0x00600000
54
-
#define CHCR_TS_HIGH_SHIFT 21
55
67
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
56
68
#define DMTE0_IRQ 34
57
69
#define DMTE4_IRQ 44
···
60
80
#define SH_DMAC_BASE0 0xFC808020
61
81
#define SH_DMAC_BASE1 0xFC818020
62
82
#define SH_DMARS_BASE0 0xFC809000
63
-
#define CHCR_TS_LOW_MASK 0x00000018
64
-
#define CHCR_TS_LOW_SHIFT 3
65
-
#define CHCR_TS_HIGH_MASK 0
66
-
#define CHCR_TS_HIGH_SHIFT 0
67
83
#else /* SH7785 */
68
84
#define DMTE0_IRQ 33
69
85
#define DMTE4_IRQ 37
···
73
97
#define SH_DMAC_BASE0 0xFC808020
74
98
#define SH_DMAC_BASE1 0xFCC08020
75
99
#define SH_DMARS_BASE0 0xFC809000
76
-
#define CHCR_TS_LOW_MASK 0x00000018
77
-
#define CHCR_TS_LOW_SHIFT 3
78
-
#define CHCR_TS_HIGH_MASK 0
79
-
#define CHCR_TS_HIGH_SHIFT 0
80
100
#endif
81
101
82
102
#define REQ_HE 0x000000C0
83
103
#define REQ_H 0x00000080
84
104
#define REQ_LE 0x00000040
85
105
#define TM_BURST 0x00000020
86
-
87
-
/*
88
-
* The SuperH DMAC supports a number of transmit sizes, we list them here,
89
-
* with their respective values as they appear in the CHCR registers.
90
-
*
91
-
* Defaults to a 64-bit transfer size.
92
-
*/
93
-
enum {
94
-
XMIT_SZ_8BIT = 0,
95
-
XMIT_SZ_16BIT = 1,
96
-
XMIT_SZ_32BIT = 2,
97
-
XMIT_SZ_64BIT = 7,
98
-
XMIT_SZ_128BIT = 3,
99
-
XMIT_SZ_256BIT = 4,
100
-
XMIT_SZ_128BIT_BLK = 0xb,
101
-
XMIT_SZ_256BIT_BLK = 0xc,
102
-
};
103
-
104
-
/*
105
-
* The DMA count is defined as the number of bytes to transfer.
106
-
*/
107
-
#define TS_SHIFT { \
108
-
[XMIT_SZ_8BIT] = 0, \
109
-
[XMIT_SZ_16BIT] = 1, \
110
-
[XMIT_SZ_32BIT] = 2, \
111
-
[XMIT_SZ_64BIT] = 3, \
112
-
[XMIT_SZ_128BIT] = 4, \
113
-
[XMIT_SZ_256BIT] = 5, \
114
-
[XMIT_SZ_128BIT_BLK] = 4, \
115
-
[XMIT_SZ_256BIT_BLK] = 5, \
116
-
}
117
-
118
-
#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
119
-
((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
120
106
121
107
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
+1
-35
arch/sh/include/cpu-sh4/cpu/dma.h
+1
-35
arch/sh/include/cpu-sh4/cpu/dma.h
···
5
5
6
6
#ifdef CONFIG_CPU_SH4A
7
7
8
-
#define DMAOR_INIT (DMAOR_DME)
9
-
10
8
#include <cpu/dma-sh4a.h>
9
+
11
10
#else /* CONFIG_CPU_SH4A */
12
11
/*
13
12
* SH7750/SH7751/SH7760
···
16
17
#define DMTE6_IRQ 46
17
18
#define DMAE0_IRQ 38
18
19
19
-
#define DMAOR_INIT (0x8000|DMAOR_DME)
20
20
#define SH_DMAC_BASE0 0xffa00000
21
21
#define SH_DMAC_BASE1 0xffa00070
22
22
/* Definitions for the SuperH DMAC */
···
25
27
#define TS_32 0x00000030
26
28
#define TS_64 0x00000000
27
29
28
-
#define CHCR_TS_LOW_MASK 0x70
29
-
#define CHCR_TS_LOW_SHIFT 4
30
-
#define CHCR_TS_HIGH_MASK 0
31
-
#define CHCR_TS_HIGH_SHIFT 0
32
-
33
30
#define DMAOR_COD 0x00000008
34
-
35
-
/*
36
-
* The SuperH DMAC supports a number of transmit sizes, we list them here,
37
-
* with their respective values as they appear in the CHCR registers.
38
-
*
39
-
* Defaults to a 64-bit transfer size.
40
-
*/
41
-
enum {
42
-
XMIT_SZ_8BIT = 1,
43
-
XMIT_SZ_16BIT = 2,
44
-
XMIT_SZ_32BIT = 3,
45
-
XMIT_SZ_64BIT = 0,
46
-
XMIT_SZ_256BIT = 4,
47
-
};
48
-
49
-
/*
50
-
* The DMA count is defined as the number of bytes to transfer.
51
-
*/
52
-
#define TS_SHIFT { \
53
-
[XMIT_SZ_8BIT] = 0, \
54
-
[XMIT_SZ_16BIT] = 1, \
55
-
[XMIT_SZ_32BIT] = 2, \
56
-
[XMIT_SZ_64BIT] = 3, \
57
-
[XMIT_SZ_256BIT] = 5, \
58
-
}
59
-
60
-
#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
61
31
62
32
#endif
63
33
+16
-4
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+16
-4
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
···
7
7
* License. See the file "COPYING" in the main directory of this archive
8
8
* for more details.
9
9
*/
10
-
#include <linux/platform_device.h>
11
10
#include <linux/init.h>
11
+
#include <linux/mm.h>
12
+
#include <linux/platform_device.h>
12
13
#include <linux/serial.h>
13
14
#include <linux/serial_sci.h>
14
-
#include <linux/mm.h>
15
+
#include <linux/sh_timer.h>
15
16
#include <linux/uio_driver.h>
16
17
#include <linux/usb/m66592.h>
17
-
#include <linux/sh_timer.h>
18
+
18
19
#include <asm/clock.h>
20
+
#include <asm/dmaengine.h>
19
21
#include <asm/mmzone.h>
20
-
#include <asm/dma-sh.h>
21
22
#include <asm/siu.h>
23
+
24
+
#include <cpu/dma-register.h>
22
25
#include <cpu/sh7722.h>
23
26
24
27
static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
···
106
103
}
107
104
};
108
105
106
+
static unsigned int ts_shift[] = TS_SHIFT;
107
+
109
108
static struct sh_dmae_pdata dma_platform_data = {
110
109
.slave = sh7722_dmae_slaves,
111
110
.slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
112
111
.channel = sh7722_dmae_channels,
113
112
.channel_num = ARRAY_SIZE(sh7722_dmae_channels),
113
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
114
+
.ts_low_mask = CHCR_TS_LOW_MASK,
115
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
116
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
117
+
.ts_shift = ts_shift,
118
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
119
+
.dmaor_init = DMAOR_INIT,
114
120
};
115
121
116
122
static struct resource sh7722_dmae_resources[] = {
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
···
21
21
#include <linux/sh_timer.h>
22
22
#include <linux/io.h>
23
23
#include <linux/notifier.h>
24
+
24
25
#include <asm/suspend.h>
25
26
#include <asm/clock.h>
26
-
#include <asm/dma-sh.h>
27
+
#include <asm/dmaengine.h>
27
28
#include <asm/mmzone.h>
29
+
30
+
#include <cpu/dma-register.h>
28
31
#include <cpu/sh7724.h>
29
32
30
33
/* DMA */
···
87
84
}
88
85
};
89
86
87
+
static unsigned int ts_shift[] = TS_SHIFT;
88
+
90
89
static struct sh_dmae_pdata dma0_platform_data = {
91
90
.channel = sh7724_dmae0_channels,
92
91
.channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
92
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
93
+
.ts_low_mask = CHCR_TS_LOW_MASK,
94
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
95
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
96
+
.ts_shift = ts_shift,
97
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
98
+
.dmaor_init = DMAOR_INIT,
93
99
};
94
100
95
101
static struct sh_dmae_pdata dma1_platform_data = {
96
102
.channel = sh7724_dmae1_channels,
97
103
.channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
104
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
105
+
.ts_low_mask = CHCR_TS_LOW_MASK,
106
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
107
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
108
+
.ts_shift = ts_shift,
109
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
110
+
.dmaor_init = DMAOR_INIT,
98
111
};
99
112
100
113
/* Resource order important! */
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
···
13
13
#include <linux/io.h>
14
14
#include <linux/serial_sci.h>
15
15
#include <linux/sh_timer.h>
16
-
#include <asm/dma-sh.h>
16
+
17
+
#include <asm/dmaengine.h>
18
+
19
+
#include <cpu/dma-register.h>
17
20
18
21
static struct plat_sci_port scif0_platform_data = {
19
22
.mapbase = 0xffe00000,
···
295
292
}
296
293
};
297
294
295
+
static unsigned int ts_shift[] = TS_SHIFT;
296
+
298
297
static struct sh_dmae_pdata dma0_platform_data = {
299
298
.channel = sh7780_dmae0_channels,
300
299
.channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
300
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
301
+
.ts_low_mask = CHCR_TS_LOW_MASK,
302
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
303
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
304
+
.ts_shift = ts_shift,
305
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
306
+
.dmaor_init = DMAOR_INIT,
301
307
};
302
308
303
309
static struct sh_dmae_pdata dma1_platform_data = {
304
310
.channel = sh7780_dmae1_channels,
305
311
.channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
312
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
313
+
.ts_low_mask = CHCR_TS_LOW_MASK,
314
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
315
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
316
+
.ts_shift = ts_shift,
317
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
318
+
.dmaor_init = DMAOR_INIT,
306
319
};
307
320
308
321
static struct resource sh7780_dmae0_resources[] = {
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+20
-1
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
···
14
14
#include <linux/io.h>
15
15
#include <linux/mm.h>
16
16
#include <linux/sh_timer.h>
17
-
#include <asm/dma-sh.h>
17
+
18
+
#include <asm/dmaengine.h>
18
19
#include <asm/mmzone.h>
20
+
21
+
#include <cpu/dma-register.h>
19
22
20
23
static struct plat_sci_port scif0_platform_data = {
21
24
.mapbase = 0xffea0000,
···
343
340
}
344
341
};
345
342
343
+
static unsigned int ts_shift[] = TS_SHIFT;
344
+
346
345
static struct sh_dmae_pdata dma0_platform_data = {
347
346
.channel = sh7785_dmae0_channels,
348
347
.channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
348
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
349
+
.ts_low_mask = CHCR_TS_LOW_MASK,
350
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
351
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
352
+
.ts_shift = ts_shift,
353
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
354
+
.dmaor_init = DMAOR_INIT,
349
355
};
350
356
351
357
static struct sh_dmae_pdata dma1_platform_data = {
352
358
.channel = sh7785_dmae1_channels,
353
359
.channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
360
+
.ts_low_shift = CHCR_TS_LOW_SHIFT,
361
+
.ts_low_mask = CHCR_TS_LOW_MASK,
362
+
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
363
+
.ts_high_mask = CHCR_TS_HIGH_MASK,
364
+
.ts_shift = ts_shift,
365
+
.ts_shift_num = ARRAY_SIZE(ts_shift),
366
+
.dmaor_init = DMAOR_INIT,
354
367
};
355
368
356
369
static struct resource sh7785_dmae0_resources[] = {
+49
-30
drivers/dma/shdma.c
+49
-30
drivers/dma/shdma.c
···
24
24
#include <linux/delay.h>
25
25
#include <linux/dma-mapping.h>
26
26
#include <linux/platform_device.h>
27
-
#include <cpu/dma.h>
28
-
#include <asm/dma-sh.h>
27
+
#include <asm/dmaengine.h>
29
28
#include "shdma.h"
30
29
31
30
/* DMA descriptor control */
···
37
38
};
38
39
39
40
#define NR_DESCS_PER_CHANNEL 32
40
-
/*
41
-
* Define the default configuration for dual address memory-memory transfer.
42
-
* The 0x400 value represents auto-request, external->external.
43
-
*
44
-
* And this driver set 4byte burst mode.
45
-
* If you want to change mode, you need to change RS_DEFAULT of value.
46
-
* (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
47
-
*/
48
-
#define RS_DEFAULT (RS_DUAL)
41
+
/* Default MEMCPY transfer size = 2^2 = 4 bytes */
42
+
#define LOG2_DEFAULT_XFER_SIZE 2
49
43
50
44
/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
51
45
static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
···
82
90
unsigned short dmaor;
83
91
84
92
sh_dmae_ctl_stop(shdev);
85
-
dmaor = dmaor_read(shdev) | DMAOR_INIT;
93
+
dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
86
94
87
95
dmaor_write(shdev, dmaor);
88
96
if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
···
102
110
return false; /* waiting */
103
111
}
104
112
105
-
static unsigned int ts_shift[] = TS_SHIFT;
106
-
static inline unsigned int calc_xmit_shift(u32 chcr)
113
+
static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
107
114
{
108
-
int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
109
-
((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
115
+
struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
116
+
struct sh_dmae_device, common);
117
+
struct sh_dmae_pdata *pdata = shdev->pdata;
118
+
int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
119
+
((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
110
120
111
-
return ts_shift[cnt];
121
+
if (cnt >= pdata->ts_shift_num)
122
+
cnt = 0;
123
+
124
+
return pdata->ts_shift[cnt];
125
+
}
126
+
127
+
static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
128
+
{
129
+
struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
130
+
struct sh_dmae_device, common);
131
+
struct sh_dmae_pdata *pdata = shdev->pdata;
132
+
int i;
133
+
134
+
for (i = 0; i < pdata->ts_shift_num; i++)
135
+
if (pdata->ts_shift[i] == l2size)
136
+
break;
137
+
138
+
if (i == pdata->ts_shift_num)
139
+
i = 0;
140
+
141
+
return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
142
+
((i << pdata->ts_high_shift) & pdata->ts_high_mask);
112
143
}
113
144
114
145
static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
···
159
144
160
145
static void dmae_init(struct sh_dmae_chan *sh_chan)
161
146
{
162
-
u32 chcr = RS_DEFAULT; /* default is DUAL mode */
163
-
sh_chan->xmit_shift = calc_xmit_shift(chcr);
147
+
/*
148
+
* Default configuration for dual address memory-memory transfer.
149
+
* 0x400 represents auto-request.
150
+
*/
151
+
u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
152
+
LOG2_DEFAULT_XFER_SIZE);
153
+
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
164
154
sh_dmae_writel(sh_chan, chcr, CHCR);
165
155
}
166
156
···
175
155
if (dmae_is_busy(sh_chan))
176
156
return -EBUSY;
177
157
178
-
sh_chan->xmit_shift = calc_xmit_shift(val);
158
+
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
179
159
sh_dmae_writel(sh_chan, val, CHCR);
180
160
181
161
return 0;
···
305
285
306
286
dmae_set_dmars(sh_chan, cfg->mid_rid);
307
287
dmae_set_chcr(sh_chan, cfg->chcr);
308
-
} else {
309
-
if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400)
310
-
dmae_set_chcr(sh_chan, RS_DEFAULT);
288
+
} else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
289
+
dmae_init(sh_chan);
311
290
}
312
291
313
292
spin_lock_bh(&sh_chan->desc_lock);
···
776
757
sh_dmae_ctl_stop(shdev);
777
758
778
759
/* We cannot detect, which channel caused the error, have to reset all */
779
-
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
760
+
for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
780
761
struct sh_dmae_chan *sh_chan = shdev->chan[i];
781
762
if (sh_chan) {
782
763
struct sh_desc *desc;
···
841
822
return -ENOMEM;
842
823
}
843
824
825
+
/* copy struct dma_device */
826
+
new_sh_chan->common.device = &shdev->common;
827
+
844
828
new_sh_chan->dev = shdev->common.dev;
845
829
new_sh_chan->id = id;
846
830
new_sh_chan->irq = irq;
···
861
839
/* Init descripter manage list */
862
840
INIT_LIST_HEAD(&new_sh_chan->ld_queue);
863
841
INIT_LIST_HEAD(&new_sh_chan->ld_free);
864
-
865
-
/* copy struct dma_device */
866
-
new_sh_chan->common.device = &shdev->common;
867
842
868
843
/* Add the channel to DMA device channel list */
869
844
list_add_tail(&new_sh_chan->common.device_node,
···
915
896
{
916
897
struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
917
898
unsigned long irqflags = IRQF_DISABLED,
918
-
chan_flag[MAX_DMA_CHANNELS] = {};
919
-
int errirq, chan_irq[MAX_DMA_CHANNELS];
899
+
chan_flag[SH_DMAC_MAX_CHANNELS] = {};
900
+
int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
920
901
int err, i, irq_cnt = 0, irqres = 0;
921
902
struct sh_dmae_device *shdev;
922
903
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
···
1002
983
1003
984
shdev->common.dev = &pdev->dev;
1004
985
/* Default transfer size of 32 bytes requires 32-byte alignment */
1005
-
shdev->common.copy_align = 5;
986
+
shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1006
987
1007
988
#if defined(CONFIG_CPU_SH4)
1008
989
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+3
-1
drivers/dma/shdma.h
+3
-1
drivers/dma/shdma.h
···
17
17
#include <linux/interrupt.h>
18
18
#include <linux/list.h>
19
19
20
+
#include <asm/dmaengine.h>
21
+
20
22
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
21
23
22
24
struct sh_dmae_regs {
···
57
55
58
56
struct sh_dmae_device {
59
57
struct dma_device common;
60
-
struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
58
+
struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
61
59
struct sh_dmae_pdata *pdata;
62
60
u32 __iomem *chan_reg;
63
61
u16 __iomem *dmars;
+1
-1
sound/soc/sh/siu.h
+1
-1
sound/soc/sh/siu.h