Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
[Blackfin] arch: Enable UART2 and UART3 for bf548
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
authored by Sonic Zhang and committed by Bryan Wu 8b01eaff 83d9cde0
+10
arch/blackfin/kernel/bfin_dma_5xx.c
+10
arch/blackfin/kernel/bfin_dma_5xx.c
···
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mutex_unlock(&(dma_ch[channel].dmalock));
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#ifdef CONFIG_BF54x
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if (channel >= CH_UART2_RX && channel <= CH_UART3_TX &&
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strncmp(device_id, "BFIN_UART", 9) == 0)
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dma_ch[channel].regs->peripheral_map |=
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(channel - CH_UART2_RX + 0xC);
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else
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dma_ch[channel].regs->peripheral_map |=
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(channel - CH_UART2_RX + 0x6);
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#endif
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dma_ch[channel].device_id = device_id;
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dma_ch[channel].irq_callback = NULL;
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include/asm-blackfin/mach-bf548/dma.h
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include/asm-blackfin/mach-bf548/dma.h
···
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#define CH_PIXC_OVERLAY 16
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#define CH_PIXC_OUTPUT 17
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#define CH_SPORT2_RX 18
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#define CH_UART2_RX 18
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#define CH_SPORT2_TX 19
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#define CH_UART2_TX 19
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#define CH_SPORT3_RX 20
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#define CH_UART3_RX 20
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#define CH_SPORT3_TX 21
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#define CH_UART3_TX 21
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#define CH_SDH 22
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#define CH_NFC 22
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#define CH_SPI2 23
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include/asm-blackfin/mach-bf548/irq.h
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include/asm-blackfin/mach-bf548/irq.h
···
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#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
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#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
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#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
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#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
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#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
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#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
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#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
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#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
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#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
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#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
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#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
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#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
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#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
···
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/* IAR4 BIT FILEDS */
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#define IRQ_CAN0_ERR_POS 0
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#define IRQ_SPORT2_RX_POS 4
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#define IRQ_UART2_RX_POS 4
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#define IRQ_SPORT2_TX_POS 8
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#define IRQ_UART2_TX_POS 8
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#define IRQ_SPORT3_RX_POS 12
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#define IRQ_UART3_RX_POS 12
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#define IRQ_SPORT3_TX_POS 16
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#define IRQ_UART3_TX_POS 16
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#define IRQ_EPPI1_POS 20
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#define IRQ_EPPI2_POS 24
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#define IRQ_SPI1_POS 28